Commit Graph

36905 Commits

Author SHA1 Message Date
Maxim Polyakov 22bf6fbcba mb/51nb/x210/gpio: 1/4 Decode raw register values
Use the intelp2m utility [1,2] with -fld=cb options to convert the pad
configuration format with the raw values of the DW0 and DW1 registers
to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(),
PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc...

./intelp2m -fld cb -t 1 -file ../../src/mainboard/51nb/x210/gpio.h

This is part of the patch set
"mb/51nb/x210/gpio: Rewrite pad config using intelp2m":

CB:43566 - 1/4 Decode raw register values
CB:43567 - 2/4 Exclude fields for PAD_CFG
CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC()
CB:43410 - 4/4 Convert field macros to PAD_CFG

Tested with BUILD_TIMELESS=1, 51NB-X210, remains identical.

[1] https://github.com/maxpoliak/pch-pads-parser
[2] https://review.coreboot.org/c/coreboot/+/35643

Change-Id: I19282c985cf35a9f99be449915aa9bab7e03472d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43566
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21 08:08:26 +00:00
Maxim Polyakov 0a6f82835e util/intelp2m: Check keywords in common code
TEST = ./intelp2m -n -file inteltool.log;
       ./intelp2m -fld cb -file inteltool.log;
       ./intelp2m -fld fsp -file inteltool.log;
       ./intelp2m -fld raw -file inteltool.log.
       Before and after the patch, gpio.h is no different.

Change-Id: I8af28960e41fcb97f03fe97c42cdddde07b3615a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21 08:07:26 +00:00
Caveh Jalali 85e4c43b02 volteer: set GSPI CS to deasserted by default
This sets the state of GSPI chip select to 1 (deasserted) as applied
by the FSP during the silicon init phase. GSPI 0 and 1 are set to CS
mode manual in the SerialIoGSpiCsMode section which means we need to
explicitly configure CS to deasserted in the SerialIoGSpiCsState
section. GSPI0 is the CR50 and GSPI1 is the fingerprint sensor. We
were running into problems where the normal expected CS toggle
sequence to wake up CR50 did not work because CS was already asserted
when it was expected to be deasserted, leading to TPM timeouts.

BUG=b:168090038
TEST=booted on volteer, no more "TPM flow control failure" messages;
	verified fingerprint enrollment still works.

Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45384
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21 08:07:13 +00:00
Frank Wu 362bcee0f4 mb/google/volteer: Add firmware configuration for MAX98373_ALC5682I_I2S_UP4
Add MAX98373_ALC5682I_I2S_UP4 firmware configuration option and configure GPIOs properly for UP4 design. The design is also for Halvor.

BUG=b:153680359, b:163382106
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage, fw_config value in Halvor:
> AUDIO=MAX98373_ALC5682I_I2S_UP4
ectool cbi set 6 0x00000400 4 2

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ie25f278dfbdc2f41a36b70403699a2e3c2234600
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-21 08:06:38 +00:00
Rocky Phagura cced3469c5 soc/intel/xeon_sp: Enable PMC support
PMC support was not enabled on Xeon_sp platforms. This involves turning
on SOC_INTEL_COMMON_BLOCK_PMC and then adding the proper hooks in SOC
specific code.  This patch leverages code from the Skylake project and
adds the bare minimum hooks to leverage PMC common code. Most
importantly this enables power management registers located in the PMC
device (under ACPI_BASE_ADDRESS). Access to this device is also needed
for SMM setup and handling.

TEST=build for Tiogapass and enable the following Kconfig options:
	select SOC_INTEL_COMMON_BLOCK_PMC
	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
        select CPU_INTEL_COMMON_SMM

Boot the system and ensure pmbase is programmed. (Look for pmbase in
debug messages). Secondly check that SMIs are enabled by looking at the
debug messages (search for "Enabling SMIs") and verifying in HW by
reading IO port 0x530.

Change-Id: I6d57a8282a8b6dc4314f156c39deb09535575cbd
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-09-21 08:06:23 +00:00
Jonathan Zhang bb25c59e90 soc/intel/xeon_sp/cpx: search IIO_UDS HOB once when creating DMAR table
IIO_UDS HOB was searched several times during the creation of DMAR table.
Reduce it to only once to improve boot time.

Both DRHD and ATSR subtable creations involve addition of PCIe bridge
device entries, combine the functions with
acpi_create_dmar_ds_pci_br_for_port().

When looping through ports to create PCIe bridge device entries,
use MAX_PORTS intead of NUMBER_PORTS_PER_SOCKET to improve boot time.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I469cd8473c50e105daeda6c5607592ae7cef6032
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-09-21 08:06:09 +00:00
Jonathan Zhang 3bfd3cfdee soc/intel/xeon_sp/cpx: remove DMAR_X2APIC_OPT_OUT flag
CPX-SP processor supports X2APIC.

Remove DMAR_X2APIC_OPT_OUT flag from DMAR table.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I63c9feda74c7abb591eac991cb98cdcad8afc158
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45375
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21 08:05:58 +00:00
Angel Pons eb53793fdb nb/intel/ironlake: Clean up cosmetics of early ME functions
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: Ic766345b58c59f3d3c3570741c0eb0ad4e53ed79
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-21 08:05:22 +00:00
Angel Pons 55f11e29e4 nb/intel/ironlake: Clean up `send_heci_uma_message` signature
The only raminfo field it needs is `memory_reserved_for_heci_mb`. So,
pass in that value directly. As it's read-only, make it const as well.

Change-Id: Ib5d4604e6c1c9bc77df9adfead93b6028d536a3d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45365
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21 08:04:57 +00:00
Angel Pons 36592bfe40 nb/intel/ironlake: Reduce the scope of `heci_uma_addr`
There's no need to have it in raminfo. Also, bump MRC_CACHE_VERSION.

Change-Id: Ida48ec4f50c880fe48d88d016acd3737a0650f80
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45364
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21 08:04:43 +00:00
Angel Pons 2f60c83f44 nb/intel/sandybridge: Drop unnecessary `gma.h`
It only contains prototypes for the long-gone native graphics init.

Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.

Change-Id: I9413abb8e49496ada60dcdf801a1f8a03be38d2e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45360
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21 08:04:26 +00:00
Angel Pons b8ebeba4a2 nb/intel/sandybridge: Put DMIBAR/EPBAR registers into separate files
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.

Change-Id: I836df4675f4886635973c0c75f5981c9ef17d84b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45359
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21 08:04:00 +00:00
Angel Pons 3447db5fe4 nb/intel/sandybridge: Move register headers into a subfolder
Move all files with register definitions into a `registers` subfolder.
Subsequent commits will move the remaining registers into this folder.

Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.

Change-Id: Ie525e755f32599db97af7969fc7fbb36a5d826b6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45358
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21 08:03:42 +00:00
Angel Pons f950a7ec67 nb/intel/sandybridge: Clean up DMIBAR/EPBAR registers
Several registers have been copy-pasted from i945 and do not exist on
Sandy Bridge. Moreover, other register definitions were missing. Use the
newly-added definitions in existing code, in place of numerical offsets.

Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.

Change-Id: I9ad849f57bc68256a2a87ffdc856c4b521e35892
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45357
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21 08:03:24 +00:00
Angel Pons dfca1697fc nb/intel/sandybridge: Introduce memmap.h
Move all memory map definitions into a separate header.

Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.

Change-Id: I7f2ff2a5cee8bf12e5dca74ff9f0b1a44e26cded
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45356
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21 08:03:06 +00:00
Duncan Laurie 14efbb464e mb/google/volteer: fw_config: Add fields for keyboard features
Add newly defined fields for presence of keyboard backlight and
number pad to the firmware configuration table.

We don't have a need to use these in coreboot (yet) but this
keeps the bit definitions in sync.

BUG=b:166707536
TEST=abuild -t google/volteer

Change-Id: I066e445f7d0be056e45737d2c538be1850ae85aa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-21 08:02:50 +00:00
V Sowmya 3fc368d09b soc/intel/jsl: Use the common code to set the PchPmPwrCycDur
This patch uses the common code to avoid violating the PCH EDS
recommendation for the PchPmPwrCycDur setting.

Change-Id: I8aba558082ff5bbe2c5b12e0e623c013548e6481
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45030
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21 08:02:34 +00:00
V Sowmya 27413d3219 soc/intel/cnl: Use the common code to set the PchPmPwrCycDur
This patch uses the common code to avoid violating the PCH EDS
recommendation for the PchPmPwrCycDur setting.

Change-Id: Id418480bc779d56ff5586516d9bd99ca15133203
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45029
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21 08:02:30 +00:00
Harshit Sharma d8a722cb61 Documentation: Add ASan documentation
Change-Id: I710ea495798597189941620c7e48fd5aa7476781
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-21 07:45:37 +00:00
Michael Niewöhner 3f5bfbd4d1 mb/system76/lemp9: move LPC options to the devicetree
Change-Id: I7b7acdc51c848541fb39926bc8de1115c026dd05
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45496
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20 21:32:50 +00:00
Michael Niewöhner 80bd8e43b0 mb/system76/lemp9: correct CBFS_SIZE
The BIOS region size is 0xc00000, not 0xa00000. Correct this.

Change-Id: I88cb0d4b9a590a32672054aa0db7f9a92070ff6d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-09-20 21:32:32 +00:00
Michael Niewöhner 8b5cd49b5a mb/system76/lemp9: enable SATA ALPM capability
Enable SATA Link Power Management capability to be able to save power.

TEST: /sys/class/scsi_host/host*/link_power_management_policy exists.

Change-Id: I88de28cfb266af3fcd6e498a08a24b46c992cb9d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45492
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20 21:32:21 +00:00
Michael Niewöhner c9ebf8d501 mb/system76/lemp9: drop disabled options from devicetree
Drop all options with zero-value, since they already default to 0.

Change-Id: I2a1a91778e83dc49c6dcf2d518cd3591f7ec4cfa
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45491
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20 21:32:11 +00:00
Kevin Chiu 1c065b311b mb/google/zork: update morphius dptc clamshell/tablet mode setting
clamshell/tablet:
Slow_ppt_limit(W)		20
Fast_ppt_limit(W)		24
Slow_ppt_time_constant		5
Stapm_time_constant		200
Sustained_power_limit(W)	12

clamshell:
Temperature limit(C')		100

tablet:
Temperature limit(C')		70

BUG=b:157943445
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. change mode and check "thermctl_limit" will change

Change-Id: I1eda1411766e446b673046236f7cc4015696521f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45520
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20 17:25:15 +00:00
Kevin Chiu cdd9f5cb72 soc/amd/picasso: Add THERMCTL_LIMIT DPTC parameter support
Add THERMCTL_LIMIT (die temperature limit) DPTC parameter
for clamshell/tablet mode.

BUG=b:157943445
BRANCH=zork
TEST=build

Change-Id: Id193a74210c92d1e45ed4824ee9c0fc9ceaa5e3a
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-20 17:24:40 +00:00
Michael Niewöhner e0d749c23b lint: check for misuse of Kconfig SUBSYSTEM_*_ID
Check that nobody misuses the Kconfigs SUBSYSTEM_*_ID. They are meant to
be used for overriding the devicetree subsystem ids locally but shall
not be added to a board's Kconfig. Instead, the devicetree option
`subsystemid` should be used.

Add a linter script for this that finds and warns about such misuse.

Also add a note in the Kconfigs' description.

TEST=CB:45513

Change-Id: I21c021c718154f1396f795a555af47a76d6efe03
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-20 17:03:32 +00:00
Zheng Bao 6252b601c9 soc/amd/picasso: Fix typo of Kconfig setting
USE_PSPSCUREOS -> USE_PSPSECUREOS.

Change-Id: I5c89975cc317cb93e79509e885010d14a79dd7e1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-20 02:47:27 +00:00
Michael Niewöhner 5a85d134b1 mb/system76/lemp9: move subsystem id from Kconfig to devicetree
Change-Id: I21e7e53787b115f50093d7caa72285ce480cef52
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-19 16:46:54 +00:00
Michael Niewöhner 1c661b92bc mb/up/squared: move subsystem id from Kconfig to devicetree
Change-Id: Icf62a73ee568d9369c53bd767bd4cfb736ea76f1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-19 16:46:34 +00:00
Subrata Banik f463dc0947 soc/intel/common/block/cse: Refactor cse_request_global_reset() function
List of changes:
1. Check if CSE is enabled from devicetree.cb
2. Create helper function cse_request_reset()
3. Modify caller function argument cse_request_global_reset()

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I3668b473bec8d51f847908d11e2e25c485ec7a97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45341
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-19 06:37:37 +00:00
Subrata Banik e9b937352e apollolake boards: Enable CSE in devicetree
Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let
Intel common cse block code can use this device.

Calling me_read_config32(offset) function from ramstage:

Without this CL :
HECI: Global Reset(Type:1) Command
BUG: me_read_config32 requests hidden 00:0f.0
PCI: dev is NULL!

With this CL :
HECI: Global Reset(Type:1) Command
HECI: Global Reset success!

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-19 06:37:24 +00:00
Hsuan Ting Chen 8742e2a923 libpayload: free: Separate NULL check out for clarity
Separate the validity check of calling free(NULL) for clarity.

BUG=b:168441735
TEST=emerge-puff libpayload

Change-Id: I0dc355553410bbe59e658945fb40c05f5f709380
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-19 01:36:57 +00:00
Duncan Laurie cbd0bd8155 sconfig: Add function for parse+override of tree
Extract the steps to parse and override a devicetree into a function
so it can be used multiple times without copying the same logic.

Change-Id: I4e496a223757beb22e3bd678eb6115968bd32529
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-18 22:41:56 +00:00
Julius Werner 7a066ecb41 trogdor: Move EN_PP3300_DX_EDP for Coachz
This patch updates the display power enable GPIO which moved from 30 to
52 for Coachz. Veterans of this project know that there's no point
trying to ask *why* this change was necessary -- the pins move in
mysterious ways and all we can do is watch and wonder. Pin 30 is now
used for a new camera reset GPIO... surely, there must have been some
excellent reason why that pin couldn't just have become pin 52 instead.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I00ad6a6249df66006b4f2b953a0a2449bd478f6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
2020-09-18 21:18:52 +00:00
Duncan Laurie 51c8373593 sconfig: Switch to getopt
Instead of positional arguments switch sconfig to use getopt and pass
the arguments as options in the build system.  This will make it easier
to add additional options.

Change-Id: I431633781e80362e086c000b7108191b5b01aa9d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-18 17:50:00 +00:00
Eric Lai 0647f614cd mb/google/octopus/variants/fleex: support LTE power sequence
GPIOs related to power sequence are
  GPIO_67  - EN_PP3300
  GPIO_117 - FULL_CARD_POWER_ON_OFF
  GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
  - keep GPIO_67 and GPIO_117 high and
  - pull down GPIO_161 for 30ms then release it.

BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9b56ef8ff346c1d4edd5aad04d4a7396c4702ffc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45193
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18 17:44:16 +00:00
Tim Wawrzynczak fc161cbb36 mb/google/volteer: Remove redundant GPIO decls in Eldrid
GPP_A19 and GPP_A20 are already declared as NC in the baseboard.

Change-Id: I02f5751a70b51a197320b865d18da3a4ffeb87f7
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45485
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18 15:57:42 +00:00
Ben Chuang ff17b31dfb drivers/genesyslogic/gl9755: Add driver for Genesys Logic GL9755
The device is a PCIe Gen2 to SD 4.0 card reader controller to be
used in the Chromebook. The datasheet name is GL9755S and the revision
is 05.

The patch sets LTR value.

Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I16048dde348be248c748d50ca4a8a62c8a781430
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-18 15:49:15 +00:00
Malik_Hsu 8ad2b8be25 mb/google/volteer/eldrid: Add option to enable WiFi SAR configs
This change adds a user selectable option to enable all WiFi SAR
configs that apply to volteer

BUG=b:168169690
TEST=1. cros-workon-volteer start
          coreboot-private-files-baseboard-volteer
     2. USE="project_eldrid" emerge-volteer chromeos-config
          coreboot-private-files-baseboard-volteer
     3. check wifi_sar-eldrid.hex in
          coreboot-private/3rdparty/blobs/baseboard-volteer

Change-Id: I6b74cd2b34ebb99cc59d456e28fd7ab2399d71d0
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45233
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18 15:46:26 +00:00
Yilin Yang 46eaa5a1ba util/rockchip: Port make_idb.py to python3
BUG=chromium:1023662
TEST=buildbot pass
TEST=1. Use python2 script
     2. Run `emerge-kevin coreboot` twice, so we get bootblock.bin.1
     and bootblock.bin.2
     3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex
     and bootblock.bin.2.hex
     4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the
     difference. (at least, the time info changes)
     5. Migrate to python3
     6. Similar steps, we get bootblock.bin.py3.hex
     7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference
     is similar. (time info, git hash changes)

Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I04253084ec9b65310c52598b629390051cd2172b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45447
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18 13:30:05 +00:00
Angel Pons 12beaea5e2 superio/nuvoton: Inline `nuvoton_hwm_select_bank`
There's no need to place a single-line function in its own compilation
unit, and then guard it behind a Kconfig symbol. This also allows using
this function in stages other than ramstage.

Change-Id: I103a4ea4cef24844d382854c9358bbb37d229e04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42130
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18 12:37:36 +00:00
Angel Pons 64a6b6cb1f src/include: Add PnP/HWM unset_and_set functions
RMW (read/modify/write) ops on PnP devices has never been so simple.

The semantics also allow the compiler to emit valid warnings if the
input parameters would overflow, which are silenced when the cast is
placed outside of the function.

Change-Id: Ica01211af2a9a00aed98880844a836f6b7957b14
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42134
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18 12:06:38 +00:00
Yilin Yang 1502494cba util/exynos: Port *_cksum.py to python3
BUG=chromium:1023662
TEST=1. Create a tiny file `in.txt` as input
     2. Run `fixed_cksum.py in.txt out.txt 20` with py2 and py3 version,
     the output is the same
     3. Run `variable_cksum.py in.txt out.txt` with py2 and py3 version,
     the output is the same

Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I9428269dfb826a3a95fffef9ea3f7c1a7107ef84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-18 08:00:39 +00:00
Yilin Yang f944e619dd util/mtkheader: Port gen-bl-img.py to python3
BUG=chromium:1023662
TEST=1. Use python2 script
     2. Run `emerge-asurada coreboot` twice, so we get bootblock.bin.1
     and bootblock.bin.2
     3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex
     and bootblock.bin.2.hex
     4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the
     difference. (at least, the time info changes)
     5. Migrate to python3
     6. Similar steps, we get bootblock.bin.py3.hex
     7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference
     is similar.

Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I788e7c9b09257142728a0f76df8c2ccc72bf6b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-18 08:00:22 +00:00
Yu-Ping Wu 541f2f74a3 libpayload: cbgfx: Fix 'equals' counter for Lanczos resampling
The current initialization of the 'equals' counter is incorrect, so that
when 'equals >= SSZ * SSZ', the pixels in the sample array might not be
all the same, leading to a wrong pixel value being set in the
framebuffer.

The 'equals' counter stores the number of latest pixels that were
exactly equal. Within the for loop of 'ox', the sample array is updated
in a column-based order, and the 'equals' counter is updated
accordingly. However, the 'equals' counter is initialized in a row-based
order, which causes it to be set too large than it should be. Consider
the example where sample[sx][sy] are initially:

 [X X X A A A]  // sy = 0
 [X X X B B B]
 [X X X B B B]
 [X X X B B B]
 [X X X B B B]
 [X X X B B B]  // sy = SSZ

Then, the correct implementation will initialize 'equals' to be 15, with
last_equal being B. Suppose all of the remaining pixels are B. Then, at
the end of the 'while (fpfloor(ixfp) > ix)' loop when ix = 4, or
equivalently after 4 more columns of sample are updated, 'equals' will
be 15 + 6 * 4 = 39, which is greater than SSZ * SSZ = 36, but we can see
there are still 2 A's in the sample:

 [B B B B A A]
 [B B B B B B]
 [B B B B B B]
 [B B B B B B]
 [B B B B B B]
 [B B B B B B]

Therefore, we must also initialize the 'equals' counter in a
column-based order.

BUG=b:167739127
TEST=emerge-puff libpayload
TEST=Character 'k' is rendered correctly on puff
BRANCH=zork

Change-Id: Ibc91ad1af85adcf093eff40797cd54f32f57111d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-18 01:35:35 +00:00
Michael Niewöhner 5d1a328e88 soc/intel/cannonlake: add missing special function pads
The following parameters do nothing else than configuring the
corresponding pads to native mode:

- DdiPortEdp
- DdiPort*Hpd
- DdiPort*Ddc
- GpioDdp*
- SpiGpioAssign
- I2c*GpioAssign
- SerialIoUartDebugEnable
- Gp*GpioAssign
- Uart*GpioAssign
- GpioEnableHdaLink
- AudioLinkDmic*
- AudioLinkSsp*
- GpioEnableHdaSspMasterClock
- AudioLinkSndw*
- SmbAlertEnable

Add the missing special function gpio pad groups for CNL, to be able to
configure them via gpio.h instead having to set various FSP parameters.

The groups and names are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.

Also, see soc/intel/tigerlake for reference.

Change-Id: Ia3bc1df1a14dbca7c7213577cb2d5b98bb0acf64
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-17 21:53:38 +00:00
Jeremy Soller b349f258a9 mb/system76/lemp9: update power limits
Tested on lemp9, power limits are adjusted from the previously low
values to the values the thermal system can handle. This was
determined by increasing the values and running the system at 100%
CPU utilization until thermal throttling occured and the chassis
temperature became uncomfortable.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I5e176e9d98376f8e2dc415e4397efc456869e72d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43624
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 21:37:11 +00:00
Michael Niewöhner d7775b763f mb/system76/lemp9: disable PCH DMIC, which is not wired
The microphone is wired to the audio codec, not to the PCH. Disable the
DMIC interface.

Change-Id: I4128a694c1a66d3c2c2d1cb831fcca3487160f8f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45133
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 21:35:32 +00:00
Michael Niewöhner 1c2b1b977a soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names
The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.

Also, see soc/intel/tigerlake for reference.

Change-Id: I59df09c8fd464e75f918455aa1972765abc51459
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-17 21:13:29 +00:00
Jeremy Soller 748bfac734 mb/system76/lemp9: skip FSP init of UART2
This UART is already initialized by coreboot for the console, it does
not need to be initialized by the FSP.

Tested on lemp9.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I7c299fd7cf6fe53d1f500a899a14e63e51ad6266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-17 20:47:49 +00:00