Commit Graph

8825 Commits

Author SHA1 Message Date
Andrew Wu 52e665bdd2 Add initial support for DMP Vortex86EX CPU.
Change-Id: I74de250c69a57109362be1b2f00c0b4aa24a64e8
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3473
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-20 19:14:44 +02:00
Patrick Georgi 483ff82539 sandybridge: Store MRC cache in CBFS
Location is hard-coded right now, which isn't optimal.
It must be chip erase block aligned, which might fail on some flash chips
(it's 64k aligned which should work for most cases).

Change-Id: I6fe0607948c5fab04b9ed565a93e00b96bf44986
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3497
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-20 12:43:01 +02:00
Nico Huber 44c392f8c2 lenovo/t60: Collect timestamps in romstage
Collect early timestamps in T60's romstage like some newer boards do.
This should also work on X60s (and other ICH7 based systems with
EARLY_CBMEM_INIT).

Change-Id: I3b2872dd7423f3379ff3b68ad999523ec35fc08e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3499
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-19 17:59:50 +02:00
Nico Huber 9359f2de00 intel/i82801gx: Store initial timestamp
Upgrade the ICH7 bootblock to store an initial timestamp like we do it
since Sandy Brigde. I've checked the datasheets for the used scratchpad
registers and grepped for their usage. I'm pretty sure that they aren't
used on any ICH7 based board (for anything before the usual S3-resume
indication).

Change-Id: I28a9b90d3e6f6401a8114ecd240554a5dddc0eb5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3498
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-19 17:58:55 +02:00
Gerd Hoffmann 414b947851 qemu: complete bochs dispi interface vga driver.
Ditch unused fb*.h files.
Rename init.c (name is _way_ to generic) to bochs.c.
Add proper bochs dispi interface detection and mode setup.
Hook up coreboot framebuffer table initialization.

Change-Id: I7154b1593902e7d42606b64819217872eee10683
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3500
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-19 02:00:08 +02:00
Gerd Hoffmann 0ea3664bc3 edid: fix warning
src/lib/edid.c:1177: error: ‘y’ may be used uninitialized in this function

Warning is bogus, but seems my gcc (4.4.7 as shipped by RHEL-6)
isn't clever enougth to figure this on its own.  So help a bit
by explicitly initializing the variable.

Change-Id: Ia9f966c9c0a6bd92a9f41f1a4a3c8e49f258be37
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3501
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-19 01:58:29 +02:00
Nico Huber 354066e117 libpayload: ahci: Increase timeout for signature reading
We can't read the drives signature before it's ready, i.e. spun up.
So set the timeout to the standard 30s. Also put a notice on the
console, so the user knows why the signature reading failed.

Change-Id: I2148258f9b0eb950b71544dafd95776ae70afac8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3493
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-18 19:29:36 +02:00
Nico Huber cacc58a874 winbond/w83627dhg: Correct resource setting for SPI (LDN6)
The SPI logical device on the W83627DHG uses the second i/o port
register pair but not the first one. So we have to also set `io1`
(the second io_info struct) and not `io0` in the pnp_info structure.

Setting the PNP_IO1 flag without a mask in `io1` caused coreboot to
hang in pnp_enable_devices() until commit aeead274 which added a
check for an unset mask.

Change-Id: I027d279b4641fecd88afb14d40fbe1c0bfbf81bb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3391
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-18 19:15:12 +02:00
Gerd Hoffmann df8d27357f qemu/q35: uncomment cache-as-ram Kconfig entries
Change-Id: I8371764e3f2d16a3a776beb1c064f461b20a4262
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3496
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-18 17:44:38 +02:00
Gabe Black 5acc76cd3e am335x: Add pinmux support based on the functions in U-Boot
I was unable to find documentation that said what mode numbers correspond
to what functionality, so I translated over what U-Boot does.

Change-Id: I34fab0f024fa2322d6bb66106aed75224e67354d
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3489
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 22:05:35 +02:00
Kyösti Mälkki 56892fc475 AMD southbridges: Move HAVE_HARD_RESET
All 3 boards with AGESA_HUDSON had HAVE_HARD_RESET with the reset.c
file already placed under southbridge/.

All 15 boards with CIMX_SBx00 had HAVE_HARD_RESET with functionally
identical reset.c file under mainboard/. Move those files under
respective southbridge/.

Change-Id: Icfda51527ee62e578067a7fc9dcf60bc9860b269
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3486
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17 21:50:46 +02:00
Kyösti Mälkki d715105d30 AMD: Use same sourcecode for reset in romstage as ramstage
Confusingly, romstage compiled in different copy of soft_reset()
than ramstage. Use source in reset.c for both.

Change-Id: I2e4b6d1b89c859c7cf5d9e9c8f7748b43d369775
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3487
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17 21:49:33 +02:00
Kyösti Mälkki 397ca6176c AMD boards: Clean use of Kconfig options
The chip component is unconditionally selected for the mainboard
so these uses are superfluous.

Change-Id: I84b053ab47f7b1f68e88d968cf305e24bc95f4da
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3485
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17 21:48:31 +02:00
Dave Frodin 0fd6a65243 Add support for XHCI (USB 3.0)
CONFIG_HUDSON_XHCI_ENABLE will control the XHCI flags in the
amd/parmer and asus/f2a85-m mainboards.  The XHCI ports on
amd/thatcher are not wired to USB jacks so always disable the flags.
This was tested on amd/parmer using a USB 3.0 thumbdrive.

Change-Id: I596b040fec30882d8d4dee34ab9f866dc1f8896b
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3465
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:45:39 +02:00
Dave Frodin 1fa1904e53 AMD Hudson: Add config option to enable XHCI
To have USB 3.0 support the XHCI controller needs to be enabled
and the xhci.bin firmware needs to be added to CBFS.

Change-Id: I0b641b30b67163b7dc73ee7ae67efe678e11c000
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3464
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:45:06 +02:00
Nico Huber 0b2ee93910 pnp: Remove now plain wrappers for default PnP functions
After removing the enter()/exit() functions for configuration mode,
most wrappers for our standard PnP functions just call the underlying
default implementation.

Remove those with a little cocci:
    @ op_match @
    identifier op;
    identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
    type device_t;
    identifier dev;
    @@
     static void op(device_t dev) { pnp_op(dev); }

    @@
    identifier op_match.op;
    @@
    -op(...) {...}

    /* Three rules to match the alignment, hmmp... */
    @@
    identifier op_match.op, op_match.pnp_op;
    identifier ops;
    @@
     struct device_operations ops = {
    -        .set_resources    = op,
    +        .set_resources    = pnp_op,
     };

    @@
    identifier op_match.op, op_match.pnp_op;
    identifier ops;
    @@
     struct device_operations ops = {
    -        .enable_resources = op,
    +        .enable_resources = pnp_op,
     };

    @@
    identifier op_match.op, op_match.pnp_op;
    identifier ops;
    @@
     struct device_operations ops = {
    -        .enable           = op,
    +        .enable           = pnp_op,
     };

Change-Id: Idc0e52c7e3600a01f3b6a4e17763557b271b481e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3483
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:42:21 +02:00
Nico Huber 13dc976a52 pnp: Register implementations of enter/exit config state
Find all the (ramstage) implementations of enter()/exit() functions
for the configuration state, register and call them through the new
struct pnp_mode_ops. As our standard PnP functions are aware of the
pnp_mode_ops, it's not necessary to call enter()/exit() around them
anymore.

Patch generated with the cocci below. It's not perfect. The movement
of the enter()/exit() calls is somehow fragile. So I checked the
remaining calls for sense, and changed some empty lines. Also a
duplicate insertion of pnp_conf_mode_ops had to be removed.
    /* Try to find enter and exit functions by their outb() structure and
       their usage around calls to our standard pnp functions: */
    @ enter_match @
    identifier enter;
    identifier dev;
    type device_t;
    @@
     void enter(device_t dev)
     {
             <...
             outb(..., dev->path.pnp.port);
             ...>
     }

    @ exit_match @
    identifier exit;
    identifier dev;
    type device_t;
    @@
     void exit(device_t dev)
     {
             <...
             outb(..., dev->path.pnp.port);
             ...>
     }

    @ pnp_match @
    identifier op;
    identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
    identifier enter_match.enter, exit_match.exit;
    type device_t;
    identifier dev;
    @@
     void op(device_t dev)
     {
             ...
             enter(dev);
             ...
             pnp_op(dev);
             ...
             exit(dev);
             ...
     }

    /* Now add enter/exit to a pnp_mode_ops structure: */
    @ depends on pnp_match @
    identifier enter_match.enter;
    identifier exit_match.exit;
    identifier ops;
    @@
    +static const struct pnp_mode_ops pnp_conf_mode_ops = {
    +        .enter_conf_mode  = enter,
    +        .exit_conf_mode   = exit,
    +};
    +
     struct device_operations ops = {
             ...,
    +        .ops_pnp_mode     = &pnp_conf_mode_ops,
     };

    /* Match against the new structure as we change the code and the above
       matches might not work anymore: */
    @ mode_match @
    identifier enter, exit, ops;
    @@
     struct pnp_mode_ops ops = {
             .enter_conf_mode  = enter,
             .exit_conf_mode   = exit,
     };

    /* Replace enter()/enter() calls with new standard calls (e.g.
       pnp_enter_conf_mode()): */
    @@
    identifier mode_match.enter;
    expression e;
    @@
    -enter(e)
    +pnp_enter_conf_mode(e)

    @@
    identifier mode_match.exit;
    expression e;
    @@
    -exit(e)
    +pnp_exit_conf_mode(e)

    /* If there are calls to standard PnP functions, (re)move the
       enter()/exit() calls around them: */
    @@
    identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
    expression e;
    @@
    -pnp_enter_conf_mode(e);
     pnp_op(e);
    +pnp_enter_conf_mode(e);
     ...
     pnp_exit_conf_mode(e);

    @@
    identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
    expression e;
    @@
     pnp_enter_conf_mode(e);
     ...
    +pnp_exit_conf_mode(e);
     pnp_op(e);
    -pnp_exit_conf_mode(e);

    @@
    expression e;
    @@
    -pnp_enter_conf_mode(e);
    -pnp_exit_conf_mode(e);

Change-Id: I5c04b0c6a8f01a30bc25fe195797c02e75b6c276
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3482
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:42:06 +02:00
Nico Huber dd4715b6a5 pnp: Implement common handling for PnP config modes
Many super i/o chips only answer to PnP requests if they are in a
configuration state (sometimes also called ext func mode). To cope with
that, the code of many chips implements its own version of our default
PnP functions like pnp_set_resource(), pnp_enable_resource() etc.

To avoid this code duplication, this patch extends our PnP device
interface with optional functions to enter and exit configuration mode.

Change-Id: I9b7662a0db70ede93276764fa15020f251eb46bd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3481
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:39:40 +02:00
Nico Huber f898f7ba4d pnp: Provide alternative pnp_enable() implementation
The current default implementation of pnp_enable() only disables devices
- if set so in the devicetree - but does not enable them. Enablement takes
place in pnp_enable_resources(). Yet, many PnP chips implement their own
version of pnp_enable() which also enables devices if set in the devicetree.

It's arguable, if enabling those devices makes sense, before they get
resources assigned. Maybe we can't write the resource registers if not,
who knows? The least we can do is providing a common implementation for
this behavior, and get rid of some code duplication.

Used the following cocci:
    @@
    expression e;
    @@
    +pnp_alt_enable(e);
    -pnp_set_logical_device(e);
    (
    -pnp_set_enable(e, !!e->enabled);
    |
    -(e->enabled) ? pnp_set_enable(e, 1) : pnp_set_enable(e, 0);
    |
    -if (e->enabled) { pnp_set_enable(e, 1); }
    -else { pnp_set_enable(e, 0); }
    )

Change-Id: I8d695e8fcd3cf8b847b1aa99326b51a554700bc4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3480
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:38:37 +02:00
Nico Huber a00f9830fb libpayload: ahci: Fix command engine shutdown
A timeout while waiting for a device' signature has shown that our
error path wasn't correct. The shutdown of the ports command engine
always timed out. Fix that by waiting for FR (FIS Receive Running)
to be cleared independently from CR (Command List Running) and after
clearing FRE (FIS Receive Enable).

Change-Id: I50edf426ef0241424456f1489a7fc86a2cfc5753
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3494
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:32:42 +02:00
Patrick Georgi 3cc151ede0 Make intel blob locations configurable
They were hard-coded to be copied from 3rdparty/ which isn't always
the right choice.

Since the defaults stay the same, this should be compatible.

Change-Id: If2173bef86ad1fcf2335e13472ea8ca41eb41f3d
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3453
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17 19:16:52 +02:00
Nico Huber 9cb0941cb2 pnp: Unify some alignment to ease autogenerating patches
Most PnP drivers align the initialization of their `device_operations`
with spaces. Unify this, so next autogenerated patches always match the
alignment.

Change-Id: I3f6baef6c8bb294c136354754125ea88c07a61a1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3479
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-17 18:11:35 +02:00
Gerd Hoffmann 7fd1beeaf7 qemu: i440fx whitespace fixup
Change-Id: I0d499027ffb175638cba0a9830d6ec2041a139db
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3488
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-17 17:04:43 +02:00
Gerd Hoffmann ee941b38d6 qemu: add q35 support
Add support for the new q35 chipset emulation
added in qemu 1.4.

Change-Id: Iabfaa1310dc7b54c9d224635addebdfafe1fbfaf
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3430
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-17 17:04:17 +02:00
Gerd Hoffmann 9839a385bb qemu: add support for memory above 4G
Change-Id: Ic83f55d01b29b43028e3b363749d64b927db5489
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3492
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-17 17:00:10 +02:00
Gerd Hoffmann 44b11f2fe4 qemu: move ram ressource reservation from "set" to "read" stage
So the pci allocation code knows where memory is and doesn't
try map pci devices there.  We also don't have to check for
overlaps between pci hole and memory then.

Change-Id: I5eaea0e4d21210719685860fa1f16ca7b2137cde
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3491
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-17 16:59:14 +02:00
Christopher Kilgour 156ff13049 cpu/amd/geode_lx/cache_as_ram.inc: Use $ for constant value instead of memory reference
An uninitialized RAM value was used to select an MSR because a $ was forgotten
in front of `CPU_DM_CONFIG0`. It should be the constant value 0x1800, corresponding
to CPU_DM_CONFIG0 MSR defined in `src/include/cpu/amd/lxdef.h`.

Change-Id: Id53ca98b06cc4a9b55916fd8db23904f98008d45
Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
Reviewed-on: http://review.coreboot.org/3478
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2013-06-17 08:26:59 +02:00
Kyösti Mälkki 04372975bd AMD sb800 agesa/hudson: Use PCI defines
The original lines had contradicting comment and code.
This change follows the code and sets MASTER bit too.

Change-Id: Id2886bfc107612530f0e9747e5d49a9740fb8532
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3466
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-14 18:54:57 +02:00
Gerd Hoffmann 00cc7f4355 qemu: move i440fx bits
Prepare tree for adding q35 support:
Move emulation/qemu-x86 to emulation/qemu-i440fx.
Rename some stuff to include 'i440fx'.

Change-Id: Ib8c58175c5734cfcda1b22404ef52c09d38f0462
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3429
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-14 18:19:26 +02:00
Kyösti Mälkki e49679d5a1 usbdebug: Drop temporary disables of log output
With this patch, output on usbdebug also includes the section of
MTRR setups for every CPU. This makes usbdebug output almost identical
with that of serial port and CBMEM console.

Tested with model_206ax. Also tested previously on model_f2x which does
not have these disable/enable calls in model_f2x_init() without detected issues.

Change-Id: Idfd0e93439907b17255633658195d698feab3895
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3423
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-06-14 18:18:56 +02:00
Kyösti Mälkki f55a54257a lynxpoint: Fix PCI IDs for EHCI
IDs were leftovers from bd82x6x.

Change-Id: I4ab6062929d346d7f000ce8c0b8c97490bb2b154
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3463
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-06-14 16:04:19 +02:00
Dave Frodin ea90963666 AMD Hudson: Add support for the SD controller
This patch provides the correct SD controller timings for
the Family16 device. It also will remove the SD controller
from PCI space when device 0:14.7 is set to off in devicetree.
This was tested on a AMD Parmer board and a AMD G-series SOC
reference board. The settings were found in the AMD
Hudson2 RRG and family16 BKGD.

Change-Id: I6d7e7997ddc39802ab75dc8a211ed29f028c0471
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3348
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 22:57:21 +02:00
Nico Huber 9029265cf5 libpayload: Fill gaps in the xHCI driver
Well, it turned out to be more as some gaps ;)
but we finally have xHCI running. It's well tested against a QM77 Ivy
Bridge board.

We have no SuperSpeed support (yet). On Ivy Bridge, SuperSpeed is not
advertised and USB 3 devices will just work at HighSpeed.

There are still some bit fields in xhci_private.h, so this might need
little more work to run on ARM.

Change-Id: I7a2cb3f226d24573659142565db38b13acdc218c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3452
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 22:21:20 +02:00
Nico Huber 5736fab4be libpayload: Port usb hub driver to use the generic code
This is mostly a rewrite, don't even try to read a diff.

Tested with an internal rate matching hub on a QM77 board and three hubs
integrated into DELL monitors.

Change-Id: Ib12fa2aa90af4e0f37143d2ed92c4a1705b6d774
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3451
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 22:18:49 +02:00
Nico Huber 0b78de2ee9 libpayload: Add a generic driver for usb hubs
The current drivers for external usb hubs and root hubs all follow
the same pattern. Before adding another one with 90% of the same code,
extract the common parts and rewrite them with a simple interface.

This also adds debouncing of new attachments. Current drivers just
waited 100ms before they reset the device. However, we should check
if the device becomes disconnected and reconnected during this period.

Porting of the current hub drivers will take place in separate
commits (when I have time to test the older HCIs).

Change-Id: I0c0ce0ac1b1cc51fb4cd009b3f9fcd1b9d2ba8fe
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3450
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 22:17:42 +02:00
Nico Huber aee44fa37d libpayload: usb: Add interval attribute to endpoints
Read bInterval from endpoint descriptors and store it in our endpoint_t
struct. The interval is encoded dependently on the device' speed and the
endpoint's type. Therefore, it will be normalized to the binary logarithm
of the number of microframes, i.e.
  t = 125us * 2^interval

The interval attribute will be used in the xHCI driver.

Change-Id: I65a8eda6145faf34666800789f0292e640a8141b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3449
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 22:16:39 +02:00
Patrick Georgi 482af6d15c libpayload: Redirect USB slave init through controller driver
xHCI requires special treatment of set_address since it determines
the device number itself (instead of the driver, as with the other
controllers). The controller also wants to validate a chosen device
configuration and we need to setup additional structures for the
device and the endpoints.

Therefore, we add three functions to the hci_t structure, namely:
  set_address()
  finish_device_config()
  destroy_device()
Current implementation for the Set Address request moved into
generic_set_address() which is set_address() for the UHCI, OCHI and
EHCI drivers. The latter two are only provided as hooks for the xHCI
driver.

The Set Configuration request is moved after endpoint enumeration.
For all other controller drivers nothing changes, as there is no other
device communication between the lines where the set_configuration()
call moved.

Change-Id: I6127627b9367ef573aa1a1525782bc1304ea350d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3447
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 22:16:27 +02:00
Nico Huber 4fc7b6c994 libpayload: Add enum for USB speeds
These values are already used in this usb stack.

Change-Id: If96f1dc2b67fbc13dfc4ae2d84e8f9945aa03163
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3448
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 22:13:16 +02:00
Nico Huber 735f55c29c libpayload: usb: Skip non-endpoint descriptors during init
During device initialization, skip any non-endpoint descriptor before
reading the endpoint descriptors. By now, only HID descriptors were
skipped.

Change-Id: I190f3ae44b864aa71d5f32c3738097cf8f33a61b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-06-13 22:02:18 +02:00
Stefan Tauner 088f569400 util/inteltool: Add support for other 5 chipsets
e4e8e090fa does add support for QM57,
but there are many more that should work with that code(?).

Does not explode on...
CPU: Processor Type: 0, Family 6, Model 25, Stepping 2
Northbridge: 8086:0044 (1st generation (Westmere family) Core Processor)
Southbridge: 8086:3b0f (QS57)

Change-Id: I85e15ba45678a5bd635415a7a8d69c05bff8f7ef
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3321
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-06-13 11:31:41 +02:00
Siyuan Wang 6c4f3ce490 AMD S3 resume: use a function to replace duplicated code
In function OemAgesaSaveMtrr of 'src/cpu/amd/agesa/s3_resume.c',
there are many code like this:
  msr_data = rdmsr(0x258);
  flash->write(flash, nvram_pos, 4, &msr_data.lo);
  nvram_pos += 4;
  flash->write(flash, nvram_pos, 4, &msr_data.hi);
  nvram_pos += 4;
Add a function write_mtrr to do this.

Change-Id: Id6464e637db1758b07ac2d79d3be1375a8d49651
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3410
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 01:17:22 +02:00
Siyuan Wang d2ae6ae789 AMD Thatcher: fix issue 'S3 fails to suspend after wake up from USB keyboard'
This issue can be reproduced in Linux by the following steps:
1) use pm-suspend to suspend.
2) use USB keyboard to wake up.
3) use pm-suspend to suspend. FAIL To SUSPEND.

The cause of this issue is:
USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event,
but this bit is not clear after wake up. So OS thinks there is a
wake up signal and wake up immediately.

In this patch, I add AcpiGpe0Blk using MMIO access and write 1
on bit 11. Write 1 to clear as spec says.
I have tested on Thatcher

The same change was done for AMD Parmer in commit »AMD Parmer:
fix issue 'S3 fails to suspend after wake up from USB keyboard'
(03901124) [1].

[1] http://review.coreboot.org/#/c/3347/
    (Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1)

Change-Id: Iaef39237497ef896d0f186e8f5522222c0ce6cb7
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3374
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 01:15:35 +02:00
Kyösti Mälkki 59d0d159f4 AMD: Kconfig cleanup
Change-Id: I21182eae1d389790c330f27e6a830d91c3ee4eb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3433
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-13 01:08:12 +02:00
Vladimir Serbinenko 22dcdd914c Add support for Intel Nehalem CPU
Change-Id: I7ecc394b1e5bc0b8b85a8afac22efc0befe2d36a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3395
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 00:32:01 +02:00
Stefan Reinauer 3a09179f46 Revert "Add support for Intel Ibex Peak (Mobile 5) southbridge"
This reverts commit 0210119b4b

Change-Id: I5be3f2a54394c592650a0dcd671e4a72ae796cb2
Reviewed-on: http://review.coreboot.org/3443
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 00:27:07 +02:00
Stefan Reinauer 0210119b4b Add support for Intel Ibex Peak (Mobile 5) southbridge
Change-Id: If56f2cacc5f1b2ef9c7b6aea508d458a43dd1309
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3397
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:31:04 +02:00
Vladimir Serbinenko 26419285bf Avoid tripping overheat alarm on X201 before ME boots
Until ME boots (which takes seconds on X201) the reported temperature
is 128 °C which triggers Linux overheat alarm which shuts down.
Pretend temperature is 40°C until ME boots.

Change-Id: Ia49fa03c6eb27f539a23711f2c8ebfde72b1dc18
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/3404
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:29:51 +02:00
Vladimir Serbinenko fe50d0bcfe Make acpi/ec.c usable in romstage
On X201 to enable EHCI debug you need to go through EC if USB power is
disabled so we need to inclue ec.c.

Change-Id: I8f8b7de639ecaebceaa53cd338136befaeec8214
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/3405
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:29:07 +02:00
Vladimir Serbinenko 7d1ebbff5a Radio and dock support in EC on X60 and X201
Enable UMTS on Lenovo X60 and X201.
Enable radios if no options are available.
Enable dock on Lenovo X201.

Based on my X201 branch.

Change-Id: I6e8d3bbd6a6b1a8e59473dd5cc8125a1583d75df
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/3377
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:28:25 +02:00
David Hendricks 942e69dea1 am335x: Add struct `am335x_uart` for uart registers
Add a struct for referencing UART registers. The layout is quite
strange on this chip, as the entire register space can take on three
different meanings depending on the line control settings (in the LCR
register) And to make things more confusing, some offsets reference
different registers depending on if a read or a write operation is
used.

Change-Id: Ie62af9c0e0edafd01b81686a0fe5c5c1d4fa06c4
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3319
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:25:11 +02:00