Commit Graph

47507 Commits

Author SHA1 Message Date
Elyes Haouas 26e0b94614 util/lint/checkpatch.pl: Reduce difference with linux v5.18
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id5eb4823399088746a34721a9855bbaf5f97b7b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-24 12:57:48 +00:00
Yidi Lin f044264886 mainboard/google/corsola: Fix incorrect timestamps in the eventlog
Timestamp '2000-00-00 00:00:00' is considered as the invalid format.
Enable RTC to fix incorrect timestamp format in the eventlog.

BUG=b:232035991
TEST=check the timestamp field in /var/log/eventlog.txt

Change-Id: I8d9822075377734ef4a609ddeee79385fe7af0f0
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2022-05-24 07:46:26 +00:00
Subrata Banik f8d4b50a67 soc/intel/alderlake: Drop unused `PCH_DEV_SLOT_LPC` macro
This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the
Alder Lake SoC PCI device list.

BUG=none
TEST=Able to build and boot taeko, google board.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib2ae40fcc4499de34534f27f03b4c359c37409e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-24 05:09:25 +00:00
Werner Zeh b60e69bde8 soc/intel/apollolake: Enable SSDT for fast SPI controller
Since the fast SPI controller is hidden on Apollo Lake the OS cannot
probe it and is therefore unaware of the reserved resources assigned in
coreboot. Select 'FAST_SPI_GENERATE_SSDT' to enable SSDT creation to
report the reserved resources to the OS.

Change-Id: I23e77a0a01141dc4f299988d19509e6df555a654
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-05-23 14:49:10 +00:00
Arthur Heymans ea2c1d357c cpu/x86/smm: Remove heap
Currently no smihandler uses heap.

coreboot's heap manager also is quite limited in what it will
free (only the latest alloc). This makes it a bad idea to use it inside
the smihandler, as depending on the alloc usage the heap might actually
be full at some point, breaking the smihandler.

This also reduces the ramstage by 448 bytes on google/vilboz.

Change-Id: I70cd822be17c1efe13c94a9dbd2e1038808b9c56
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-23 13:53:26 +00:00
Uwe Poeche bf378a0fdf mb/siemens/mc_ehl: Disable RAPL
Disable RAPL for all mainboards based on mc_ehl for stable real time
mode of CPUs.

Test: Boot mc_ehl1 with this patch and ensure the bits in the MCBAR
register are cleared.

Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-23 11:54:58 +00:00
Uwe Poeche 0ce586b1a4 soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig
This patch provides the possibility for EHL based boards to disable
RAPL settings via SOC_INTEL_DISABLE_POWER_LIMITS config switch.

On Elkhart Lake the way via setting relevant MSR bits does not work.
Therefore the way via MCHBAR is choosen.

Test:
Check MCHBAR mapped registers (MCH_PKG_POWER_LIMIT) on mc_ehl1.

Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-23 07:17:21 +00:00
Jon Murphy ac040552fc mb/google/guybrush: Remove TODO for ESPI functions
The feature request was moved to Skyrim in the interest of time
and effort.  The bug was updated to reflect this, and the comment
should be removed from the monkey island code base

BUG=b:232952508
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Id4ca43692aa56b6dba2f7acc1f924b30c1e966ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-22 18:28:00 +00:00
Jon Murphy c44249d52c mb/google/guybrush: Remove unused sleep GPIO table
On Guybrush, there wasn't a need for a sleep GPIO table.
Remove the TODO and filler table and function to reduce
unnecessary function calls/overhead.

BUG=b:232952508
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic51ee4845d663acf34f050f7b3abf57a7c247c88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-22 18:27:26 +00:00
Felix Held 6e43836ef3 mb/gogle/skyrim/devicetree: enable display HDA device
The HD audio controller of the GPU on bus A device 0 function 1 wasn't
enabled, so it didn't get resources assigned. Enable it to fix this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib9a4129ce594c5dd59f70e855fef5f2c04ebb9c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64554
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21 18:53:12 +00:00
Felix Held e0ea930296 mb/gogle/skyrim/devicetree: enable audio coprocessor device
The ACP device on bus A device 0 function 5 wasn't enabled, so it didn't
get resources assigned. Enable the ACP device to fix this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc9376314213e9d624756519f703d508411cb1bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64553
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21 18:52:52 +00:00
Felix Held b29f7d3f8d mb/gogle/skyrim/devicetree: enable crypto device
The crypro device on bus A device 0 function 2 wasn't enabled, so it
didn't get resources assigned resulting in this the Linux kernel error:

[   38.582036] pci 0000:04:00.2: attach allowed to drvr ccp [internal device]
[   38.582064] ccp 0000:04:00.2: enabling device (0000 -> 0002)
[   38.582175] ccp 0000:04:00.2: ioremap failed
[   38.582178] ccp 0000:04:00.2: initialization failed
[   38.582181] ccp: probe of 0000:04:00.2 failed with error -12

Enable the crypto device to fix this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia812df6e59f3767dcbaa908fa620b62619590f85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64552
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21 18:52:35 +00:00
Mario Scheithauer 5b3ccc253f mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edge
There are three external Marvell PHY 88E1512 on this mainboard. The PHY
IRQ comes with a falling edge but the EHL MAC side needs a rising edge
signal. For that reason, we need an inversion of the IRQ polarity.

Change-Id: Id3caf582b4434b046779f5733e6ad9b57528ce35
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-21 17:41:16 +00:00
Mario Scheithauer dccdaceb49 soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity
EHL MAC side expects a rising edge signal for an IRQ. Based on the
mainboard wiring it could be necessary to change the interrupt polarity.
This patch provides the functionality to invert a falling edge signal
that comes from an external PHY. The inverting can be activated via
devicetree parameter.

Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-21 17:40:52 +00:00
Eric Lai 8698a6f5a9 mb/google/nissa: Change pen garage wake to EV_ACT_ANY
Follow google stylus spec. The Stylus-Present GPIO MUST be a wake
pin that interrupts the system in active operation when the stylus
is removed or inserted.

BUG=b:233159811
TEST=EC wake event work as expected.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Icf609c647e19914684a93c89022f2cd4888a67ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-21 17:40:23 +00:00
Sean Rhodes de198bb707 soc/intel/apollolake: Hook up Sata Hot Plug to device tree
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I37d31598e87e5b625ded3186980e3aba7dcf6440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-21 16:30:08 +00:00
Sean Rhodes 2683108188 soc/intel/apollolake: Hook up Legacy 8254 Timer
Hook Timer8254ClkSetting to `legacy_8254_timer` cmos option. If that
isn't set, fallback to the `USE_LEGACY_8254_TIMER` Kconfig option.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4f91cc2c8f48e9da47399059386092314b631b08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-21 16:29:38 +00:00
Tyler Wang 59f3eb9a07 mb/google/brya/var/craask: Generate SPD ID for supported memory part
Add supported memory parts in mem_parts_used.txt, and generate SPD id
for this part.

H9JCNNNBK3MLYR-N6E

BUG=b:229938024
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ibb111cddc00a0d066ef9792d974a6e4ad263cc99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-21 16:29:00 +00:00
Sean Rhodes f304d5ff8c mb/starlabs/lite/glk: Correct indendation in devicetree
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I780e2765059ad7473fe5f33c50dd0d8a561151fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-21 16:26:13 +00:00
Werner Zeh 53553e8ee5 src/soc/intel/cmn/fast-spi: Add SSDT extension to fast SPI driver
If the SPI controller is hidden from the OS (which is default on Apollo
Lake) then OS has no chance to probe the device and therefore can not be
aware of the resources this PCI device occupies. If the OS needs to move
some resources for a reason it can happen that the new allocated window
will be shadowed by the hidden PCI device resource and hence causing a
conflict. As a result this MMIO window will be inaccessible from the OS
which will cause issues in applications. For instance on Apollo Lake
this causes flashrom to stop working.

This patch adds a SSDT extension for the PCI device if it is hidden from
the OS and reports the occupied resource via ACPI to the OS. For the
cases where the device is hidden later at coreboot runtime and therefore
is not marked as hidden in the PCI device itself a Kconfig switch called
'FAST_SPI_GENERATE_SSDT' is introduced. It defaults to 'no' and can be
set from SOC code to override it.

Since there is no defined ACPI ID for the fast SPI controller available
now, the generic one (PNP0C02) is used.

Test: Boot mc_apl4 and make sure flashrom works again.

Change-Id: Ia16dfe6e001188aad26418afe0f04c53ecfd56f1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-21 16:20:17 +00:00
Tyler Wang 3c88dc85f6 mb/google/nissa/var/craask: Disable pen garage and WFC based on fw_config
BUG=b:229938024
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ib5770f02a6d524417be6723f7f70aa80d9452f62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-21 16:18:57 +00:00
Tyler Wang 10fb9c7f36 mb/google/nissa/var/craask: Switch LTE-related GPIOs settings based on fw_config
If the LTE USB DB is connected, enable LTE-related settings.
Otherwise, disable LTE-related settings.

BUG=b:229938024, b:229048361, b:229040345
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I37719cee48370a04534067aa64a3aa77e453948a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-21 16:16:53 +00:00
Terry Chen 03bdf47102 mb/google/brya/var/crota: Enable SaGv
Enable SaGv support for crota

BUG=b:229600878
TEST=FW_NAME=crota emerge-brya coreboot

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ibc06ef19e9fbbc91ef650a4ac060ce2b7c5c25d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-20 20:27:59 +00:00
Teddy Shih 13b27a376e mb/google/dedede/beadrix: Update FW_CONFIG probe for daughter board LTE
To make sure daughter board LTE existing, we update probe to DB ports
value of FW_CONFIG field, (https://partnerissuetracker.corp.google.com/issues/226910787#comment11)
as well as, refer to Google Henry and Ivan comments (https://partnerissuetracker.corp.google.com/issues/226910787#comment14)

BRANCH=dedede
BUG=b:226910787
TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot.

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I9ab4412b614ec665fbafc998756b805591982b65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-20 20:27:35 +00:00
V Sowmya fe97ad37fc mb/google/nissa: Configure the external V1p05/Vnn/VnnSx rails for Nereid
This patch configures external V1p05/Vnn/VnnSx rails for Nereid
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
  S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide

BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I1df4ea10798354f41fe9cce0f8c478930517207c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-20 20:26:58 +00:00
V Sowmya 1e44a5b0c7 mb/google/nissa: Configure the external V1p05/Vnn/VnnSx rails for Nivviks
This patch configures external V1p05/Vnn/VnnSx rails for Nivviks
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
  S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide

BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: If8da0dfe3059087526f74042be3c8b7e4a7ece82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-20 20:26:36 +00:00
V Sowmya bccad8d0a8 mb/intel/adlrvp: Configure the external V1p05/Vnn/VnnSx rails
This patch configures external V1p05/Vnn/VnnSx rails for adlrvp-n
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
  S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide

BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I06298eb1aec07eae34420c5736e912c707fefbc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-20 20:26:13 +00:00
Casper Chang 55c1e7f858 mb/google/brya: Disable PCH USB2 phy power gating for primus
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.

BUG=b:221461379
TEST=Verify the build for primus board

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I4d7d52bdeafe8b1b55822b5c8d040c94ce1f3878
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-20 16:43:03 +00:00
Tim Wawrzynczak f5cd9a15ba mb/google/brya/acpi: Add support for NBCI _DSM subfunction
The Nvidia GPU supports another function named NBCI (NoteBook Common
Interface), which has some subfunctions which are required for the
Nvidia kernel driver to consume. The specification for this function
comes from the Nvidia GN20 Software Design Guide.

BUG=b:214581763
TEST=build

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I19eb9417923d297a084d6f5329682e91cd506a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-20 14:59:31 +00:00
Tim Wawrzynczak 2a9b7d9313 mb/google/brya/var/agah: Select INCLUDE_NVIDIA_GPU_ASL
The agah variant will include an Nvidia GN20 series GPU, therefore
select the INCLUDE_NVIDIA_GPU_ASL Kconfig to include the respective
ASL code into the DSDT.

BUG=b:214581763
TEST=build patch train

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icc718d01506ccb4dd42841239e96926f4ddaa9c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-20 14:59:03 +00:00
Tim Wawrzynczak c852533379 mb/google/brya: Add PEG and initial Nvidia dGPU ASL support
Some brya variants will use a GN20 series Nvidia GPU, which requires
quite a bit of ACPI support code to be written for it. This patch
lands a decent bit of the initial code for it on the brya platform,
including:

1) PEG RTD3 methods
2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods)
3) NVOP _DSM method

There will be more support to come later, this is all written to
specifications from the Nvidia Software Design Guide for GN20.

BUG=b:214581763
TEST=build patch train

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-20 14:58:46 +00:00
Arthur Heymans 2efd8315f2 lib/Makefile.inc: Add cbfs header pointer on !BOOTBLOCK_IN_CBFS
On some x86 targets it the bootblock is loaded via a different
mechanism, like via the AMD PSP or Intel IFWI. Some payloads need that
pointer so add it to cbfs.

Note that on Intel APL this file is not used, which is why the
bootblock still needs to contain the pointer in the ARCH_X86 part.
It is not worth it to add logic to specifically deal with APL as this is
a legacy feature anyway.

For AMD non-car platform this fixes cbfs access in SeaBIOS.

Change-Id: If46e80e3eed5cc3f59964ac58e507f927fc563c4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-20 11:22:32 +00:00
Mario Scheithauer 5b757b597a soc/intel/ehl: Use defines for Ethernet controller IDs
Use defines for a better reading of the code.

Change-Id: I8e696240d649c0ea2341b8f04b62eebffebc1d57
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64519
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-20 11:22:03 +00:00
Lean Sheng Tan e1c385ebe1 mb/siemens/mc_ehl2: Quick fix for PSE TSN phy interface type
Based on quick fix on this commit 7b0fe59be (soc/intel/ehl: Fix
logical bug for PseTsnGbePhyInterfaceType), disable PSE TSN
SGMII as the original intention is to set the PSE TSN phy
interface as RGMII.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Id2e05b19f156621a945110791038bc0d19a0aad0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-05-20 11:21:11 +00:00
Lean Sheng Tan 100514d8c7 soc/intel/ehl: Fix logical bug for PseTsnGbePhyInterfaceType
By right if PseTsnGbeSgmiiEnable is disable,
PseTsnGbePhyInterfaceType should use RGMII setting.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: If593a5534716a9e93f99cb155fb5e86e12b1df17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-05-20 11:20:46 +00:00
Amanda Huang a68824185e mb/google/skyrim: Expose SKU and board ID to Chrome OS
Select EC_GOOGLE_CHROMEEC_SKUID and EC_GOOGLE_CHROMEEC_BOARDID to
provide common routine for reading skudid and boardid from Chrome EC.

BUG=b:229052726
TEST=emerge-skyrim coreboot chromeos-bootimage
Check the corresponding directory gets mounted to /run/chromeos-config/v1

Change-Id: I6aff02d29d44e95cd9b9e9485593c81f0d4a4b0e
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-20 11:20:11 +00:00
Terry Chen bf2e0a781a mb/google/brya/variants/crota: Configure audio codec IRQ type
The audio codec used by crota has a level-sensitive interrupt,
therefore configure the GPIO pad as level-sensitive.

BUG=b:230418589
TEST=emerge-brya coreboot and verified pass

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I588c21e44b9bb17cd5a48bf5f22465ec328496e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-20 11:19:52 +00:00
Jon Murphy 7e63dfad5a mb/google/skyrim/var/skyrim: Add better descriptors for USB endpoints
Fix descriptors for USB ports to align with their function and
placement with respect to the schematics.

BUG=N/A
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If57bebf9bffd4616c437ec655b64cab3298ac08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-20 11:19:06 +00:00
Jon Murphy d5b1f547c3 vc/amd/fsp/sabrina: Update PSP header to set the SOC FW ID
Update the PSP header to set the SOC FW ID to 0x0149 for
this platform

BUG=b:217414563
TEST=Build and verify header is set correctly

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic604ec96560c2d4d89c48c4a27528c5cfe4ca7e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-20 11:18:41 +00:00
Arthur Heymans f4905da14c Doc/4.17-relnotes.md: Add updated CBMEM_INIT hooks
Change-Id: I417bab99eeb7ec91fcb39d092d396580ad02ef23
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-05-20 07:15:45 +00:00
Kyösti Mälkki fa3bc049f5 CBMEM: Change declarations for initialization hooks
There are efforts to have bootflows that do not follow a traditional
bootblock-romstage-postcar-ramstage model. As part of that CBMEM
initialisation hooks will need to move from romstage to bootblock.

The interface towards platforms and drivers will change to use one of
CBMEM_CREATION_HOOK() or CBMEM_READY_HOOK(). Former will only be called
in the first stage with CBMEM available.

Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-20 07:15:39 +00:00
Jianjun Wang 20a87c0bed libpayload/pci: Add pci_map_bus function for MediaTek platform
Add 'pci_map_bus' function and PCIE_MEDIATEK config for MediaTek
platform.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-05-20 02:53:35 +00:00
Jianjun Wang 2ad74deb2a libpayload/pci: Add support for bus mapping
Move the common APIs to pci_ops.c and IO based operations to
pci_io_ops.c, and add pci_map_bus_ops.c to support bus mapping.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-05-20 02:51:33 +00:00
Jianjun Wang 7439a49f4c soc/mediatek: Fill coreboot table with PCIe info
In order to pass PCIe base address to payloads, implement pcie_fill_lb()
to fill coreboot table with PCIe info.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-05-20 02:49:42 +00:00
Dtrain Hsu 36618e882d mb/google/brya/var/kinox: Remove stop pin declaration for LAN
Remove the stop pin declaration for LAN. Confirmed with LAN vendor,
8111K do not need to implement stop pin. It caused S0ix fail.

BUG=b:232327947
TEST=Build and suspend_stress_test -c 5 pass

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9bdaa28cd879c1ea7de2de8afb25761df39bcfc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-19 18:49:40 +00:00
Jianjun Wang d16c2aa6de coreboot_tables: Add PCIe info to coreboot table
Add 'lb_fill_pcie' function to pass PCIe information from coreboot to
libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the
__weak function.

ARM platform usually does not have common address for PCIe to access the
configuration space of devices. Therefore, new API is added to pass the
base address of PCIe controller for payloads to access PCIe devices.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
2022-05-19 16:34:55 +00:00
Arthur Heymans cd259cb08a arch/x86/car.ld: Add a Kconfig param to flag AGESA brokenness
AGESA has a lot of code in the .data section (initialized data). However
there is no such section in CAR stages as the code runs in XIP mode and
CAR is too small to contain the data section. When the linker can not
match code to a section it will just append it, which is why AGESA
worked at all.

Follow-up patches will attempt to fix AGESA and set Kconfig parameter to
'n'. After all AGESA sources have been fixed, this can be removed.

Change-Id: I311ee17e3c0bd283692194fcee63af4449583d74
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-05-19 11:07:35 +00:00
Reka Norman e46a977541 mb/google/nissa: Rework LTE GPIO configuration
Currently, the LTE pins are enabled in gpio.c, then disabled in
fw_config.c if LTE is not present. However, since there's a short delay
between mainboard_init() and fw_config_handle(), this means that when
LTE is not present GPP_H19 (SOC_I2C_SUB_INT_ODL, used for the SAR
sensor) will be floating for a short period of time.

Rework the GPIO config so that the LTE pins are disabled in the
baseboard, then enabled in fw_config.c for variants using LTE. However,
this doesn't work for WWAN_EN and WWAN_RST_L since they need to be
enabled in bootblock. So these are instead enabled in the variant
gpio.c, then disabled in fw_config.c if LTE is not present.

BUG=None
TEST=LTE still works on nivviks

Change-Id: I9d8cbdff5a0dc9bdee87ee0971bc170409d925a2
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-19 11:06:38 +00:00
Teddy Shih eb0c90aec5 mb/google/dedede/beadrix: Update PCIe and SATA pins for Realtek RTL8822CE suspend
To make sure Realtek RTL8822CE suspend stress test smoothly, we remove
1c.7 as wireless LAN (WLAN) connects the signal PCIE_4 and it will map
to 1c.7. refer to Intel Simon comment (https://partnerissuetracker.corp.google.com/issues/230386474#comment12),
as well as, remove redundant 17.0 and 1c.6 that both are described by
baseboard/devicetree.cb

BRANCH=dedede
BUG=b:230386474
TEST=on beadrix, verified by Realtek RTL8822CE can run suspend stress
test properly.

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ib418eed57f07afaa6b397b42a057808eab142f7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2022-05-19 11:06:01 +00:00
Angel Pons c2461a174d soc/intel/common/block/smbus: Deduplicate some code
Reuse existing SMBus code from southbridge/intel/common/smbus_ops.h.

Change-Id: Iea4f6886bb49590f7f96abbfbe631ac9d4dda902
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64432
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-19 11:05:27 +00:00