Commit Graph

21987 Commits

Author SHA1 Message Date
Barnali Sarkar 130f266c6e soc/intel/common/block: Add max SPI transaction time-out as 5 sec
Earlier 15ms time-out was kept for SPI transactions which was not
enough for SPI Erase transactions.

Increase the max time-out time to 5 secs which was present in SKL
before common code.
This increase in time-out won't disturb other SPI transactions like
Read, Write or Read Status, since, for those it will come out of
the loop once FDONE bit or FCERR bit is set.

BUG=b:63959637
BRANCH=none
TEST=Built and booted poppy and all SPI transactions succeeded.

Change-Id: I1c015d80b33677de11755fb2097373631d1fa8c4
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-24 23:59:51 +00:00
Patrick Georgi 695576799b google/reef: Configure EN_PP3300_DX_LTE on coral
BUG=b:63876329
BRANCH=none
TEST=none

Change-Id: I98c700d5b928c031129cf0138d22652a28d1ad1d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-24 18:19:21 +00:00
Patrick Georgi 5266c3b778 google/reef: copy gpio.c for coral
It requires changes to match the hardware. Except for the weak
attributes that are now removed in coral's copy, the file is identical
to the baseboard version.

BUG=b:63876329
BRANCH=none
TEST=none

Change-Id: Ib0c5f0ecae9919f20631dacef0253416989fb011
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-24 18:19:14 +00:00
Martin Roth e1695e2cd4 nb/intel/i440bx: Add final newline to raminit.c
The newline lint check just went in, and immediately broke the build
due to a commit that went in earlier today.
This fixes the build.

Change-Id: Ic4ba8ce0c8085861bc6c654afdee3fea9f4621fc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-24 17:48:54 +00:00
Patrick Rudolph 0cce14341a mb/lenovo/t430: Disable `usb_always_on` by default in CMOS
Fix regression introduced by commit 7ffb329f.

The default value for usb_always_on is no longer sane and is replaced
by the same default that is used on all other boards (disabled).

Change-Id: Ia8854a8491bc56507d01e08e1ca1e195a1d62bfc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-24 16:49:12 +00:00
Patrick Rudolph c1055ab07a soc/intel/skylake: Use common opregion implementation
Enable SOC_INTEL_COMMON_GFX_OPREGION for all FSP versions.
Allows to get rid of opregion.c, as it's no longer needed.

Change-Id: I39190488e12917a09dbf7ee3947a33940ebc290b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-07-24 16:48:30 +00:00
Martin Roth 43be77db31 util/lint: Update final newline check
- Exclude .png and .patch files.
- Turn into a lint-stable test.

Change-Id: I4a5c77d7856bc5017ba441d458378b4837c1c7d5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-24 16:28:24 +00:00
Arthur Heymans ad5014952b sb/intel/i82801jx: Generate default fadt and madt
Function copied from i82801gx with offsets fixed for i82801lx.

Change-Id: Ib420c69470c3190cc1eac234ce68a18382fbc04a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-24 15:09:27 +00:00
Martin Roth b4560cd523 Update files with no newline at the end
Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24 15:08:16 +00:00
Martin Roth 467a87abce Fix files with multiple newlines at the end.
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20704
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24 15:08:08 +00:00
Wisley Chen fa1d383f93 mainboard/google/soraka: pull high TOUCHSCREEN_STOP_L pin
After updating to Wacom Firmware version 501, touchscreen can't work.
Wacom FW (ver. 501) enables STOP function.
STOP Pin:
  High: Normal Operation
  Low: Stop Scanning
So pull TOUCHSCREEN_STOP_L high

BUG=b:37007801, b:37265219
BRANCH=none
TEST=manual testing on Soraka board and touchscreen works at boot
and after suspend/resume.

Change-Id: I8a2bdce1554fd99dea30cf91fa48d0529f40b7b0
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/20664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-24 06:07:04 +00:00
Arthur Heymans 41114650d0 sb/intel/i82801jx: Add function to detect s3 resume
File copied from i82801gx.

Change-Id: I107087b6448f18b6a5ae21c2ae0392c057dd23b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23 20:34:11 +00:00
Arthur Heymans e5dcaf1269 sb/intel/i82801jx: Add addition IO resources
Adapted from i82801gx.

Change-Id: I9108a45135908b7c4e74e9df3bb8f89f55893299
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23 20:33:34 +00:00
Keith Hui 899577676b asus/p2b-d: Use romstage from asus/p2b-ds.
The romstage for both is line-for-line identical.
Merge both into P2B-DS so it benefits from my
modernization efforts.

Change-Id: Idd964f4c5c4dfd9e2e0ac4a4f41e4ee9a84a729c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23 20:22:55 +00:00
Keith Hui 7654a0db7e asus/p2b-f: Use romstage from asus/p2b-ls.
The romstage for both is line-for-line identical.
Merge both into P2B-LS so it benefits from my
modernization efforts.

Change-Id: I2d1a46236f83a4955ceb5e98b576cce0560f28df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23 20:22:46 +00:00
Keith Hui fb0984d30f 440BX boards: Drop unused #includes from romstage
Romstage of many 440BX boards included headers that are not used.
Remove them as part of a bigger cleanup effort.

Change-Id: I89ddeda3c90e1a4907c05851185b69f3b29e54ba
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23 20:22:29 +00:00
Keith Hui c903b9376e asus/p2b-ls: Drop onboard LAN from devicetree.cb
I am able to complete a	board-status run over onboard ethernet
(ie. it works) without this entry, so it's not necessary.

Change-Id: Iabdf1a1ff3c904bea1b7b5eaefb1d23831dd2cb9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23 20:20:31 +00:00
Keith Hui 078e324080 northbridge/intel/i440bx: Merge RAM init routines
There are 4 routines used in RAM init that most if not all
i440bx mainboards call in the same order. Implements a single
RAM init routine for them to allow for future consolidation.
Boards to be changed to use this one routine in a future change.

Change-Id: Ib553b07b117de12b7982586bce0f9355f55013a0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23 20:20:26 +00:00
Martin Roth 5bb5307c7d depthcharge: Update build
- Add prompt so the defconfig can be selected for the build.
- Remove target rename code from makefile.  The old versions don't build
with the latest vboot, so this isn't useful anymore.
- Change $(info ...) to an echo.  info prints immediately when
evaluated, which made it print when it shouldn't have, on make clean
for example.
- Split up single line shell scripts into multiple lines
- Change checkout target to only update the commit id when actually
changing versions instead of on every build.

Change-Id: I46fc2822cf93c821b402e8961ceecedc088f486c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-23 20:17:45 +00:00
Martin Roth f02171efc6 depthcharge: Update stable commit id
Update from commit eb583fa8 - Wed Mar 29, 2017
(rk3399_sdhci: Reintroduce PHY power-cycling at 52MHz)

to commit 5a086f5c - Tue Jul 11, 2017
(ps8751: enable software sync)

This brings the stable version of depthcharge forward by 74 commits.

Change-Id: I3a3719fa3a91824042d452de7774be85b884d96d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-23 20:17:27 +00:00
Rajat Jain 2671afcbbc mainboard/google/{poppy,soraka}: Enable S0ix
Enable S0ix for poppy and soraka in their device trees respectively.

BUG=b:36630881
BRANCH=none
TEST=Verified S0ix and S3 operation on Poppy and Soraka (250+ iterations).

Change-Id: I9ba91499e54f729970448af6f71804ad5b3cb836
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-23 04:01:04 +00:00
Keith Hui 9aa45e6952 northbridge/intel/i440bx: Move NB macro to i440bx.h
This move makes the NB macro more widely available,
in preparation for implementing get_top_of_ram().

Change-Id: Icd8e82cfdfdccb662b2139d0e5d1d5af72cbae7f
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-22 22:50:08 +00:00
Martin Roth 3f6421e1fa soc/intel/cannonlake: Keep variable from going out of scope
The variable p was going out of scope while still being pointed to by
*cpu_name.

Fix coverity ID 1378215 (Pointer to local outside scope)

Change-Id: I6ad7b1919104b4d97869efe5065e39c2a43de638
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2017-07-22 22:49:46 +00:00
Furquan Shaikh 4a1d450d07 mainboard/google/poppy/variants/soraka: Update GPP_{D1,D2,B7} config
GPP_B7, GPP_D1 and GPP_D2 are not used going forward. Mark them as NC
in gpio table.

BUG=b:62322846,b:62240755

Change-Id: I7aee08314e6ce96d5913ae315bf75f5c04ab7370
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20672
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-22 05:25:01 +00:00
Furquan Shaikh 907a0cfc30 mainboard/google/poppy/variants/soraka: Define separate gpio tables
Now that soraka is starting to deviate from the baseboard w.r.t. gpio
settings, make a new copy of gpio table before we make any
variant-specific changes in it.

BUG=b:62240755,b:62322846
BRANCH=None
TEST=Verified with gpio_debug=1 in skylake/gpio.c that the gpio
configuration before and after this change remains same.

Change-Id: I448d18f18b63e9bfb739c518d599de3b9b602dc2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-22 05:24:57 +00:00
Logan Carlson 50522254fb arch/arm/armv7: Correct checkpatch errors
- Correct whitespace issues with files under arch/arm/armv7.
- Fix comments and remove unnecessary line continuations in mmu.c

Change-Id: I69d50030b07b1919555feca44967472922176a81
Signed-off-by: Logan Carlson <logancarlson@google.com>
Reviewed-on: https://review.coreboot.org/19996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-21 20:40:27 +00:00
Martin Roth 80358a1f47 Revert "soc/intel/cannonlake: Add postcar stage support"
This reverts commit 399c022a8c.

This was merged too early.  I'll repost it.

Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20686
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-21 17:39:10 +00:00
Martin Roth 70de396958 Revert "soc/intel/cannonlake: Call into FSP siliconinit"
This reverts commit dbe7f893c0.

This was merged too early.  I'll repost it.

Change-Id: Ife56f45e91c0b961d0fad0e1872c6df3f9e18973
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20685
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-21 17:32:07 +00:00
Martin Roth b137c13e57 I82801JX: Add IS_ENABLED around config options
This chipset was just added and had a few places that needed to be
fixed.

Change-Id: Ief048c4876c5a2cb538c9cb4b295aba46a4fff62
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20684
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-21 17:00:01 +00:00
Hannah Williams 837afb0938 soc/intel/apollolake: Add pci device id for GLK IGD
Change-Id: Id2c94afed8976687524a0913ea1c13aeddd98333
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/20654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-21 15:56:48 +00:00
Lijian Zhao dbe7f893c0 soc/intel/cannonlake: Call into FSP siliconinit
The following changes can make system call into FSP siliconinit and exit
from that until payloads.

1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.

Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21 15:56:16 +00:00
Lijian Zhao 399c022a8c soc/intel/cannonlake: Add postcar stage support
Initialize postcar frame once finish FSP memoryinit

Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21 15:55:40 +00:00
Martin Roth 4cfae2f574 util/lint: exclude patch files from asm syntax check
This allows the paches to add cross-compile support for true x86 16-bit
GCC (ia16) to go in.

Change-Id: If9246b5fb2f3578afea601fd63b7d716ddf8597e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/19714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-21 15:55:21 +00:00
Stefan Reinauer e2804c14a4 util/vgabios: Don't call redefined printk in printk
A few pieces of coreboot code (like the video bios emulator) are
imported from other code bases, and hence might call printf. In
order to see the output, we redefine printf to printk. However,
when we are re-importing this code in a userspace utility, we might
call printk instead of printf if we're not careful.
A good fix for this would be to not call printf in coreboot ever.
As a short term fix to keep testbios from segfaulting, we just
don't call printf from printk, so we don't cause our own stack to
overflow.

Change-Id: I789075422dd8c5f8069d576fa7baf4176f6caf55
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-21 15:45:41 +00:00
Arthur Heymans 3876f24221 nb/intel/x4x: Rework programming DQ and DQS DLL timings
This does the following:
* Clarify that settings are set to the same value for each rank;
* Allows to program coarse
* Fix some style issues like white spaces between arithmetic
  operators.

Change-Id: I3a9e28cfec915a0bb15789c23bea259f621b5096
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-21 15:45:16 +00:00
Arthur Heymans 12a4e98cea nb/intel/pineview/raminit: Refactor timings selection
This does not use loops to compute timings but uses DIV_ROUND_UP.

Another thing affected by this patch are minimum timings. Presumably
those only need to be guarded against on DDR3. With this change
timings are set up like vendor (with tWTR below previous minimum)

TESTED on Intel D510MO

Change-Id: Ia374f26e5bbb8b90d90c24ae6c20412ba53bd7b6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-21 15:45:05 +00:00
Arthur Heymans 349e08535a sb/intel/i82801jx: Add correct PCI ids and change names
Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-21 15:44:19 +00:00
Arthur Heymans 7b9c139ac2 sb/intel/i82801jx: Copy i82801ix
Change-Id: I878960e7e0f992426382ca717b8b42787f01ebc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-21 15:43:18 +00:00
Subrata Banik c3198543b6 soc/intel/skylake: Perform LPC offset read after lockdown operation
This patch is to provide an additional read LPC pci offset register
BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is
successful.

Change-Id: I308c0622d348fc96c410a04ab4081bb6af98e874
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21 14:46:13 +00:00
Subrata Banik 8e39009c57 common/block/fast_spi: Perform SPI offset read after lock down operation
This patch is to provide an additional read SPI pci offset register
BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is
successful.

Change-Id: I3b36c1a51ac059227631a04eb62b9a6807ed37b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21 14:45:31 +00:00
Subrata Banik ba3ae3eead soc/intel/skylake: Rectify LPC Lock Enable (LE) bit definition
LPC pci config register BIOS Control (BC) - offset 0xDC bit 1
is for Lock Down.

Change-Id: I838dd946b8cdb7114f58ccc5d02159f241f0bad0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21 14:44:22 +00:00
Hannah Williams 3ff14a0c85 soc/intel/apollolake: Bring in delta for GLK SOC
Change-Id: I3e76726bb77f0277ab5776ae9d3d42b7eb389fe3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/19603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21 03:59:09 +00:00
Lijian Zhao a77c68adf3 soc/intel/cannonlake: Make ramstage relocatable
Relocate ramstage into CBMEM.

Change-Id: I0543d25d722c5872f4f139a98e5125a41cc40653
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20 21:57:10 +00:00
Marshall Dawson 148a7a60d8 libpayload: Fix unaligned buffer logic in default_memset
Fix an issue when setting an unaligned buffer where n is less
than the difference of the rounded up pointer and the pointer.
This was identified where n=1 was passed.  n was decremented
once, as expected, then decremented again after the while()
evaluated to false.  This resulted in a new n of 4GB.

Change-Id: I862671bbe7efa8d370d0148e22ea55407e260053
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-07-20 21:38:14 +00:00
Aaron Durbin 65943e1670 soc/intel/common/gpio: add helpers for relative pin calcuations
The gpio numbers are global, but they have their respective place
within each community and the group within their community. For
all the calculations open coding this calculation convert them to
use the helpers.

Change-Id: I0423490ae1740ef59225a70fea80a7d91ac2a39a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-20 21:08:35 +00:00
Aaron Durbin ac8e4db246 soc/intel/common/gpio: fix gpi_status_get()
A pad number is passed into gpi_status_get() to determine if its
associated bit is set from a generated event. However, the
implementation wasn't taking into account the gpi_status_offset
which dictates the starting offset for each community. Additionally,
the max_pads_per_group field is per community as well -- not global.
Fix the code to properly take into account the community's
gpi_status_offset as well as the max_pads_per_group.

Change-Id: Ia18ac6cbac31e3da3ae0ce3764ac33aa9286ac63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20652
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2017-07-20 17:06:48 +00:00
Nico Huber ea864f4a2d soc/intel/skylake: Remove dead `CONFIG_PRE_GRAPHICS_DELAY`
`CONFIG_PRE_GRAPHICS_DELAY` was only applied on a dead code path in
`igd.c` that is guarded by always selected `CONFIG_ADD_VBT_DATA_FILE`.
Nobody missed it for nearly a year, plus, it's not applied on the GOP
path, let's drop it.

Change-Id: I0b70cce3a3f2b50cb4e72c4d927b35510ff362a2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20 15:45:20 +00:00
Nico Huber 959ac071d4 soc/intel/skylake/igd: Remove dead quirk from dead code path
This quirk was superseded a view lines above. Also the whole path is
guarded by `CONFIG_ADD_VBT_DATA_FILE` which is always selected for
nearly a year now.

Change-Id: I7fc5184d6e81e4588616e0302dee410e74bdab5a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-07-20 15:45:11 +00:00
Nico Huber 9dc62ea133 soc/intel/skylake: Fix broken memory info HOB scanning
It looks like this code was written with completely different semantics
in mind. Controllers, channels and DIMMs are all presented in their phy-
sical order (i.e. gaps are not closed). So we have to look at the whole
structure and not only the first n respective entries.

Change-Id: I8a9039f73f1befdd09c1fc8e17cd3f6e08e0cd47
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20650
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-20 15:44:59 +00:00
Marshall Dawson fb66e81e6c x86/lapic/secondary.S: Align stack for _secondary_start
At a process _start, the stack is expected to be aligned to a
16-byte boundary.  Upon entry to any function the stack frame
must have the end of any arguments also aligned.  In other words
the value of %esp+4 or %rsp+8 is always a multiple of 16 (1).

Align the stack down inside _secondary_start and preserve proper
alignment for the call to secondary_cpu_init.

Although 4-byte alignment is the minimum requirement for i386,
some AMD platforms use SSE instructions which expect 16-byte.

1) http://wiki.osdev.org/System_V_ABI
   See "Initial Stack and Register State" and "The Stack Frame"
   in the supplements.

BUG=chrome-os-partner:62841664

Change-Id: I72b7a474013e5caf67aedfabeb8d8d2553499b73
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20 15:34:21 +00:00