Enable the backlight in the OS callback to SMI for APMC. This keeps
the backlight off until the OS is ready to display something.
BUG=b:72694972
TEST=Backlight turns on at ChromeOS splash screen
Change-Id: Idf32b1a3d45971883571a829a5c0c1f8563bb1f7
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add the mainboard resume function and __weak variant override.
Change-Id: I808734208bd1ce81428771ea203709b53db56cd3
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This updates the IDPROM region along with the unused regions.
Change-Id: If73bb8162d3d0733e3bd8561cd5549f2184db2be
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/27505
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the EC under the LPC PCI device to make sure that the SSDT path
matches the DSDT. Matches the behaviour of all other Lenovo devices.
Change-Id: I9ded7f639866d71d39ea0d5d0c36602d386c177f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
there are 3 thermal sensors and index is:
0: 1 Charger
1: 1 SOC
2: 0 CPU
it needs to adjust sensor to index 2 to have correct
CPU temperature.
BUG=b:111284412
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I27afb6c5b64b0c39d6db15e6c61ea16a1fda1ca3
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This device claims to run at 75MHz with dual read, but it is not always
reliable. Add an option to change the SPI flash speed to 16MHz, to avoid
any problems.
BUG=b:111363976
TEST=manually try to get my em100 running (it doesn't yet)
Change-Id: I78d3d32c467aac82c72d31c773bfb0f69808aed4
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This applied to AMD devices as well as Intel, although the mechanism is
different. Move the option to a common place.
BUG=b:111363976
TEST=USE=em100-mode emerge-reef coreboot
See that a message appears:
* Enabling em100 mode (slow SPI flash)
Change-Id: Iea437bdf42e7bc49b1d28c812bfc6128e3eb68bd
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add new Pantheon sku-id for loading vbt-pantheon.bin
BUG=b:78663963
BRANCH=firmware-nami-10775.B
TEST=Boots to OS and display comes up.
Check the board specific vbt binary loaded.
Change-Id: I1ee156372754ac0e77caae5959a9ca9884de95f4
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27432
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FCAM_PWR_EN gpio should be GPP_B4 according to the latest board
schematics.
Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e
Signed-off-by: Ricky Liang <jcliang@chromium.org>
Reviewed-on: https://review.coreboot.org/27433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Currently thermal event support can not be disabled at board level.
Define and dependent code are placed in same file.
Move define of HAVE_THERM_EVENT_HANDLER to mainboard file.
Change-Id: Icb532e5bc7fd171ee2921f9a4b9b2150ba9f05c5
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27415
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enabling of TBMC device on AP side requires corresponding support on the
EC side as well. Since not all octopus variants have tablet mode support
enabled, this change enables TBMC device only for phaser.
BUG=b:111264961
Change-Id: I1ce181baa8ebaff0a9d767e97ddc256eef9789e8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Remove "IshEnable" from soc_intel_skylake_config since it's not
used anymore.
Enable/disable ISH by checking if ISH device is turned on or not.
Refer to https://review.coreboot.org/#/c/coreboot/+/26485/.
BUG=b:79244403
BRANCH=none
TEST=Built.
Change-Id: I4d2889af118659852431c87cb516fd19b577efc5
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/26521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To enable ISH device on atlas board, change "device pci 13.0 off end" to
"device pci 13.0 on end" in file
mainboard/google/poppy/variants/atlas/devicetree.cb. "IshEnable" is
not needed.
Config atlas board specific ISH setting in devicetree.cb.
Dynamically load gpio setting for ISH enabled/disabled cases.
BUG=b:79244403
BRANCH=none
TEST=Verified on Atlas board with ISH rework. ISH log showed on console.
Change-Id: I8269a85cd2ab7917bfc0e7d63d988e0e678d0bf2
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/26486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to get better performance, map dram as cached after dram ready
in romstage.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui. Need a futher check after dram
calibration code ready.
Change-Id: Ie541fe08ee1d5b260abbabc0a5c18fb04e602b9c
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27304
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor MMU operation code which will be reused among similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm
Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add an extra space after 8th value on each line to make it easier
to count the values.
Update the empty spd to remove two random 0x80 values.
BUG=None
TEST=None
Change-Id: If330dbf0c133f65aedddc58ecb351a80b0e45a05
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/27423
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set cntfrq_el0 to provide correct timer frequency.
Change-Id: I4b6d0b0cf646a066fc5a51552a1891eccbd91e5e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25450
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Print some useful information about the board.
Change-Id: I0acac7a29290bc2eb9f4283317165fa0cf1b24e1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25449
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Configure and enable MMU.
* Cover the whole I/O space.
* A minimum of 512KB TTB space is required.
* Use secure mem attribute as firmware is running in ARM TZ region.
Tested on Cavium SoC.
Change-Id: I969446da62b4cc7adf9393fab69ff84ebf49220d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This adds Cavium CN81xx SoC and SFF EVB files.
Code is based off of Cavium's Octeon-TX SDK:
https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK
BDK coreboot differences:
bootblock:
- Get rid of BDK header
- Add Kconfig for link address
- Move CAR setup code into assembly
- Move unaligned memory access enable into assembly
- Implement custom bootblock entry function
- Add CLIB and CSIB blobs
romstage:
- Use minimal DRAM init only
devicetree:
- Convert FTD to static C file containing key value pairs
Tested on CN81xx:
- Boots to payload
- Tested with GNU/Linux 4.16.3
- All hardware is usable (after applying additional commits)
Implemented in future commits:
- Vboot integration
- MMU suuport
- L2 Cache handling
- ATF from external repo
- Devicetree patching
- Extended DRAM testing
- UART init
Not working:
- Booting a payload
- Booting upstream ATF
TODO:
- Configuration straps
Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688
Signed-off-by: David Hendricks <dhendricks@fb.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
These two files were added before I was able to get the updated linter
committed. Updated/Add the headers so the stable header lint check
can be updated.
Change-Id: I464ddecb5eebe8c5b907f3dcfeab1b06501af6ab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
the FPMCU_INT_L on GPP_C11 is active low but the kernel irq handler is
defined as IRQF_TRIGGER_LOW, so do not invert it twice.
BRANCH=poppy
BUG=b:78613978
TEST=On Nocturne, the 'cros_ec' IRQ count in /proc/interrupts does not
increment wildly.
Change-Id: I56c13c797b133dd22669a2299bcd16ef14eed335
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/27221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Clean up leftovers of old SPD generation and utilize
common procedure to produce SPD binary.
Change-Id: I4e48817c03b4372887bc0ea14209736ae2b4e48f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Until now, chromeec was doing keyboard initialization for the boards
that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not
leave the keyboard controller in a default reset state. This could
result in payloads or OS failing to probe the controller as there
could be stale data buffered in the controller during the handoff.
Since the boards using chromeec already perform keyboard
initialization in payload, there is no need to initialize the
keyboard in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD
selection from all google mainboards using chromeec.
BUG=b:110024487
Change-Id: I9af48e648231c18f98d0cc1ddd178b8d00082b0a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Until now, chromeec was doing keyboard initialization for the boards
that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not
leave the keyboard controller in a default reset state. This could
result in payloads or OS failing to probe the controller as there
could be stale data buffered in the controller during the handoff.
Since the boards using chromeec already perform keyboard
initialization in payload, there is no need to initialize the keyboard
in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD
selection from all google mainboards using chromeec.
BUG=b:110024487
TEST=Keyboard works fine after booting to OS even if user hits keys
during BIOS to OS handoff.
Change-Id: I1f49b060eb005c0f2b86f9d68d6758954eeb3cf0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To uniform the naming of the 'Dual Graphics' mode amongst the ThinkPads that
support it, the T400 CMOS value needs a change. This was the outcome of a
discussion on another patch: https://review.coreboot.org/#/c/coreboot/+/23040/
This might cause breakage for automated NVRAM configuration scripts, and
manuals. I only found one manual using the previous 'Switchable' option:
https://libreboot.org/docs/install/r400_external.html#a-note-about-gpus
Change-Id: I2e4d8bafbae5de97c78dab118f75fdefff1d7c37
Signed-off-by: Nico Rikken <nico@nicorikken.eu>
Reviewed-on: https://review.coreboot.org/27158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Enable Image Processing Unit and CIO2 device that constitute IPU3.
BUG=None
TEST=Build and boot up into Nocturne platform and check with lspci.
Change-Id: Ic2edf5ec7bde5c55ce1b13cf7b680094a9fffc6a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://review.coreboot.org/27124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Sensors and CSI2 receiver configuration for Nocturne platform.
IMX355 module has VCM, NVM and is on the second port of receiver.
IMX319 module has NVM and is on the first port of receiver.
Change-Id: I37c877df8062d5c79e25ed27775ab58e977555db
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://review.coreboot.org/26283
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These bits start the acquisition process. They should only be set by the
driver.
BUG=b:74363445
TEST=compile
Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/27265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
According to sona thermal table, PL2 need to check cpu id.
And then set PL2 value.
BUG=b:110867809
TEST=The thermal team verify OK
Change-Id: I5759fb3c685e3d4eef1be054541f950843d19874
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
