Commit Graph

23831 Commits

Author SHA1 Message Date
Kevin Chiu 2be3bdd748 google/snappy: enhance CCD type-A USB 2.0 phy strength
Alan(11")/BigDaddy(14") right type-A(port#2), CCD(port#4) are
occasionally undetectable. USB 2.0 phy needs an override to enhance
drive strength.

right type-A port#2
PERPORTPETXISET: 4
PERPORTTXISET: 4
IUSBTXEMPHASISEN: 1
PERPORTTXPEHALF: 0

CCD port#4
PERPORTPETXISET: 7
PERPORTTXISET: 7
IUSBTXEMPHASISEN: 1
PERPORTTXPEHALF: 0

BUG=b:72922816
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I2b18c11709280d00ec3a6ef10f93a416acb4fb45
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/24969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-06 17:40:36 +00:00
Daisuke Nojiri d182b63347 mainboard/google/fizz: Check HDMI HPD and DisplayPort HPD
Some type-c monitors do not immediately assert HPD. If we continue
to boot without HPD asserted, Depthcharge fails to show pictures
on a monitor even if HPD is asserted later.

Also, if an HDMI monitor is connected, no wait is needed. If only
an HDMI monitor is connected, currently the API always loops until
the stopwatch expires.

This patch will make the AP skip DisplayPort wait loop if it detects
an HDMI monitor. And if an HDMI monitor is not detected, the AP will
wait for DisplayPort mode (like before) but also its HPD signal.

This patch also extends the wait loop time-out to 3 seconds.

BUG=b:72387533
BRANCH=none
TEST=Verify firmware screen is displayed even when a type-c monitor
does not immediately assert HPD. Verify if HDMI monitor is connected,
AP does not wait (and firmware screen is displayed on HDMI monitor).

Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-06 08:50:51 +00:00
Duncan Laurie 50f06a14cd soc/intel/skylake: Remove MCFG constants
The MMCONF base address and length are set in Kconfig so it does
not need to be redefined by the SOC as the code can just use the
Kconfig variable directly.

Tested on a fizz board to ensure MCFG is still created properly.

Change-Id: I5fd472b1afc8264823a2b9db0f296fbfb6b1ecc0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/24975
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06 08:48:51 +00:00
Duncan Laurie fd50b7c3d7 soc/intel: Fix MCFG end bus number
The ACPI MCFG table is generated with a static end bus number of 255,
which expects that the reserved range in E820 is 256MB.  However the
actual MCFG range is configurable with Kconfig, so these two values
may not match when the OS tries to determine the range:

PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
PCI: MMCONFIG 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) (size reduced!)
acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge

Instead of forcing the end bus number to be 255 use the Kconfig value
to set it based on the current configuration.

Tested on a fizz device to ensure that the kernel no longer complains:

PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000)

Change-Id: I999ea9b72b9deba5f27dd692faa0408427a0bf89
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/24974
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06 08:47:59 +00:00
Duncan Laurie 3879ef49ea mb/google/fizz: Skip FSP init for UART 0
The GPIO pins for UART 0 on Fizz are routed to the add-in card slot
and should not be used as a UART device.  coreboot is setting the
pins to GPIO Mode but FSP is re-configuring them for Native Mode
and the behavior is unexpected when the kernel tries to initialize
the UART device.

The UART 0 device is PCI function 0 so it needs to be enabled for
other functions to be visible to the OS so it can't just be disabled.
Instead, set the device to PchSerialIoSkipInit so that FSP will not
change the pin state.

BUG=b:73006317

TEST=Tested with add-in card on fizz hardware to ensure the pin state
does not change when FSP runs or the kernel boots.

Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/24973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-06 08:46:37 +00:00
Martin Roth 069ca66ea4 soc/amd/stoneyridge: Add ST/CZ SMBus device id
The SMBus PCI device ID for Stoney wasn't updated when the code was
pulled over from hudson.  This means that the IOAPIC wasn't being
initialized in coreboot.

BUG=b:74070580
TEST=Boot Grunt, see IOAPIC init messages in console.

Change-Id: Ida5d3f3592488694681300d79444c1e26fff6a1a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/24930
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06 08:45:32 +00:00
Lijian Zhao 345d1e3962 Revert "mainboard/google/meowth: enable PCH iSCLK"
This reverts commit 2e81f394cf, as it will
have side effect that will make system shutdown failure. System will not
enter S5 sleep state, instead a global reset will be generated.

Once camera driver ACPI framework ready, isclk programing will be moved
into APCI method, in _PS3, isclk will be turned off to save power.

BUG=b.72532565
BRANH=master
TEST=Apply the changes and flash coreboot, on meowth devices, issue
"halt" in OS stage, system can shutdown successfully.

Change-Id: If35697911f97c524d9b52bdf4dae5c9ef1cc8618
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06 08:03:28 +00:00
Matt DeVillier 4132893808 ec/chromeec: Fix check for UHEPI support
Commit 1dfc2c3
[google/chromeec: Enable unified host event programming interface]
added support for UHEPI, but google_chromeec_is_uhepi_supported()
incorrectly treats negative error return codes from
google_chromeec_check_feature() as supported. Fix this check to only
treat positive return values as supported, as per the original intent.

Test: boot google/lulu, verify cbmem console reports UHEPI not
supported even if feature check returns error code, verify lid/kb
wake events correctly wakes the device from S3/sleep.

Change-Id: I7846efb340bc1546b074e8502daf906c444bd146
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-05 18:24:04 +00:00
Furquan Shaikh 908ea9132b mb/google/poppy: Allow use of optional secondary SPD
This change adds support for variants to use secondary SPD if
required. This enables a variant to have different types of memory
supported using the same image.

BUG=b:73514687

Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-05 17:56:08 +00:00
Furquan Shaikh 39d3021b16 mb/google/poppy/variants: Set pch_trip_temp to 75C
Similar to Soraka, this change sets the pch_trip_temp value to
75C. This is important so that PMC can shutdown the thermal sensor
when CPU is in C-state and DTS temp <= pch_trip_temp.

BUG=b:74089135

Change-Id: Ic46fa0681796b821dfb014ab91734c960df7846a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-05 17:56:01 +00:00
Furquan Shaikh fa9f107319 cpu/x86/mp_init: Increase AP check-in time-out to 1second
Currently, the AP check-in time-out in bsp_do_flight_plan is set to
100ms. However, as the number of APs increases, contention could
increase especially for resource like UART. This led to MP record
time-out issues on KBL platform with 7 APs and serial-console enabled
BIOS image.

This change increases the time-out value to 1 second to be on the safer
side and let APs check-in before continuing boot.

BUG=b:74085891
TEST=Verified that MP record time-out is not observed anymore on Nami.

Change-Id: I979c11a10e6888aef0f71b5632ea803a67bbb0ff
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-05 17:55:44 +00:00
Furquan Shaikh 10c3b96ac7 soc/intel/common/block/smm: Add configurable delay before entering S5
This change adds a configurable delay in milliseconds before SLP_EN is set in
SLP_SMI for S5. Reason for doing this is to avoid race between SLP and power
button SMIs.

On some platforms (Nami, Nautilus), it was observed that power button SMI
triggered by EC was competing with the SLP SMI triggered by keyboard
driver. Keyboard driver indicated power button press which resulted in
depthcharge triggering SLP_SMI, causing the AP to enter S5. However, the power
button press also causes the EC to send a pulse on PWRBTN# line, which is
debounced for 16ms before an interrupt is triggered. This interrupt was
generated after SLP_SMI is processed which resulted in the device waking back up
from S5.

This change adds a config option SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS which is
used to add a delay before SLP_EN is set for S5. This change should only affect
CHROMEOS boards as the config option will be 0 in other cases.

BUG=b:74083107
TEST=Verified that nami, nautilus do not wake back from S5 on power button press
at dev mode screen.

Change-Id: Iaee19b5aba0aad7eb34bd126fda5b0f6ef394ed7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-05 17:55:32 +00:00
Furquan Shaikh 591be2d581 lib: Add delay.c to smm
BUG=b:74083107

Change-Id: I98ab5c84268e8754fbaf6a30cd26fe1084e45a20
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-05 17:55:23 +00:00
Paul Menzel bcf9a0a7ab nb/intel/i945/gma: Log configured VGA mode
This is useful information, when debugging problems related to graphics.

Change-Id: Iacb0ae5f012207192379fd07e91f4687ec32cdfb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/23807
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-03 15:19:38 +00:00
Nico Huber 8aaa00401b sb/intel/common: Fix conflicting OIC register definition
Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a
common location) makes some platforms use the wrong OIC register defi-
nition. It was extended to 16-bit in the corporate version of ICH10.
So let's give the new size and location a new name: EOIC (extended OIC).

This only touches the systems affected by the mentioned change. Other
platforms still need to be adapted before they can use the common RCBA
definitions.

Change-Id: If9e554c072f01412164dc35e0b09272142e3796f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/24924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-03-02 17:21:06 +00:00
Aaron Durbin 60320182d0 console: only allow console messages after initialization
The console subsystem allows printk() to be called prior to the
drivers and/or infrastructure is completely set up. In those
situations don't allow messages to be added until the console
is completely initialized.

BUG=b:73898539

Change-Id: Idc3840132d7f95f8e22045d7484c528d828bb0de
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/24917
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02 15:22:24 +00:00
Bora Guvendik 277f4b9974 mb/google/zoombini/variants/meowth: Enable NVMe
Turn on pcie ports 9,10. Enable Root Port 9 and set up clkreq 3.

BUG=b:72120814
TEST: Boot to OS via NVMe

Change-Id: I272b63b11e6b00ae5bdbef5a37ee517cc0636f6d
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/23208
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02 15:21:54 +00:00
Iru Cai d2517af6f9 mb/hp: Enable additional ports at WWAN slot for Elitebooks
2760p: enable PCIe
8470p: enable mSATA
8460p: enable PCIe, also add comments according to circuit diagram
2570p: comment for some USB ports

Change-Id: Ib5209f2dfb249fca5bae89bc6da3b704c8e903dd
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/23357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-02 15:20:10 +00:00
Martin Roth 45cc2ba882 ec/google/chromeec: Add note before error message
When clearing events from the EC, an error is returned when we try
to clear an event that doesn't exist.  This is normal, but can
be distracting when trying to track down an error, so add a message
saying that the error is expected.

BUG=None
Test=Build Grunt with SMM debug enabled. See message before
"EC returned error result code 1".

Change-Id: Ib2e684e357e821c795de4b59658432c91a8d63fc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/24914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-02 15:19:16 +00:00
Nick Vaccaro 4100f2b97c mainboard/google/zoombini/variant/meowth: enable speed shift
BUG=b:73817825,b:69011806
BRANCH=master
TEST=Build and flash to meowth, verify cpufreq shows up in kernel
for all cores :

	localhost ~ # find / -name "cpufreq"
	/sys/devices/system/cpu/cpu3/cpufreq
	/sys/devices/system/cpu/cpu1/cpufreq
	/sys/devices/system/cpu/cpufreq
	/sys/devices/system/cpu/cpu2/cpufreq
	/sys/devices/system/cpu/cpu0/cpufreq
	/sys/module/cpufreq
	/usr/share/laptop-mode-tools/modules/cpufreq

Change-Id: I63242b2b049e37167c0d3b8eab630cb6e15a75fd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/24902
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02 15:18:52 +00:00
Katherine Hsieh aef0d6b0a7 mb/google/reef/sand: Override USB2 phy settings
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need
to be overridden.

port#1:
PERPORTPETXISET = 4
PERPORTTXISET = 4
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0

port#4:
PERPORTPETXISET = 7
PERPORTTXISET = 7
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0

BUG=b:72623892
BRANCH=master
TEST=emerge-sand coreboot chromeos-bootimage

Change-Id: I4051aefbec4583bb1f8babec08fdbeb27f749769
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/23879
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01 16:22:21 +00:00
Matt DeVillier 0f49bbceef soc/intel/broadwell: Generate ACPI DMAR table
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the
GFXVTBAR is only generated if the IGD is enabled.

Change-Id: Id7c899954f1bae9d2b48532ca5ee271944f0c5f6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-03-01 16:10:25 +00:00
Matt DeVillier 81a6f109ba soc/intel/broadwell: Enable VT-d and X2APIC
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers and reserved from the OS.

Change-Id: I7afcce0da028a160174db2cf6b4b6735bcd59165
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-03-01 16:10:15 +00:00
Lijian Zhao e85e0f57ac mainboard/google/meowth: Turn on DBC over USB3.0
Intel DCI (direct connect interface) allows debug Intel target using
USB3.0 ports. It will support debug via USB stack (DCI Dbc) using USB3.0
only.

BUG=None
TEST=Turn on DCI trace hub in descriptor.bin and flash the coreboot
image. Using DAL to halt/run CPU.

Change-Id: I39e68dabfcb9e659733019334299e562eee3681d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-03-01 16:09:53 +00:00
Seunghwan Kim 3dd88f175d mb/google/poppy/variant/nautilus: Change SlowSlewRateForSa setting
If switch to VT2 on nautilus, screen flicker appears. We found if we
rollback the change of slew rate setting, then the flicker issue will
be gone: https://review.coreboot.org/c/coreboot/+/22588
But nautilus board needs slew rate tuning to reduce EE noise, so we
decided to change only SlowSlewRateForSa to 2 (Fast/8) instead of
rollback the whole change of the CL:22588. It can remove the flicker on
VT2.

BUG=b:71397040
BRANCH=master
TEST=emerge-nautilus coreboot

Change-Id: Id1d4bd8b1316c02c783de708ec4658e030193a26
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/23877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-01 16:09:26 +00:00
Tim Chen 70ba1b7e78 mb/google/reef: Override USB2 phy settings
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need
to be overridden.

port#1:
PERPORTPETXISET = 4
PERPORTTXISET = 4
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0

port#4:
PERPORTPETXISET = 7
PERPORTTXISET = 7
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0

BUG=b:72623892
BRANCH=master
TEST=emerge-reef coreboot chromeos-bootimage

Change-Id: Iab782ac6dfd81af839fff0e60e2b2460ce722733
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/23878
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01 16:07:59 +00:00
Sheng-Liang Pan 06e3e1f055 mb/google/coral: add usb2 phy setting override for some variants
Due to there are some chances USB devices can not be detected.
USB2 port#1 and #4 PHY register need to be overridden for variants
Santa/Lava/Blue/Bruce/Astronaut.

port#1:
PERPORTPETXISET = 4
PERPORTTXISET = 4
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0

port#4:
PERPORTPETXISET = 7
PERPORTTXISET = 7
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0

BUG=b:72623892
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage

Change-Id: I401905685cc3078df657919b162272c3de320296
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/23881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-01 16:07:35 +00:00
Justin TerAvest 23cff8bf50 mb/{amd/gardenia,google/kahlee}: Initialize GPIOs earlier
The GPIOs for PCIe reset and power enable for WLAN must be set up before
amdinitearly for wlan to function.

BUG=b:73898539
TEST=Boot, see WLAN controller in lspci

Change-Id: I568a3240a54817ab6dcf15fe39f7f1336943852b
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/24916
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01 16:07:10 +00:00
Justin TerAvest bb75effd87 soc/amd/stoneyridge: Remove printk for GPIO
The printk() calls in sb_program_gpios() aren't necessary, and incur a
13 second delay if the function is called from
bootblock_mainboard_early_init(). This commit removes them so GPIOs can
be set up earlier.

TEST=call sb_program_gpios from bootblock_mainboard_early_init
BUG=b:73898539

Change-Id: I064291decf47d86132e36469e029b3262ec20172
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/24915
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01 16:05:18 +00:00
Julien Viard de Galbert a8c9efe655 mb/scaleway/tagada: set SMBIOS Enclosure Type in Kconfig
Change-Id: I7acffcf3fc36742c77ce00b253f5b0a68d435798
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24911
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01 13:47:50 +00:00
Julien Viard de Galbert 9d231a9fd3 smbios: Add option to select the enclosure type
This allows for a mainboard to change the value from its Kconfig.

The default value is still SMBIOS_ENCLOSURE_DESKTOP (0x03) or
SMBIOS_ENCLOSURE_LAPTOP (0x09) if SYSTEM_TYPE_LAPTOP is set.

Change-Id: I35bc913af69565531831746040a0afe0cabe1c58
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-01 13:46:49 +00:00
Subrata Banik a3af8eb76b drivers/intel/fsp2_0: Fix build error while DISPLAY_HOBS is selected
This patch fixes brokenness issues in coreboot with CONFIG_DISPLAY_HOBs
config selection due to recent UDK2017 package changes.

TEST=Build and boot UDK2017 platforms with DISPLAY_HOBS select.

Change-Id: I5c779c86870c62253d64c6af456bf017553e269c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28 17:40:01 +00:00
Nick Vaccaro c8f0a6c31a mainboard/google/zoombini: consolidate SPD makefiles
- consolidate commonality in meowth and zoombini's SPD makefiles into
  a common zoombini/spd/Makefile.inc
- move all SPD hex files into zoombini/spd directory
- move SPD_SOURCES definitions to variants/$(VARIANT_DIR)/Makefile.inc

BUG=b:69011806,b:71776625
BRANCH=master
TEST=Verify 'emerge-meowth coreboot' and 'emerge-zoombini coreboot'
compile and boot successfully.

Change-Id: I2291ebaf0ef5da1b22eb0e8fa7af8dbb50848c29
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23874
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-28 17:38:47 +00:00
Kane Chen c3892c8fa8 skylake: Fix unwanted disablement of ACPI UPWE
In PORTSC, Port Enabled/Disabled(PED) is RW1CS.

When there is a USB device attached on system, current UPWE method
will set 1 to PED, this will cause port disabled as it's RW1CS.

This change is inspired by xhci_port_state_to_neutral in linux driver.
It will mask all RO and RWS bits and set WDE and WCE.

BUG=b:70777816
TEST=System won't be awakend from s3 automatically when usb devices
     is attached. Also system can be awakend by hotplugging usb
     devices under S3.

Change-Id: Ifd4c2d6640fea538e0ac71d7c5e73ab529e94f42
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28 17:37:57 +00:00
Crystal Lin e099b30964 mb/google/poppy/variants/nami: Enable elan touchscreen
BUG=b:72062694
BRANCH=master
TEST=Verify touchscreen on nami works with this change.

Change-Id: Iaec71a11121b3d2849f12d18cda0e506be2ace09
Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/23872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28 17:36:56 +00:00
Ravi Sarawadi 3c2310d2df mb/google/octopus: Add LPDDR4 memory init
Add LPDDR4 initialization support.

BUG=b:73136980
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: Ieffcfa2f9d075eb0be13562f1a0c7ee503b005d9
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/23832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-28 17:36:37 +00:00
Furquan Shaikh 51700313f5 soc/intel/skylake: Add support to print ME version
This change adds a boot state callback to print ME version after
DEV_ENABLE is complete. Information is printed only if UART_DEBUG is
enabled because talking to ME to get the firmware version adds ~1
second to boot time.

TEST=Verified on Soraka that ME version printed is correct.

Change-Id: I360d5d7420950d5aa255df08be6d7123621b87a8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/23857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-28 02:19:02 +00:00
Arthur Heymans d2d2aef6a3 sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location
Many generations of Intel hardware have identical code concerning the
RCBA.

Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-27 09:46:29 +00:00
Marc Jones 5fd1d5ad12 soc/amd/stoneyridge: Refactor northbridge resource allocator
The resource allocator was overly complicated due to porting
from a multi-node resource allocator. It had some assumptions
about the UMA memory and where it would be located. The
refactored allocations account for UMA being reserved above 4GiB.

TEST=Check CBMEM table has correct RAM regions.

Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26 18:18:21 +00:00
Marc Jones 932b5bdb6d soc/amd/common: Save the UMA settings from AGESA
Save the UMA base and size settings returned by AGESA
in amdinitpost();

Change-Id: Id96cc65582118ad41d397b1a600cab1615676a55
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26 18:18:07 +00:00
Nick Vaccaro ab2618d488 mainboard/google/zoombini: enable 4 cores
BUG=b:70731385
BRANCH=master
TEST='emerge-meowth coreboot chromeos-bootimage', flash
image.serial.bin to meowth board, boot into kernel, and
verify 4 cores are running.

Change-Id: Ia233e41acd19b317f82433a5d41d84ea934a66c4
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23839
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-26 15:07:56 +00:00
Richard Spiegel bd65480593 src/arch/x86/smbios.c: Fix type 17 part number
Some DIMMs have invalid strings when it comes to device part number
(bytes 0x149-0x15c). From DDR4 SPD specs it should be ASCIIZ with unused
space filled with white spaces (ASCII 0x20). Byte 20 should be 0 (ASCIIZ),
all others should be ASCII.

Create a test that detects invalid strings and replace invalid
characters with *. If a replacement was made the output string then must
be <Invalid (replaced string)>.

BUG=b:73122207
TEST=Build, boot and record serial output for kahlee while injecting
different strings to dmi17->PartNumber. Use code to examine SMBIOS,
while testing different valid and invalid strings.
Remove string injection before committing.

Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26 15:06:58 +00:00
Richard Spiegel 99fd08d324 soc/amd/common/block/pi/amd_late_init.c: Fix part number
Kahlee DIMM have invalid string when it comes to part number
(bytes 0x149-0x15c). We currently force a NA string, but grunt has the
proper strings. Just let the string go through, and a second commit
within smbios.c will be responsible for testing the string and taking
proper action.

BUG=b:73122207
TEST=Build, boot and record serial output for kahlee while injecting
different strings to dmi17->PartNumber. Remove string injection before
committing.

Change-Id: I427262873f9ec80f459245e5f509e28a68de3074
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26 15:06:36 +00:00
Vanessa Eusebio 3ca534f302 MAINTAINERS: Update INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB Maintainers
* Add David, Jeff, and Shine
* Remove Fei

Change-Id: I2803af80ac8c2b1d04ecd125c0cb123e736cdf7e
Signed-off-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
Reviewed-on: https://review.coreboot.org/23847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafranski
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-02-26 15:06:10 +00:00
Furquan Shaikh 8389fe6da3 ec/google/chromeec: Remove extra newline characters from printk
This change removes extra newline characters from print statements for
wake masks.

Change-Id: I13cde76bfb0f10b1dda8117c27f2891e909f9669
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/23858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-26 15:05:08 +00:00
Werner Zeh 5ea714acce mb/siemens/mc_bdx1: Avoid dereferencing a NULL pointer
Coverity scan has found an error where a NULL pointer is dereferenced.
The bug would happen if the devicetree does not contain a valid entry
for PCA9538. In this case the code
 * if (dev->path.i2c.device == PCA9538_SLAVE_ADR)
would dereference to a NULL pointer.

This patch fixes this issue. Thanks coverity!

Found-by: Coverity (CID 1386126: Null pointer dereferences (REVERSE_INULL))
Change-Id: I75e271d86c16fa3938420c43575ebba910f6a2fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26 05:35:58 +00:00
Zhongze Hu 12f656ced7 mb/google/fizz: Enable PCIe port 11, 12
Our CFM daughter card would like to use individual PCIe lanes for two
different devices on the card.

dlaurie@ has reconfigured PCIe port 9-12 from 1x4 to 1x2 + 2x1 on b2b
connector on fizz to meet the requirement:
https://chrome-internal-review.googlesource.com/571936
We also need to enable the ports on device tree.

BUG=b:72523836
TEST=none
BRANCH=fizz

Change-Id: Icded9850d833752680e0174b6c476e657817b319
Reviewed-on: https://chromium-review.googlesource.com/923867
Commit-Ready: Zhongze Hu <frankhu@google.com>
Tested-by: Zhongze Hu <frankhu@google.com>
Reviewed-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924860
Commit-Queue: Shelley Chen <shchen@chromium.org>
Tested-by: Shelley Chen <shchen@chromium.org>
Signed-off-by: Zhongze Hu <frankhu@chromium.org>
Reviewed-on: https://review.coreboot.org/23845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2018-02-23 22:04:41 +00:00
Julien Viard de Galbert 4ecd42f9b5 console: Introduce a way for mainboard to override the loglevel
This change adds a config option to allow mainboard to override
the console loglevel. When the option is set, the platform has
to define the function get_console_loglevel returning a valid
loglevel value.

This allows a mainboard to sample a GPIO to switch the loglevel
value between different environments (qualification vs production)
without re-flashing.

Change-Id: Id6cc72b8fe5c4c50a6f83ce80e6440b078eec6e2
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-23 08:44:59 +00:00
Richard Spiegel 8f825e0cd0 mb/google/kahlee/mainboard.c: Fix mainboard_picr_data
While programming interrupts, a message "perhaps this device was defined
wrong?" shows up twice. This is caused because some devices have
interrupt programmed for APIC mode, but not for non-APIC mode. Fix
mainboard_picr_data table by identifying devices programmed with value
0x1F while programmed differently on mainboard_intr_data table. Do so
only for devices that are used by kahlee or interrupt required by old OS.

BUG=b:70788755
TEST=Build and run kahlee, Verify that message disappears from serial
output.

Change-Id: Ic285036290519ed3ee617dffa616bd26c61575c5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-22 20:27:09 +00:00
Justin TerAvest f6106718a8 mb/google/kahlee: Use GPIO macros for baseboard
This commit uses newly defined macros to make it easier to read which
iomux function pads are being configured to use.

TEST=Booted grunt, confirmed display backlight came on.
BUG=b:72875858

Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22 17:16:51 +00:00