Most LAPIC registers are 32bit, and thus the use of long is valid on
x86_32, however it doesn't work on x86_64.
* Don't use long as it is 64bit on x86_64, which breaks interrupts
in QEMU and thus SeaBIOS wouldn't time out the boot menu
* Get rid of unused defines
* Get rid of unused atomic xchg code
Tested on QEMU Q35 with x86_64 enabled: Interrupts work again.
Tested on QEMU Q35 with x86_32 enabled: Interrupts are still working.
Tested on Lenovo T410 with x86_64 enabled.
Change-Id: Iaed1ad956d090625c7bb5cd9cf55cbae16dd82bd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36777
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We are currently relying on the assumption that the amdcompress tool
will zero out the bss section. Instead of relying on this assumption,
lets explicitly clear it.
The implementation was copied from assembly_entry.S.
BUG=b:147042464
TEST=Cold boot trembyle and also s3 resume trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifb4f4cc6932dd4c3c92d4e7647569f9a0c69ea4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change is required so we have a defined entry point on S3. Without
this, the S3_RESUME_EIP_MSR register could in theory be written to
later which would be a security risk.
BUG=b:147042464
TEST=Resume trembyle and see bootblock start.
coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 smm starting (log level: 8)...
SMI# #6
SMI#: SLP = 0x0c01
Chrome EC: Set SMI mask to 0x0000000000000000
Chrome EC: Set SCI mask to 0x0000000000000000
Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected.
EC returned error result code 9
SMI#: Entering S3 (Suspend-To-RAM)
PSP: Prepare to enter sleep state 3... OK
SMU: Put system into S3/S4/S5
Timestamp - start of bootblock: 18446744070740509170
coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 bootblock starting (log level: 8)...
Family_Model: 00810f81
PMxC0 STATUS: 0x200800 SleepReset BIT11
I2C bus 3 version 0x3132322a
DW I2C bus 3 at 0xfedc5000 (400 KHz)
Timestamp - end of bootblock: 18446744070804450274
VBOOT: Loading verstage.
FMAP: area COREBOOT found @ c75000 (3715072 bytes)
CBFS: Locating 'fallback/verstage'
CBFS: Found @ offset 61b80 size cee4
PROG_RUN: Setting MTRR to cache stage. base: 0x04000000, size: 0x00010000
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4b0b0d0d576fc42b1628a4547a5c9a10bcbe9d37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add DW9768 VCM device and add its entry in the OV8856's _DSD
to allow the V4L2 driver to use the VCM functionality.
Also add ACPI entries for AT24 NVM device, this will enumerated
as a generic NVM device and not part of the V4L2 framework.
BUG=b:155285666
BRANCH=None
TEST=Build and able to see DW9768 and AT24 getting listed I2C3 lanes
and able to capture image using world facing camera.
Change-Id: I19e4a4107c5bc9d96f718d654df50e2705b98c03
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Old (!PARALLEL_MP) cpu bringup uses this as the first
control to do SMM relocation.
Change-Id: I4241120b00fac77f0491d37f05ba17763db1254e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Broadwell does not have any `TESGMB`, but it has a `TSEGMB`.
Change-Id: Id25030aa86f2312e261eceb8b78c3878e9e0ee04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The PCI COMMAND register is 16 bits wide. So, do not use 32-bit PCI ops
to update it.
Change-Id: I8f8d9e978f3b241cb544dd1d26e0f5fa8997d11e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Fix Puff and its variants to not shutdown the AP before the cr50 reboot.
This is the same approach that Sarien do to remain on during a cr50
cycle.
BUG=b:154071064
BRANCH=none
TEST=none
Change-Id: I5f92b4f769654b67c10c91e4cc7b2bce785e302f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42497
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Here we consolidate some of the dptf.asl duplication between
Puff and it's variants. Customizations can be done later
either as a direct copy or preferably via introducing a #define.
BUG=b:154071868
BRANCH=none
TEST=none
Change-Id: I35fa1e152adb5f04fb6ef1bd2448376cf9f37980
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Here we consolidate some of the ec.h duplication between
Puff and it's variants.
BUG=b:154071868
BRANCH=none
TEST=none
Change-Id: I13dfe09da5c7a19677b156063bb51a58bc059b93
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
The former is not standard C, and we primarily use the latter form.
Change-Id: Ia7091b494ff72588fb6910710fd72165693c1ac5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Commit 86ba0d73f3 added VBIOS support for
Raven2 silicon and changed the VBIOS file names to the format including
the PCI device revision number. Upstream SeaBIOS expects the file to
have only the PCI vendor and device IDs in the CBFS file name, so it
doesn't find the VBIOS any more after that patch got applied. This patch
adds the path and CBFS file name to include the Picasso VBIOS a second
time under the CBFS file name SeaBIOS expects.
This is a workaround and not a clean solution, but avoids breakage.
It's separated from the rest of the Mandolin support, so it can just be
reverted after a proper fix is implemented.
https://chromium-review.googlesource.com/2015963/ in combination with a
links file in CBFS might solve the issue for most of the cases, but it's
not sure yet if for all, so a proper fix might require more than that.
BUG=b:153675508
Change-Id: I4d9042615965b6a2d9255c194cf23368264ffe54
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42433
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mandolin is the CRB for AMD Picasso and Dali.
The mainboard code still needs a little cleanup and verification, but
I'll do that in a follow-up to have a non Chromebook board using the
Picasso SoC code in tree as soon as possible to be able to detect some
possible breakage.
BUG=b:130660285
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33772
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Constify local variables and drop redundant logic, while preserving the
original behavior. While we are at it, also reflow print statements.
Change-Id: Id024f3ac717dad98c4287add9b33defde7a0028d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Commit 0148fcb4 [Combine Broadwell Chromeboxes using variant board scheme]
incorrectly flipped the mic pin configs for verb NIDs 0x18 and 0x19,
so set them back to the correct values, which match the original
Chromium sources (where the NID identifiers in the pin config comments
were reversed, which was the source of the confusion originally.
Test: build/boot guado variant, verify mic attached to 3.5mm jack functional
Change-Id: I65b813c8f801303682762ce5a7446e07af117b9f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42518
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 0558d0c [mb/google/beltino/**/hda_verb.c: Correct pin configs]
incorrectly flipped the mic pin configs for verb NIDs 0x18 and 0x19,
so set them back to the correct values, which match the original
Chromium sources (where the NID identifiers in the pin config comments
were reversed, which was the source of the confusion originally.
Test: build/boot panther and zako variants, verify mic attached
to 3.5mm jack functional
Change-Id: I172a0bb299049d113a0272ee9c790b25b6242cad
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42499
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
fch_apic_routing is used as name of an array that init_tables()
populates with the APIC IRQ routing information. Also the fch_pirq array
where fch_apic_routing was used as struct name contains the IRQ mapping
for both PIC and APIC mode, so rename it to fch_irq_routing.
Change-Id: Iba7a2416c6e07cde1b8618bdabf31b00e3ca4dd1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The PIC and APIC IRQ routing tables are pre-populated with PIRQ_NC in
init_tables(), so the fch_pirq table entries where both IRQ numbers are
set to fch_pirq are redundant and can be removed.
Change-Id: I0d9b4f25e12a66cf86d1ad541955c3d2fe336c5a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Files are both identical and common for both SoCs.
Change-Id: I54b78108d342a0fd03bf70ffe6a09695c5678eb4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42545
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support for SW CM. Add Operating System Capabilities
(_OSC) method to enable USB/DisplayPort/Inter-domain USB4 Internet
Protocol tunneling and enable PCIe tunneling as well. Remove Connect
Topology(CNTP) command because kernel driver directly works with SW CM
Thunderbolt firmware. Update _DSD method for USB4 support across XHCI
and PCIe root ports.
BUG=b:140645231
TEST=Check Type C device all ports connection/enumeration with SW CM.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I859c5075882e40d7be30d4ba88cc825886712b74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We don't use these on zork, so lets save the power.
BUG=b:153001807
TEST=Boot OS and make sure UART 1, 2 and 3 are not probed and remain
powered off.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2fadeba779b66ec2fb13951b9487118ef0737a94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Rename dptf.asl to dptf_common.asl under soc/intel/common/acpi path
to avoid any kind of confusion with another dptf.asl file under
soc/intel/common/acpi/dptf path. Sometime it's confusing to have
two dptf.asl files just one directory apart.
BUG=None
BRANCH=None
TEST=Build and boot on volteer system
Change-Id: I23d93719e23c0b7659ccb23e5d0868f879bc162c
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add unique new acpi device ids for dptf for Tiger Lake soc based platforms
and update volteer speficic dsdt.asl file accordingly. The Linux kernel
driver expects these new acpi device ids for dptf functionalities.
BUG=None
BRANCH=None
TEST=Build and boot on volteer system
Change-Id: I7dbb812c0fc0f5084c98cf2752ce7ddce8e4d50e
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Move uart_platform_base and uart_platform_refclk to their own
compilation unit to avoid preprocessor usage. The newly created
compilation unit is only added to the build when PICASSO_CONSOLE_UART
is selected.
Change-Id: I56911addc8c000a0772156e5166720867cdd26fe
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42517
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PCIe platform descriptors passed to Picasso FSP should use fixed width fields.
BUG=b:153681134
TEST=Boot system and suspend/resume. All PCIe devices train succesfully.
Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Change-Id: If2a34be895db2c19c8830f5888cb99e43ad21b73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42519
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kconfig 4.17 started using the $(..) syntax for environment variable
expansion while we want to keep expansion to the build system.
Older Kconfig versions (like ours) simply drop the escapes, not
changing the behavior.
While we could let Kconfig expand some of the variables, that only
splits the handling in two places, making debugging harder and
potentially messing with reproducible builds (e.g. when paths end up
in configs), so escape them all.
Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
The APU2 was using the soc/amd/common functions to do GPIO reads and
writes. The functions that were being used are getting eliminated in
the SOC directory, but since the APU isn't using the rest of that code
(as it's not using the rest of the SOC codebase), it proved to be
problematic to use the updated functions.
The solution I've put in place here is to pull everything needed for the
GPIO reads & writes into the gpio_ftns.c & h files.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ied39c114bdf3637977d21f56fd7db428c52e4706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This decouples the linear framebuffer type from the symbols needing it.
Change-Id: I733e630e0aa2fb2947d079caef26253ce443fe91
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42432
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If we are not using the UARTs or they don't have the correct GPIOs
configured we should let the mainboard disable them.
BUG=b:153001807
TEST=Dump SSDT and see UART device is disabled
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifc04e36e0ebe5cce4b6cc228c7174dc76f2ffa4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The option to have amdfw outside of CBFS used dd to write amdfw at a
given location overwriting anything that was there before, which may
cause the build to fail due to the FMAP header being overwritten
resulting in a not too obvious error that the image is a legacy image
without FMAP header.
Mandolin was the only board using this functionality, but I fixed the
placement of components in the flash image there, so that amdfw can just
be placed in CBFS avoiding those problems.
Change-Id: I0f3abab9d3939da43e1681d5cfe2c8d494402acf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42438
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With RELOCATABLE_RAMSTAGE the backing up of low memory
on S3 resume path was dropped. We forgot some things
behind.
Change-Id: I674f23dade0095e64619af0ae81e23368b1ee471
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
For baytrail and braswell, explicitly initialise
it to ACTIVE_ECFW_RO without ChromeEC.
For broadwell and skylake, fix it to report actual
google_ec_running_ro() status.
Change-Id: I30236c41c9261fd9f8565e1c5fdbfe6f46114e28
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42389
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Elyes HAOUAS