This change replaces the device tree walks with device pointers by
adding alias for dptf_policy generic device in the tree.
Change-Id: I8fd5476a9cea84ab8b2678167b3e0504eecacf6c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
USB3 MB doesn't have re-timer. Thus we have to configurate the AUX pin.
For now, we use USB3 DB to determine the USB3 MB.
BUG=b:197907500
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ide45c77e0a6f736a02d5dc9ad05aa1ef9e754fa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update thermal setting from thermal team.
BUG=b:200134784
TEST=build and verified by thermal team.
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: If74c3bc19cf4abd64d646b842cbb6a61b910e933
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
NVMe needs extra time to run boot process, enable power and deassert
reset for NVMe earlier in the boot flow that primus can successfully
boot into OS with non-serial coreboot.
BUG=b:199967106
TEST=USE="project_primus" emerge-brya coreboot and verify it builds
without error.
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I9c66efe96515347502d059556052c764c1be5d09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Follow FIBOCOM_L850-GL Hardware User Manual_V1.0.8.
BUG=b:180166408,b:187691798
TEST=measure WWAN power off by scope is meeting the spec.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I6b2725cd61d5b54bc7fd70a9daffd29e7b43690b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
vboot_reference is introducing a new field (ctx) to store the current
boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged
in both vboot flow and elog_add_boot_reason in coreboot.
In current steps of deciding bootmode, a function vb2ex_ec_trusted
is required. This function checks gpio EC_IN_RW pin and will return
'trusted' only if EC is not in RW. Therefore, we need to implement
similar utilities in coreboot.
We will deprecate vb2ex_ec_trusted and use the flag,
VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag
in coreboot, verstage_main.
Also add a help function get_ec_is_trusted which needed to be
implemented per mainboard.
BUG=b:177196147, b:181931817
BRANCH=none
TEST=Test on trogdor if manual recovery works
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO field of fw_config.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:200009010
TEST=ALC5682-VD/ALC5682-VS audio codec can work
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I09c7830fff6b318cf1a1f4a44ee0a819691f7c58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57673
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MIPI camera support for OVTI2740
BUG=b:196937374 b:194926283
TEST=Build and boot on Kano
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I248c64b9460c898f9faa5f7ac8cf339a9c814013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch has changes to support multiple camera modules, base on the value set in the SSFC_CONFIG.
BUG=b:198235323
TEST=tested the changes with redrix 5MP(ov5675/hi556) camera.
Change-Id: I71c8355617171ec7d08862759b87d4bf12ce2924
Signed-off-by: Arec Kao <arec.kao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57272
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCIe WWAN module used on brya0 requires control over 4 signals to
successfully power it on. It is desirable to do this before passing
control to the payload, because the modem requires a ~10 seconds
initialization phase before it can be used.
The corrected sequence looks like:
1) Drive device into full reset and enable power in bootblock
2) Deassert FCPO in romstage, after power rails stabilize
3) Deassert WLAN_RST#, then WLAN_PERST# in ramstage
BUG=b:187691798
Change-Id: I10f15a4dcfd86216c334fb24b4693ea250d35ee4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This GPIO is used to force the USB retimers on Type-C ports to stay in a
powered state and can be used e.g., during a firmware update to the
retimer to force power on even when no device may be connected to the
port. However, its power rail is controlled elsewhere and coreboot is
not applying a FW update, so this GPIO should be driven low instead.
BUG=b:193402306
TEST=compile
Change-Id: I976a0b8252b31aacef476d5ee4bcf6b1ef2e79de
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
All variants originally had been changed to start with an arrow with
two spaces following it to line up with the platform name. A number
of recent platforms were added only using a single space. This change
updates them all to have two spaces so they line up again.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iab9e6207fff5a7d2f6d76e5ca33eeaca721a224f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch selects SOC_INTEL_COMMON_BLOCK_TCSS from Alder Lake SoC
Kconfig and drops SOC_INTEL_COMMON_BLOCK_TCSS Kconfig selection from
specific mainboard (brya) to ensure all Alder Lake mainboards can make
use of common TCSS block.
BUG=b:187385592
TEST=Type-C pendrive/Gen-2 SSD detected as Super speed.
Change-Id: I85f6a967eb34ea760418131a9586bfdeb13c9b5d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update audio FW config based on the schematic carbine_adl-p_evt_20210901.pdf
BUG=b:199180746
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I4f8ee1a97dd92c7aa0131cd0a77b05f851a26b05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57529
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on latest schematic (0903) update the GPIO table.
BUG=b:197308586
BRANCH=None
TEST=emerge-brya coreboot
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie79ba14859f7fa4ea66a0f0d58287f4515d01baf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Some variants may require more complex power sequencing than can be
accomodated with just 2 GPIO tables, therefore introduce one in romstage
as well.
BUG=b:187691798
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7a63a2ee2cd036b9ae5822be9c87d8a026a54922
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
gimble only uses one WiFi SAR table, contained in a file named wifi_sar_0.hex
BUG=b:189068477
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ied030b79183cc6f962674260e7a82a7261b317ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57616
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the schematic diagram of version C14_MB_20210902A_SB,
modify the settings of GPIO and fw_config.
BUG=b:197700276
BRANCH=none
TEST=emerge-brya coreboot
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I14907faeb631193715b1e0e451e427fb79a68279
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update fw_config.c based on the schematic carbine_adl-p_evt_20210901.pdf
BUG=b:190688567
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I240c0cd777d215e46a0a661aaac63a187311019d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
NVMe needs extra time to run boot process, enable power and deassert reset for NVMe earlier in the boot flow that gimble can successfully boot into OS with non-serial coreboot.
BUG=b:198405404
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ib76965db2a6cd0c19be4043fec73af297a619c7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57359
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables SaGv support for gimble.
BUG=b:198531517
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I29887418827614afb10558c6958c9c5e9667079e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marx Wang <marx.wang@intel.com>
Roughly half the boards had a "title" comment for the board. This adds
it for the rest of the boards to make everything consistent.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ib941318842136212727f56fc6130381c5c9cd55b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change adds a new Kconfig `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
that can be selected by mainboard to reserve hotplug resources for
USB4 at the SoC level. `ADL_ENABLE_USB4_PCIE_RESOURCES` is dropped
from soc/intel/alderlake and instead the newly added Kconfig is now
used. This new Kconfig is added so that the same config can be used
across different platforms. In following changes, this Kconfig is
utilized by TGL as well.
Change-Id: Id7c359a0e255c43c2732f6cbe287bc7da14a46e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There are two different types of 682 SKU available with TDP
of 28W and 45W. This patch fix override values for power
limits for these 682 SKU. This patch also sets power limit
values dynamically based on machine ID and CPU TDP of SKU.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I796e56321ae9c8312530a4b8986cd73a2245f5fa
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57290
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once.
Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The RW_MRC_CACHE only needs to be 64K for Brya.
BUG=none
TEST="emerge-brya coreboot chromeos-bootimage", flash and boot
brya0 to kernel.
Change-Id: I74365b795e184b92f483ae2bf862791e235c5362
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56989
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO PM was disabled for brya to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. All devices currently tested on brya support 4us
long pulses. This change drops the GPIO PM override and re-enables
dynamic GPIO PM.
TEST=Boot brya to OS, ensure no TPM errors.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0c7b66b5514d8b80775ab7578ce7b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56926
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable this feature, and it can use the probe statement in devicetree
to cache of fw_config field as oem string.
BUG=b:191931762
TEST=With CBI FW_CONFIG field set to 0x8,
set probe AUDIO MAX98390_ALC5682I_I2S_4SPK in devicetree
dmidecode -t 11
OEM Strings
AUDIO-MAX98390_ALC5682I_I2S_4SPK
Change-Id: I93cd9ef2d1ad963e66c422cff17b083abf731046
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add SPD support to gimble for LPDDR4 memory part K4UBE3D4AA-MGCR.
BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ida21fd50129412af59a341dea45232fd0f9931ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57253
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on latest schematic to update the gpio table.
BUG=b:197308586
BRANCH=None
TEST=emerge-brya coreboot
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0d91199ffd2128a136ea0a33dfe7affa77ae61d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Based on latest shcematic to update the device tree.
BUG=b:197308586
BRANCH=None
TEST=emerge-brya coreboot
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I59601571c5e4c2d19738cb333605fb22e1ea0d2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.
If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.
Also, add a release note for the upcoming 4.15 release.
Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Add two thermal sensors for fan and wwan for DPTF based thermal control.
BRANCH=None
BUG=b:181271666
TEST=None
Change-Id: Idc9bd6040c9bb316ec7e314f5e9c937c75cfc95a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Create the anahera variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:197850509
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ANAHERA
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Id7649d56a8d6f85d12208f7ddaf2f71a7fe98e8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
