Without this change, the tool only reports the first hit. We want to see
all of them.
Change-Id: Ib59b13c50b61c48e3cb200bf57e28c9453590819
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Add a helper function specific to ramstage to add the boot count
information into event log at ramstage.
BUG=b:117884485
BRANCH=None
TEST=Add an event log from romstage, boot to ChromeOS
Change-Id: Ic79f1a702548d8a2cd5c13175a9b2d718527953f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29542
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Group event log state information together to manage them better during
different stages of coreboot.
BUG=b:117884485
BRANCH=None
TEST=Add an event log from romstage, boot to ChromeOS
Change-Id: I62792c0f5063c89ad11b512f1777c7ab8a2c13e5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the SmbusEnable config option from devicetree and instead
use the state of the PCI device to determine if it should be
enabled or disabled.
Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Remove the SmbusEnable parameter from all Cannon Lake mainboards.
Instead this will be determined by the enable state of the SMBUS
PCI device.
Change-Id: I7ece6768da4c517747af12a07012583575816ae1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some embedded controllers expect to be sent a command when the OS
calls the ACPI \_PTS and \_WAK methods. For example see the code
in ec/google/wilco/acpi/platform.asl that tells the EC when the
methods have been executed by the OS.
Not all ECs may define these methods so this change requires also
setting a Kconfig option to enable it.
Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
ME Cleaner's component has an entry specifying its website, which this
parser didn't know how to handle. Avoid the resulting warning.
While at it, de-C the switch statement and make it work go-style. This
also fixes "R" statements being ignored.
Change-Id: Ifc23e28daba9d85bf690557a80134accea8bed21
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This change updates the configuration of EC_SYNC IRQ to be level
triggered to match the EC behavior.
Change-Id: I8e3cb2ae8016ea183d9067697aa5d4b9caa2d07e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* Clear remalloced memory
* Fix check for invalid VBT offset in header
* Fix VBIOS checksum generation
* Fix VBIOS size field
* Align VBIOS size to multiple of 512
* Reassign pointers after use of remalloc
* Don't leak on error path
Current version is enough to allow the proprietary Windows Intel GMA
driver to find the VBT in the legacy VBIOS area and it doesn't BSOD
any more.
The LVDS screen remains black, due to an unknown issue with the
proprietary driver, while the VGA works.
Tested with libgfxinit and native graphics init.
Change-Id: If07b1bb51d8fb3499d13102f70fedb36c020fb72
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Useful for testing stuff in C_ENVIRONMENT_BOOTBLOCK, like
VBOOT with separate verstage.
Changes:
* Use symbols to set up CAR and STACK
* Zero CAR area
* Move BIST failure checking to cpu folder
* Rename functions where necessary
Tested:
* qemu-2.11.2 machine pc
* qemu-2.11.2 machine q35
Test result:
* BIST error reporting is still working.
* Console starts in bootblock
* SeaBios 1.11.2 as payload is still working
Change-Id: Ibf341002c36d868b9b44c8b37381fa78ae5c4381
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On some boards the devicetree and Function Disable register did not
match. In this case the FD values are put in the devicetree as these
were the values that were actually used in practice.
A complete devicetree will make it easier to automatically disable
devices in ramstage.
Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Instead of having the code for the RAM init time stamps in each
mainboard’s `romstage.c`, factor it out to the northbridge code, done in
commit 771328f7 (intel/i945: add timestamps in romstage).
Change-Id: Ibb699a1fea2f0b1f3c6564d401542d2fb3249f5a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17994
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard also has a SD slot.
Change-Id: Id56bc1be60ec8c2be0e5543d1d8851610b7248e0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard also has an external RTC chip, but not on this bus. The
topic is currently in clarification and will be published with a later
patch. In a first step we enable all I2C busses.
Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Enable all PCIe root ports for this mainboard.
Change-Id: I7f6feb2f0d4c45f32d9454838e67e1a244b2712b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
There is no device on I2C0 which requires a lower clock rate.
Change-Id: Ib7c4e3251545b2d32368dd56206e3b4844a24800
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
All PCIe root ports of this mainboard do not have an associated CLKREQ
signal. Therefore the ports are marked with "CLKREQ_DISABLED".
Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On this mainboard there are legacy PCI device, which are connected to
different PCIe root ports via PCIe-2-PCI bridges. This patch disables
the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.
Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard provides customer hardware reset button. A feature of
this button is that it holds the APL in reset state as long as the reset
button is pressed. After releasing the reset button the APL should
restart again without the need for a power cycle. When Bit 3 in Reset
Control Register (I/O port CF9h) is set to 1 and then the reset button
is pressed the PCH will drive SLP_S3 active (low).
Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
There is an on-board PCI device where bus master has to be enabled in
PCI configuration space. As there is no need for a complete PCI driver
for this device just set the bus master bit in mainboard_final().
Change-Id: I1ef4a7774d4ca75c230063debbc63d03486fed6f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
For this mainboard the correction of transmit voltage swing from SATA
interface is not necessary.
Change-Id: I900d0d44b88585c223182d85c78cf3ff1e3e9159
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On this mainboard there is a legacy PCI device, which is connected to
the PCIe root port via a PCIe-2-PCI bridge. This device only supports
legacy interrupt routing. For this reason we have to adjust the PIR6
register (0x314c) which is responsible for PCIe device 13h and 14h. This
means that the interrupt routing will also be the same for both PCIe
devices. The bridge is connected to PCIe root port 2 and 3 over two
lanes (Device 13.0 and 13.1).
The following routing is required:
INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#->PIRQC#
Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29513
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change tcc offset from 0 to 10 for fleex.
Refer to b:117789732#1
BUG=b:117789732
TEST=Match the result from TAT UI
Change-Id: I481526ab10a16a33fe0cf9528b52b8524e012451
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
EC_SYNC_IRQ from EC to host is level-triggered in practice and
configuring it as edge-triggered on the host results in host missing
events if there are multiple events queued on the EC side. This is
because Linux kernel driver reads one event per irq and the EC does
not de-assert the interrupt line until all events are drained
out. This results in event queue being filled up completely on the EC
and the host failing to see any of those events.
This change configures EC_SYNC_IRQ as level triggered to allow the
host to read events from the the EC as long as the line is asserted.
BUG=b:118949877
Change-Id: Id3fcfa0445f83865d57975a7bbc179dca047ba4c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Link memory.c instead of including it.
Change-Id: I2bc461b13332ec5885c33c87828a5fd023f8e730
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Remove dead code
* Add support for types 2504 and 2505
* Print dock info at romstage entry
* Improve dock disconnect for type 2505
* Move defines into dock.h for future ACPI code
* Reduce timeouts according to spec to decrease boot time on error
* Fix no docking detection (reduces boot time by 1 second)
* Configure GPIO LDN before reading GPIOs
* Use Kconfig values instead of fixed defines
* Add documentation
Tested on Lenovo T500 with docking 2504 and 2505.
Change-Id: Ic4510ffadc67da95961cecd51a6d8ed856b3ac99
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change disables HECI1 device at the end of boot sequence. It uses
the P2SB messaging to disable HECI1 device before hiding P2SB and
dropping privilege level.
BUG=b:119074978
BRANCH=None
TEST=Verified that HECI1 device is not visible in lspci on octopus.
Change-Id: Id6abfd0c71a466d0cf8f19ae9b91f1d3446e3d09
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change 76ab2b7 ("arch/x86: allow global .bss objects without
CAR_GLOBAL") allowed use of global .bss objects and hence moved around
the macros resulting in car_active returning 0 even for those boards
where CAR is actually active but do not require global migration. This
resulted in boards getting stuck when doing a reset in verstage because
the code flow incorrectly assumed that there was no CAR active and
hence triggered a cache invalidate.
This change fixes the above issue by returning 1 for car_active if
ENV_CACHE_AS_RAM is set even if global migration is not required.
BUG=b:109717603
TEST=Verified that board reset does not trigger cache invalidate in
verstage and does not result in board hang.
Change-Id: I182f3e4277c57d6c50f7fcac2be72514896b3c61
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com>
Reviewed-by: Nick Chen <nickchen@ami.corp-partner.google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Now postcar is a standalone stage, add
it as target to all TPM bus drivers.
This is a required for a measured boot.
Change-Id: I758185daf3941a29883c2256b900360e112275e1
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29546
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now postcar is a standalone stage give it a
proper type.
Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
It is able to do so if timestamps are initialized.
Change-Id: Ic95313a19646b66dc1633fb680e54bfc61ec90be
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/27330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
1. Add two parameters for panel initialization timing.
> lvds_poseq_varybl_to_blon
> lvds_poseq_blon_to_varybl
2. The BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/
EDP_BKLTEN_L, so move APU_EDP_BKLTEN_L to early init stage,
and be enabled depends on SKU, thus we can control the delay
time by config APU_DP_VARY_BL.
BUG=b:118011567
TEST=emerge-grunt coreboot.
Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
GPIOs that use GPI_APIC setting with DEEP can cause an IRQ storm after
S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic
reset over PLTRST to prevent IRQ strom after S3 resume.
For sarien/arcada these are all runtime IRQs only, not wake capable.
Change-Id: Iec3706a3b47b54abbacd06081910f389979c330f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Select the option to disable eSPI when ACPI is enabled so the EC
is unable to assert an SMI when booted into the OS. There is a
kernel driver that implements the same mailbox interface so it
cannot also be used by the SMI handler.
Change-Id: I8bafc749f22aed5595e19e773762ee8b038950b9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add an option that will disable eSPI SMI when ACPI mode is enabled,
and re-enable eSPI SMI when ACPI mode is disabled. Additionally it
ensures eSPI SMI is disabled on the ACPI OS resume path.
This allows a mainboard to ensure that the Embedded Controller will
not be able to assert SMI at runtime when booted into an ACPI aware
operating system.
This was tested on a Sarien board with the Wilco EC to ensure that
the eSPI SMI enable bit is clear when booted into the OS, and remains
clear after resume.
Change-Id: Ic305c3498dfa4b8166cfdb070fc404dd4618ba3c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: Ibde5f613c61c36f5c9b405326fd18a3fd16cca56
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/28840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: Icb281f1b23c637971497eb28ed428235adf42f2d
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/28839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: If462126df31468ef55ec52e2061b9f98d3015f61
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/28838
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make the firmware slot configuration in VBOOT selectable. The following
three modes are available:
-RO only
-RO + RW_A
-RO + RW_A + RW_B
The mode "RO only" is the lowest mode with no safety during update.
You can select either RW_A or RW_AB via Kconfig which will add the
selected parttions to the final image.
Change-Id: I278fc060522b13048b00090b8e5261c14496f56e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/27714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This patch also add new SKL PCH-H device id's in soc platform reporting and
common lpc driver.
BUG=None
TEST=Booted kabylake RVP11 with HM175 SKL PCH-H and verified the device id
in serial logs.
Change-Id: I8c04bf8d9c27caad800427a5c29da869da1d445d
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Patrick Georgi