CAR_MIGRATION was removed in commit:
cbf5bdfe - CBMEM: Always select CAR_MIGRATION
ALT_CBFS_LOAD_PAYLOAD was removed in commit:
cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD
MARK_GRAPHICS_MEM_WRCOMB was removed in commit:
30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB.
EXTERNAL_MRC_BLOB was removed in commit:
0aede118 - Drop unused EXTERNAL_MRC_BLOB
CACHE_ROM is only in Google's codebase.
LID_SWITCH is only in Google's codebase.
DEFAULT_POST_DEVICE_LPC is only in Sage's codebase.
ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used.
HUDSON_NOT_LEGACY_FREE never existed as far as I can tell.
MAINBOARD_DO_EDID never existed as far as I can tell.
Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10616
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The default route does work for all Chromebooks and is replaced
with platform-specific one in follow-up.
Change-Id: Ia1839ed38dacf44a89dc757394d054e17666f193
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10442
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Change-Id: I0796b6e7adad0151c5aa6271d62a2cf4abeedb1e
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10643
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC.
This is the start of creating a common interface for all of them.
This also allows us to reduce the chipset dependencies for CBFS_SIZE.
Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10613
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Bring back the ability to link in the DSDT. This is to help Chrome OS to
switch over to a new upstream quickly (because some of the custom built
mechanisms are a pain with tons of files).
This is supposed to be temporary (famous last words), but I'd rather fix the
lack of CBFS awareness in CrOS bit for good in the time I usually spend on
keeping upstream and CrOS branches close.
Change-Id: I7fa5540bbf5c568c4adca56a09c83b6c7e358ad5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10637
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is only needed on boards that still provide old style PIRQ
tables.
Change-Id: Ie299de2937e5b91b7b3e1d1110e40be23c6d9f52
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10508
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
AMD Kern uses PspSecureOs_prod_CZ.csbin rather than PspSecureOs_prod_CZ.sbin.
PspSecureOs_prod_CZ.csbin is the firmware in CarrizoPI v1.0.0.7.
Change-Id: Idf54ee808dd6965aec9b979be00b7f890a88b06d
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10639
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The CBFS size is really mainboard specific, since it really depends on
size of the chip on the mainboard, so it makes sense to have it in
the mainboard menu along with the ROM-chip size.
- Move the CBFS_SIZE definition up in src/kconfig
- Move the Mainboard Menu markers out of src/mainboard/kconfig into
src/Kconfig so CBFS_SIZE can live in the mainboard menu.
- Add a long list setting default values to do what the chipset
directories were previously defaulting the values to. This will
be trimmed down in a following patch that creates a common set of
IFD routines. (Who knew that kconfig supported line wrapping?)
- Update the help text.
Change-Id: I2b9eb5a6f7d543f57d9f3b9d0aa44a5462e8b718
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10610
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Move IASL up with the other tools.
- Remove OUT= which is no longer used in the
payloads/external/SeaBIOS Makefile.
Change-Id: I211ddcf3496b533151936fa5cbfa7a92986ec28f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10606
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Allow adding and executing a refcode binary.
Change-Id: I00e91a088a5695b42528e246d0ed642d988603e3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/10638
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It's guarded by a non-standard configuration option, so didn't trigger.
Change-Id: Ib7a9a45befcb7857edde37e20de7d65a60970882
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10623
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Mickey:
- Does not have power key
- Does not have an audio codec(all audio goes thru HDMI)
- VCC18_LCD moved to VLDO8 and needs to be turned on (was
connected to VSWOUT2 earlier)
BUG=none
BRANCH=none
TEST=Boot from mickey board, and hdmi work normal
Change-Id: I88cdc41ce8bb96a6b17aeb7f24b1c5619471b24e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6c966edfa29df1049c469442dc3ad8bf8b4197b1
Original-Change-Id: I3d98203185f52ed751a5d3045a0ee8f9b4dfbc71
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/274876
Reviewed-on: http://review.coreboot.org/10630
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
VPD strings are not null terminated, so we can't use strcpy
on them in cros_vpd_gets.
BUG=none
BRANCH=none
TEST=add serial_number followed by cam_calib_data to VPD on smaug;
make sure that smaug boots and serial number matches exactly (no garbage)
Change-Id: Id72885517b3d0b1934ba329c1ef0d89a67bd2bb4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 56bbe6688b11043360a046a250d1ea93db4d9f0e
Original-Change-Id: I811dfc2f0830a91410eb69961a6565080ff78267
Original-Signed-off-by: Stephen Barber <smbarber@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280836
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-on: http://review.coreboot.org/10627
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
this is an brief hdmi driver which config with simple
display parameter, const encoder input & output color
format and 8bit color depth, and only 48KHz audio support.
what's more to prevent TV have not show an right things
before coreboot switch to kernel space, we have to add
an terrible 2s delay to driver (2s come from test many
times), cause we have to wait TV to respond (we got no
flag to check whether it is ready).
BUG=chrome-os-partner:40337
TEST=Booted Veyron Jerry and display normal
BRANCH=None
Change-Id: Icd33467e95de6219e1b614616f0112afc52097b6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e5b699aff75a579116aae63d858c834b2f648e8
Original-Change-Id: Iedc87c011c5b62ce5f16a296dd9c3e0c2eaba59b
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272565
Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10625
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add missing newline to SPD CRC verification error message.
Verified by testing this code on Intel IvyBridge and Gigabyte GA-B75M-D3H.
Change-Id: Id1a0a2329507975c3f66ab884f6e26d99003318e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10636
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Use the correct SPD size for crc calculation. sizeof(*spd) returns 4
while sizeof(spd_raw_data) returns the expected value of 256.
Fixes erroneous printing of "ERROR: SPD CRC failed!!!" in raminit log.
Verified by testing this code on Intel IvyBridge and Gigabyte GA-B75M-D3H.
Change-Id: Iba305c69debd64fa921e08e00ec0a3531c80f56f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10629
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Bettong, Lamar and Olivehill Plus have many same Kconfigs.
Move them to northbridge/amd/pi/Kconfig.
Change-Id: I758d5a09f27eee7a7bd60268a2aaed6f16fd0294
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10421
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a new mainboard based on AMD's Family 15h Model 60h processor.
TEST: Bettong can boot Ubuntu 14.10, Windows 7 and Windows 8.
Change-Id: Id807369ff0f04ba303383c65ddd1bd512f184e6a
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10420
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested on Bettong. Windows 7, Windows 8.1 and Ubuntu 14.04 can boot.
Change-Id: Ifcbfa0eab74875638a40e74ba2a3bb7c4fb02761
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10419
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Merlin Falcon(Carrizo) replaces struct AMD_S3SAVE_PARAMS
with struct AMD_RTB_PARAMS and replaces AMD_S3_PARAMS with
S3_DATA_BLOCK.
Change-Id: If074a8de95d82130d29b2e3cfbd7e35cdb9b929d
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10526
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The symbols used in these expressions were not correct and would never
evaluate as true.
Change-Id: Ia20177f41505473b14bc7b8e4b6fb16de36cc295
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10437
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
At present, no option exists for "Keep VESA framebuffer", which
means that text-mode will be used. Add the appropriate Kconfig
option.
Change-Id: Iaed07eba6d9288c857f7e7a0b0be1107071e49e5
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/10553
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
On i945 legacy brightness control is enabled by a single
bit in BLC_PWM_CTL. It's bit 16 or bit 0 (the other one
reverses polarity). Set the bit to enable brightness
controls.
Change-Id: Id855c4e91fe71fb489739e62fbe99ca22841acd2
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/7048
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: If4c1ab5ae33a64be3e7b14150d410edd291ee4ed
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10591
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I4763ce32bb0b0e301401daaeb89440524fcc682e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10584
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ife94f5324971f4fa03e9139f458b985f6fed9d87
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10577
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The EARLY_CONSOLE Kconfig symbol was removed in
commit 48713a1b - console: Drop EARLY_CONSOLE option
The arm64 and mips directories don't even have early_console.c
to include.
Change-Id: Idc60ffb2bac2b180f4fdd0adf5c411e1f692a846
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10615
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Kconfig sometimes fails to parse the last line of a file if there's
no newline at the end. Add one to be safe.
Change-Id: Ia9973a89b12596e1f2a2741ad2e255e886495331
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10614
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Because Kconfig uses the first valid default that it comes across, the
'source' commands to load sub-Kconfigs should be ordered from the
most specific (mainboards) to less specific (chipsets) to least specific
(architectures). This allows the mainboards to override chipsets and
architecture Kconfig files.
Because the architecture files were getting loaded ahead of the chipset
and cpu Kconfigs, the preferred defaults values for things such as
NUM_IPI_STARTS or RISCV_BOOTBLOCK_CUSTOM could not be set.
Change-Id: Ic327452833f012ec06dabb5b5ef661aba3aff464
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10609
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
The HAVE_UART_MEMORY_MAPPED symbol is no longer present, so these
don't actually select anything.
Change-Id: I6d0eb610e48a4506ac7449ac677ee67981d0ff0d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10608
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ib1c6732d3a338f6d898fadc19e5af59032343451
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10580
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I29eaba74185711df055cf56c23ef2bdae0c7b43e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10578
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I782007fe9754ec3ae0b5dc31e7865f7e46cfbc74
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10576
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This does not optimize memcpy for 64bit, it merely makes it compile.
Change-Id: I69ad6bd0c3d5f617d9222643abf7a2ba7c2a0359
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10575
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Adding new board based on AMD Kabini.
Most of the code is copied from gizmosphere/gizmo2
Board is developed by BAP - Bruhnspace Advanced Projects:
http://www.unibap.com/ (Site is under construction)
Special on this board is:
-Soldered down memory
-SuperIO Fintek F81866D
Known bugs:
-S3 doesnt work
-Serial ports only works for the first boot. Needs power cut.
Tested with:
-SeaBios as Payload
-Linux OS - Lubuntu 14.10 32/64Bit, Kernel 3.19 - 4.1
-Windows 8 64Bit
Change-Id: I7e2b306620dd152a9f01ab6ccf2a0a880a068adb
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: http://review.coreboot.org/10288
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Provide ACPI devices with devicetree-compatible annotations for the
three leds and the button of the APU1, as well as the GPIO driver.
This will cause the Linux kernel to automatically load the following
modules:
leds_gpio (CONFIG_LEDS_GPIO)
gpio_keys_polled (CONFIG_KEYBOARD_GPIO_POLLED)
gpio_sb8xx (CONFIG_GPIO_SB8XX)
See
http://events.linuxfoundation.org/sites/events/files/slides/ACPI_vs_DT.pdf
and https://lwn.net/Articles/612062/ for some more information on how
the PRP0001 HID works.
To make this usable a Linux GPIO driver for the AMD chipset is also
required, which I am currently working on, but have not submitted
upstream yet.
Leds have been named after the convention in
Documentation/leds/leds-class.txt:
LED Device Naming
=================
Is currently of the form:
"devicename:colour:function"
For comparison, on an OpenWRT device:
GPIOs 0-21, ath79:
gpio-1 (tp-link:green:usb ) out hi
gpio-2 (tp-link:green:system) out lo
gpio-3 (reset ) in hi
gpio-5 (tp-link:green:qss ) out lo
gpio-7 (qss ) in hi
gpio-9 (tp-link:green:wlan ) out lo
gpio-18 (rtl8366rb ) in hi
gpio-19 (rtl8366rb ) in hi
On the apu1:
GPIOs 288-511, platform/PRP0001:00, AMD SB8XX/SB9XX/A5X/A8X GPIO driver:
gpio-475 (switch1 ) in hi
gpio-477 (apu1:green:led1 ) out hi
gpio-478 (apu1:green:led2 ) out hi
gpio-479 (apu1:green:led3 ) out hi
Change-Id: I956ee92d9d98ef27a83ccb30d314543bd8634f2c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10540
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Allow calls to cpu_phys_address_size and its support functions during
romstage. This enables the proper display of MTRRs during romstage
without duplicating this code.
BRANCH=none
BUG=None
TEST=Build and run on cyan
Change-Id: I6f6465c150a683ce91f1494ebb5d9ac60b75b795
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6bfd517088b6a2e8a5958a837e6c8c471de19fd0
Original-Change-Id: I429f9beb69298836acdd71d17a7bcb717939dfc2
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/277392
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10561
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Martin Roth