DFD (Design for Debug) is a debugging tool, which scans flip-flops
and dumps to internal RAM on the WDT reset. After system reboots,
those values can be shown for debugging using MTK internal parsing
tools.
BUG=b:202871018
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7b711755022b5d9767019611151fea65e71edc66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60828
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In some cases, partner may assign same clkreq on more than one devices.
This could happen when one device is in baseboard dev tree and another
one is in override dev tree.
This change adds a clkreq overlap check and shows a warning message
TEST=On brya, assigned one clkreq to 2 devices and found the warning
message
Change-Id: I2f701a19118f4702c227b17e43b6551591d9b344
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Define the register offsets and bits in a separate header file instead
of in the middle of the .c file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I814192b2dfeff05877ac857dd89e8cdc7ae5ee25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In espi_wait_channel_ready the return value of espi_get_configuration
didn't get checked before. In the case of the espi_send_command call in
espi_get_configuration returning CB_ERR, espi_get_configuration didn't
write to the local config variable, so if this happens in the first pass
of the do-while loop, the following espi_slave_is_channel_ready call
would use the uninitialized local config variable as parameter. Fix this
by checking the return value of espi_get_configuration.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iff1a0670e17b9d6c6f4daf2ea56badf6c428b8c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add minimal Device entries with just an _ADR for each of the PEG ports
for P and M chipsets (N does not have any PEG ports).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The PMC IPC method used to enable/disable PCIe srcclks uses the
LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC
command expects the RP number to be its "virtual wire index"
instead. This new function returns this virtual wire index
for each of the CPU PCIe RPs.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5e9710f0d210396f9306b948d9dce8b847300147
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The PMC IPC method used to enable/disable PCIe clk sources uses the
LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC
command expects the RP number to be its "virtual wire index"
instead. This new function returns this virtual wire index
for each of the CPU PCIe RPs.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Don't perform GPP lock configuration if
SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS config is not selected.
This patch fixes a compilation issue when APL/GLK boards are
failing while gpio_lock_pads() function is getting called from
IA common gpio block.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I392dc2007dba8169e480f82b58b7f0a1578bb09f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch modifies struct pad_config.pad type from `int` to 'gpio_t'
as pad offset inside GPIO community is unsigned type and also to
maintain parity with `struct gpio_lock_config.pad` type.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I15da8a1aff2d81805ba6584f5cc7e569faf456e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch renames struct gpio_lock_config variable `gpio` to `pad`,
to represent the pad offset within the GPIO community.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6bed99c401435c96c9543f99406a934d7141c575
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch fixes the documentation discrepancy of GPIO reset type
between PCH EDS and GPIO BWG. As per GPIO BWG, there are four GPIO
reset types in Alder Lake as below:
- Power Good - (Value 00)
- Deep - (Value 01)
- Host Reset/PLTRST - (Value 10)
- RSMRST for GPD/Reserved for GPP - (Value 11)
Hence, created two different reset types for `GPP` and `GPD`.
Also, replaced PAD_CFG0_LOGICAL_RESET_x macros with PAD_RESET().
BUG=b:213293047
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4b8742c7a0cc1dc420e3e22e34a16355294ed61b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The current CBFS mcache size (roughly 7KiB) is insufficient for mt8186,
so we need to increase it by 1KiB (and decrease the stack by 1KiB).
Error logs:
CBFS ERROR: mcache overflow, should increase CBFS_MCACHE size!
CBFS: mcache @0x0010e004 built for 63 files, used 0xde4 of 0xdfc bytes
BUG=b:202871018
TEST=no cbfs error logs.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I1e627ede3774665575006f752f89101e3c5bde9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60529
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Building an image for the Purism Mini v2 with `x86_64-linux-gnu-gcc-11`
fails with the format warning below as the size of size_t differs
between 32-bit and 64-bit.
CC ramstage/soc/intel/common/block/acpi/pep.o
src/soc/intel/common/block/acpi/pep.c: In function 'read_pmc_lpm_requirements':
src/soc/intel/common/block/acpi/pep.c:57:50: error: format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
57 | printk(BIOS_ERR, "Failed to retrieve LPM substate registers"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
58 | "from LPM, substate %lu, reg %lu\n", i, j);
| ~
| |
| size_t {aka unsigned int}
src/soc/intel/common/block/acpi/pep.c:58:62: note: format string is defined here
58 | "from LPM, substate %lu, reg %lu\n", i, j);
| ~~^
| |
| long unsigned int
| %u
src/soc/intel/common/block/acpi/pep.c:57:50: error: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
57 | printk(BIOS_ERR, "Failed to retrieve LPM substate registers"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
58 | "from LPM, substate %lu, reg %lu\n", i, j);
| ~
| |
| size_t {aka unsigned int}
src/soc/intel/common/block/acpi/pep.c:58:71: note: format string is defined here
58 | "from LPM, substate %lu, reg %lu\n", i, j);
| ~~^
| |
| long unsigned int
| %u
The variables `i` and `j` are of type size_t, so use the corresponding
length modifier `z`.
Fixes: 2eb100dd ("soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM")
Change-Id: I27bce0a6c62b1c1ebbca732761de2f59b042a5d4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Building an image for the Purism Mini v2 with `x86_64-linux-gnu-gcc-11`
fails with the format warning below as the size of size_t differs
between 32-bit and 64-bit.
CC ramstage/soc/intel/common/block/irq/irq.o
src/soc/intel/common/block/irq/irq.c: In function 'assign_fixed_pirqs':
src/soc/intel/common/block/irq/irq.c:186:90: error: format '%lu' expects argument of type 'long unsigned int', but argument 5 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
186 | printk(BIOS_ERR, "ERROR: Slot %u, pirq %u, no pin for function %lu\n",
| ~~^
| |
| long unsigned int
| %u
187 | constraints->slot, fixed_pirq, i);
| ~
| |
| size_t {aka unsigned int}
CC ramstage/soc/intel/common/block/gspi/gspi.o
CC ramstage/soc/intel/common/block/graphics/graphics.o
CC ramstage/soc/intel/common/block/gpio/gpio.o
CC ramstage/soc/intel/common/block/gpio/gpio_dev.o
The variable `i` is of type size_t, so use the corresponding length
modifier `z`.
Fixes: b59980b54e ("soc/intel/common: Add new IRQ module")
Change-Id: I09f4a8d22a2964471344f5dcf971dfa801555f4a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.
Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Typically, FSP-M aka MRC debug log level defaults to `3`
meaning prints all `Load, Error, Warnings & Info` messages.
Sometimes it's too much information to parse even when users
aren't required to have such detailed information hence,
implement `fsp_map_console_log_level()` that maps coreboot console
log level to FSP-M debug log level and suppress verbose MRC debug
messages unless caller selects `HAVE_DEBUG_RAM_SETUP` config and
then the user can enable `DEBUG_RAM_SETUP`.
TEST=FSP-M debug log suggested default `SerialDebugMrcLevel`
UPD value is `2`. While this patch selects `HAVE_DEBUG_RAM_SETUP`
and user to select `DEBUG_RAM_SETUP` config to override
`SerialDebugMrcLevel` UPD value to '5' aka verbose.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since TGL `spi_protection_mode` bit replaces the previous
`manufacturing mode` without changing the offset and purpose
of this bit.
This patch renames to `manufacturing mode` aka `mfg_mode` to
maintain the parity with other PCHs as part of IA-common code.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6d00f72ce7b3951120778733066c351986ccf343
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Add a devicetree setting to configure the CdClock (Core Display Clock)
frequency through a FSP UPD. Because the value for this UPD's default
setting is non-zero and devicetree settings default to 0 if not set,
adapt the devicetree values so that the value for the UPD's default
setting is used when the devicetree setting is zero.
Also update the comment describing the FSP UPD in the header file
FspsUpd.h to match the correct CdClock definition.
BUG=b:206557434
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
To provide power to PS8640, the eDP bridge IC on krabby, add control
of VRF12 and VCN33 to set voltage from MT6366.
TEST=measure 1.2V from VRF12 and 3.3V from VCN33.
BUG=b:210806060
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I55a9ca16e1e335e9355d0a1b30c278a9969db197
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch makes the debug consent for ADL comment default value
comment proper. Default `Platform Debug Consent` value is
2: Enabled (Al probes and tracehub.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic5eeb4f02d051dc1efba2deaecb51cbc7eac51f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
