Now we only need to clean out the FAM10 stack mess and we're good to go with a
uniform RAMBASE.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
USB port for use as Debug Port (on chipsets which support that).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
few more code comments to src/cpu/x86/*.inc files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
that component rather than the mainboard.
The intel/d810e2cb is the only board using the i82801bx southbridge.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Most of the mainboards with i82801gx SBs seem to use the
HAVE_HARD_RESET, which is already selected in the i82801gx SB config.
Removing it from some of those boards should be a functional no-op.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
All Intel CPU models appear to be identified with the form
INTEL_CPU_MODEL_xxxxx. I haved changed the Atom to fit this normal form.
A side effect is that the CPU doesn't need to be listed on the boards
that support it since the socket identifies the CPUs it supports.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
is selected that uses a chipset which actually has that functionality _and_
we have code to initialize the Debug Port in coreboot (for that chipset).
Also, remove the duplicate list of PCI IDs and just link to the wiki page at:
http://www.coreboot.org/EHCI_Debug_Port
The list is now less useful in the kconfig help as this option will only
appear for those boards where it's actually supported.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Use PCI_COMMAND and PCI_COMMAND_MEMORY from pci_def.h instead of
hardcoding their values.
- SB600/SB700: Drop useless/unused SB600_DEVN_BASE and SB700_DEVN_BASE.
- ICH7: Drop unused EHCI_CONFIG_FLAG and EHCI_PORTSC.
- s/uint32_t/u32/.
- Cosmetics, whitespace, coding style fixes and added code comments.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Interrupt transfer support is missing (ie. no keyboard),
bulk and control transfers work (ie. mass storage).
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Build-tested using abuild.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Some boards still used the old DEBUG_RAM_SETUP (without _CONFIG prefix).
Also, consistently use "#if CONFIG_DEBUG_RAM_SETUP" (not #ifdef) as we do
elsewhere.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Drop unused DBGP_DEFAULT #defines on boards with chipsets where no
USB Debug Port support is implemented anyway (at the moment, at least):
- hp/dl145_g3
- hp/dl165_g6_fam10
- ICH7: Move unrelated code out of set_debug_port(). All ICH southbridges
with Debug Port hardcode the physical USB port used as Debug Port to 1.
In other words, this port is not user-configurable (as seems to be
the case on NVIDIA MCP55). For now we keep the 'port' parameter in order
to not change the API, this might be fixed differently later.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
wonder why variables in .data or .bss (both somewhere in ROM space)
are wrong.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Three CAR implementations on Intel CPUs include <cpu/amd/mtrr.h>, which
is obviously wrong, so drop the #includes. None of their #defines are used
in the Intel code.
Build-tested with two of the affected boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
statement to those files that actually need it. This significantly
reduces the number of dependencies, so it's no longer extremely ugly to
specify them manually (see the src/pc80/Makefile.inc portion)
- Add double include guards around option_table.h defines
- Also, drop the AMD DBM690T work around for the issue
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also fixes random whitespace issues, typos, etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the device tree, instead of using hardcoded values.
If this changes behaviour, this is either
- a bug in mptable_write_buses(), or
- a bug in the old mptable or device config, that is
they were inconsistent.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Without a (currently) dummy set_debug_port() function the build fails,
this may or may not be fixed differently in the future.
Manually build-tested on all SB600/SB700 boards, and tested on hardware on
one SB600 board I own, works fine.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
another recent change into account.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Original patch was
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Updates to accomodate changes in coreboot are
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Add missing license headers, or missing (C) lines to various files.
(most are from AMD / Yinghai Lu, based on svn logs)
- src/include/ehci.h was taken from the Linux kernel. Updating it to
the latest version from git HEAD while I'm at it (build-tested with
one board). It also sports some new EHCI 1.1 addendum #defines which
we may or may not need.
This new file also already has a proper GPL header.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
used for source level debug.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The 'delay' variable shadows the global 'delay()' function, yielding
this compiler warning/error:
src/pc80/../lib/usbdebug.c: In function `ehci_reset_port':
src/pc80/../lib/usbdebug.c:281: error: declaration of `delay' shadows a global declaration
src/lib/delay.c:9: error: shadowed declaration is here
This fixes the issue by renaming the 'delay' variable to 'delay_ms'.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
consits of weak function which always exists (with defaults) and a possibility to
override this with normal function in main.c. This is the other way of
doing that and not using the devictree.cb.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
After we splitted up the old i82801xx driver which was supposed to support
multiple generations of ICH* chipsets, some of the generified code
is now obsolete in i82801ax which should only cover ICH/ICH0 and none of
the later ICH* generations.
Hence:
- Drop "struct pci_driver" entries for chipsets other than ICH/ICH0.
- Drop drivers for hardware that is not present on ICH/ICH0: NIC, SATA, EHCI.
- Drop PIRQE-PIRQH #defines and code, not available on this chipset.
- Simplify some parts of the code (more will follow).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Resolves a number of TODOs items within, and clarified a number of other TODOs.
Change register_values[] from long to u8 (byte). For what we are doing
this is sufficient and makes it only 1/4 the size.
Remove a hard-coding of SDRAMC register that is redundant and now
incorrect, now that SDRAMC is conditioned on SDRAMPWR_4DIMM Kconfig
and set through register_values[].
This fixes all boards with 3 DIMM slots (e.g. ASUS P2B, A-Trend ATC-6220).
RPS registers are now set in runtime code; remove it from
register_values[] table.
Bring DUMPNORTH() back. The code it refers to is still there.
Move #define of NB up so the DUMPNORTH() macro can use it.
Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
On this board all reads from SPD return 0xff by default, there's a custom
GPIO fiddling needed to enable access to the SPD SMBus offsets at
0x50-0x53. While coreboot actually sort of booted sometimes before r5193,
that was just sheer luck as the RAM init was hardcoded in certain ways.
Since the proper, more heavily SPD-based RAM init the brokenness of the
ASUS P3B-F RAM init was becoming visible.
This patch uses GPIOs to enable access to the SPD SMBus offsets,
and resets the GPIOs again after RAM init (this is needed to allow for
lm-sensors to work, for example).
Tested successfully on hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Idwer Vollering <vidwer@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Root cause: After function STOP_CAR_AND_CPU disables cache as
ram, the cache as ram stack can no longer be used. Called
functions must be inlined to avoid stack usage. Also, the
compiler must keep local variables register based and not
allocated them from the stack. With gcc 4.5.0, some functions
declared as inline are not being inlined. This patch forces
these functions to always be inlined by adding the qualifier
__attribute__((always_inline)) to their declaration.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
newer Phenom II.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Stefan Reinauer