2c018fba95
- First pass at s2880 support.
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- SMP cleanups (remove SMP only use CONFIG_SMP)
- Minor tweaks to romcc to keep it from taking forever compiling
- failover fixes
- Get a good implementation of k8_cpufixup and sizeram for the opteron
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21 20:13:45 +00:00
6d4512cdf9
added payload
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21 17:28:35 +00:00
634a99110c
fix crt0 includes ordering
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21 16:51:40 +00:00
9a0989b941
typo fixed.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21 16:22:17 +00:00
1b0e79704f
new chip stuff
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21 15:12:38 +00:00
2b02b63c54
new chip configure
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21 14:00:53 +00:00
73a9cf4ccb
* update quartet target to latest SMP changes.
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* remove dead code from coherent_ht.c
* add ldtstop code for link speed changes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21 13:05:56 +00:00
8275bad6f6
more chip stuff
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21 04:20:08 +00:00
54b3d233ed
more chip stuff
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21 03:38:42 +00:00
d0580343b6
chip stuff
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-20 23:28:01 +00:00
9b4336cf41
- Major cleanup of the bootpath
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- Changes to allow more code to be compiled both ways
- Working SMP support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-19 04:28:22 +00:00
fe4414587a
tidy up
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-19 04:19:48 +00:00
c361a6b218
a few changes
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-19 04:07:07 +00:00
b2e67cdd2c
new config format
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-18 17:17:52 +00:00
6ae46145e6
Allow options in mainboard configuration file
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Moved payload into romimage
More flexible romimage declaration
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-18 17:05:10 +00:00
ce72e7ee21
fix problems with options, more functionality
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-18 01:06:15 +00:00
f3961e0491
add AMD Quartet target
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 22:53:27 +00:00
438a3e423e
moved generate_row from coherent_ht.c to board specific auto.c files
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due to different routing defaults of different boards.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 22:51:30 +00:00
07d72dcfa2
added romimage support
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 22:25:53 +00:00
16743b89fb
new config format
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 22:11:58 +00:00
375505f5cc
dont export sandpoint options
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 22:10:11 +00:00
a8d2240e6a
sick of typing python command
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 17:50:11 +00:00
062d540139
sandpoint options
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 13:14:07 +00:00
b03b33697d
- Update Config so we now have the proper number of cpus
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- Remove some debugging code from auto.c
- Update coeherent_ht.c so we get the proper broadcast routes.
- Fix the dram probing code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 06:34:30 +00:00
2ec0020b3c
- Get the correct routing tables entries for the hdama's onboard nics
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 05:16:46 +00:00
5289938f06
Config.lb for this new part
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 04:35:19 +00:00
387a8db88e
- Remove excess line from pci_device.c
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 04:10:42 +00:00
d520759338
- Remove $Id: from crt0.S.lb
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 03:28:00 +00:00
4086d16ba2
- Implement an enable method for pci devices.
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- Add initial support for the amd8131
- Update the mptable to something possible
- hdama/Config add the amd8131 southbridge
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 03:26:03 +00:00
5fb929e6e3
- pci_device.c fixes for generic pci bridges to zero the unused portion of bridge resources
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- coherent_ht.c remove dead idle loop.
- raminit.c Enable a 64MB mmio window just below 4GB
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17 02:15:46 +00:00
9b45b04d23
fix some glitches in cht code: always enable routing on node7, plus do masking right when setting cpucnt/nodecnt
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-16 15:23:57 +00:00
91a8ce7d80
- ldscripb.lb remove another $Id: line..
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- romcc_io.h Add include guards.
- hdama/Config nothing really but I have been moving the setting back and forth between 1 and 2 cpus
- auto.c Changed the enabled debugging comments. This almost works with 2 cpus
- coherent_ht.c First pass at getting this right. It can now find 2 cpus and place them
in some semblance of a working state.
- raminit.c Fix problems with 4GB of ram. Disable some of the debugging code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-16 07:04:58 +00:00
61b29a9b72
- Commit a binutils safe version of reset16.inc
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-16 01:58:18 +00:00
ae948f78e6
- Compile fixes
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-14 20:40:38 +00:00
50086df616
new config files
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-14 19:02:29 +00:00
8052f4d5da
new init format
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-14 18:03:07 +00:00
109959d6b1
new config rules
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-14 18:00:10 +00:00
68f9b1b135
new init stuff
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-14 17:16:26 +00:00
a485fe9f10
IDE support
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-14 17:08:57 +00:00
70572e64c1
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-13 23:30:23 +00:00
655bf44cde
- Remove all of the annoying $Id strings
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12 02:15:12 +00:00
3d3f438937
- Use an SMBUS_IO_BASE value that will not conflict with an automatically assigned value
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12 01:48:30 +00:00
548593ad66
- generalize generic_sdram.c
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12 01:46:53 +00:00
bd537be3d2
- Add missing carriage return in ramtest.c
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12 01:46:05 +00:00
c24a568551
- Solo updates
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12 01:44:36 +00:00
34cadde255
- Commit more tests for romcc
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12 01:40:54 +00:00
58f74a2514
- Remove use of useless EXT macro
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12 01:39:05 +00:00
64f7162e17
- Initialize list pointers
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12 01:38:35 +00:00
542fe8056b
- Small typo fix in pci_ops.c
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12 01:38:11 +00:00
b3e9b4a534
- Implement division and rdtsc support for romcc
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12 01:37:33 +00:00
Eric Biederman