For add-stage command, --pow2page is equivalent of passing
-P log2ceil(sizeof stage). The sizeof stage can be hard to
determine in Makefile to be passed on the commandline.
Change-Id: If4b5329c1df5afe49d27ab10220095d747024ad6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Currently, the logs are only checked, if retrieved locally. Moving it
after the if statement, now logs retrieved remotely are also checked.
The change in behavior is, that now all commands are executed first, so
before hitting this error, other errors might occur unrelated to the
console log.
Change-Id: I016bbde66c58a654042ad880c6007ddc1d143691
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change drops the check for IS_TOP_ALIGNED_ADDRESS() before
setting offset to 0 in cbfstool_convert_fsp(). If the user provides a
baseaddress to relocate the FSP to, then the offset should be set to 0
since there is no requirement on where the file ends up in cbfs. This
allows the user to relocate the FSP to an address in lower DRAM.
BUG=b:155322763
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ibeadbf06881f7659b2ac7d62d2152636c853fb9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit 9ff4029db9.
Pulling the toplevel Makefile into a tiny one has all sorts of side
effects. For instance, the toplevel (random) .config is also included
so the results depend on the board that is selected there. What finally
broke it is a line that is unconditionally printed for AMD Picasso
boards resulting in lots of lines like this:
skipping LENOVO_W520 because we're missing compilers for \
(Adding PSP c7ce61492157d3237f679c4a40a08b79 \
.../coreboot/3rdparty/amd_blobs/picasso/PSP/PspBootLoader_prod_RV.sbin)
While both issues, the random .config and amd/picasso, could be worked
around easily, it seems hard to predict what other pitfalls are lurking
in the Makefile inclusion. Also, the problem solved by its inclusion
can be fixed by a much simpler `make .xcompile`.
Change-Id: I2ff70f561d717eb30e5f3c06c83e83468e174ec5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
abuild requires the `.xcompile` file to be present already before it
runs any actual `make` builds that would generate it.
Change-Id: Ib485e7741b7700fa241c192e60900ae5f1d977f5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
SPD sources for Dedede and Volteer are being auto-generated by SPD
tools now, and so we can remove SPD_SOURCES from Makefile.inc for
those templates. That makes Makefile.inc empty for those reference
boards, so remove Makefile.inc from the templates.
BUG=b:158492307
BRANCH=None
TEST=Create new variant of volteer, waddledee, and waddledoo, and
verify that we can still build the coreboot image.
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Iba5264384302300cc8d2256a6b43f3353770154a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42204
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GCC 10 GNAT toolchain uses a new exception handler ABI, so older
GNAT cannot be built with GCC 10. This patch backports the new
exception handler in libgnat to make GNAT able to be built.
The libgnat patch doesn't remove the old exception handler, so it can
still be built with older compilers.
The cross toolchain can now be built with GCC 10.1.0 in Arch Linux
(with the latest IASL in CB:38907 that can be built in Arch), and the
toolchain can build a working coreboot image with libgfxinit for HP
EliteBook 2560p.
The original and patched crossgcc built with Debian 10.4 GCC 8.3.0,
and the patched crossgcc built with Arch GCC 10.1.0 generate identical
coreboot images with `make BUILD_TIMELESS=1`.
Change-Id: I757158056bf4698d3c68715e026c226615bc70a1
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42158
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This tells the PSP where in main memory to copy the vboot workbuf.
BUG=b:152576063
TEST=Build sharedmem destination into AMDFW, verify shared memory
gets placed at that location.
Signed-off-by: Martin Roth <martin@coreboot.org>
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830
Original-Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For the verstage-on-PSP implementation, we need 2 additional copies
of the AMD firmware tables at non-standard locations. These are
for RW-A & RW-B fmap regions. This change allows us to build the
AMD firmware tables into those regions.
BUG=b:148767300
TEST=boot with psp_verstage, verify boot location
Signed-off-by: Martin Roth <martin@coreboot.org>
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534
Original-Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: I7f841db8617b953dc671a9c12576145f85263581
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
As per JEDEC spec, manufacturer part name should be set to
blank (0x20). This change updates gen_spd.go to set bytes 329-348 as
0x20 and regenerates SPDs for TGL and JSL.
Change-Id: I6af18d89afd7264cec7e54b38e95df83d55aa058
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42023
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL and JSL:
1. MT53E512M32D2NP-046 WT:E
2. K4U6E3S4AA-MGCR
3. H9HCNNNCPMMLXR-NEE
4. K4UBE3D4AA-MGCR
BUG=b:157862308, b:157732528
Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41989
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a JSON file (`global_lp4x_mem_parts.json.txt`)
containing global list of LP4x memory parts to live along with the spd
tools since the part information is not really any SoC or mainboard
dependent and comes directly from the part datasheet. It can be shared
by mainboards based on different platforms supported by the tools.
BUG=b:155239397,b:147321551
Change-Id: I9e2f98fc9c1c8a7f73c9a1bfab22c996de222a32
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41874
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Serial Presence Detect (SPD) data for memory modules is used by Memory
Reference Code (MRC) for training the memory. This SPD data is
typically obtained from part vendors but has to be massaged to format
it correctly as per JEDEC and MRC expectations. There have been
numerous times in the past where the SPD data used is not always
correct.
In order to reduce the manual effort of creating SPDs and generating
DRAM IDs, this change adds tools for generating SPD files for LPDDR4x
memory used in memory down configurations on Intel Tiger Lake (TGL)
and Jasper Lake (JSL) based platforms. These tools generate SPDs
following JESD209-4C specification and Intel recommendations (doc
Two tools are provided:
* gen_spd.go: Generates de-duplicated SPD files using a global memory
part list provided by the mainboard in JSON format. Additionally,
generates a SPD manifest file (in CSV format) with information about
what memory part from the global list uses which of the generated
SPD files.
* gen_part_id.go: Allocates DRAM strap IDs for different LPDDR4x
memory parts used by the board. Takes as input list of memory parts
used by the board (with one memory part on each line) and the SPD
manifest file generated by gen_spd.go. Generates Makefile.inc for
integrating the generated SPD files in the coreboot build.
BUG=b:155239397,b:147321551
Change-Id: Ia9b64d1d48371ccea1c01630a33a245d90f45214
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
BUG=chromium:1088209
TEST=emerge coreboot-utils (with patches to the ebuild) works
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I25d237d048e417f4e412583031905ecf3614c431
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change adds support to sconfig for generating the firmware
configuration field and option definitions in devicetree.cb.
In addition these fields and options can be used to probe for a device
and have that device be disabled if it is not found at boot time.
New tokens:
fw_config: top level token, table can be defined before chips
field: define field in the mask with the start and end bits
option: define option in a field with the value of the field
probe: indicate that a device should probe by field and option
Example:
fw_config
field FEATURE 0 0
option DISABLE 0
option ENABLE 1
end
end
chip drivers/generic/feature
device generic 0 on
probe FEATURE ENABLE
end
end
Variants can add new fields and add new options to existing fields in
overridetree.cb but cannot redefine an existing option.
Devices can have multiple probe tokens, and the device will be considered
to be found if any of them return true.
The output from defining this field are:
1) the various fields and options will be added as macro constants to
static.h and can be used by fw_config for probing.
2) the probe entries will result in a list of fields/options to probe
that is added to the resulting struct device and handled by coreboot.
BUG=b:147462631
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I8aea63e577d933aea09e0d0b09470929cc96e0de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This should make it easier to add more includes.
Change-Id: Ib4a25352901408c2b36de4972391df742a0d8037
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41744
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
add_register() contained a duplicate check but only compared the new
key to the first (smallest in order) list member. Fix that and factor
the list handling out so it can be used by other functions.
Change-Id: I5a8346f36fa024351e1282c9681868ecf451b283
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41743
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
They're not added as a dependency, even though that should be possible,
because we want the build tests to run even when the unit tests fail.
Change-Id: Ia3391d7b289160178fa773dfd7b7c51c6ef77805
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The templates for the zork reference boards are still being actively
worked on in the trembyle-bringup branch. Remove the zork template
from the main branch to avoid confusion when trembyle-bringup is
merged.
BUG=b:157099580
BRANCH=none
TEST=N/A
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I0ff9de959c7b2646b90e68df05f0b2e9bdd60cf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The majority of the codebase has been converted to use SPDX identifiers
now, so let's enforce those by default. The only exceptions are
src/include and src/lib, which are not being checked since many of the
files there do not have license headers at all. Files with custom
licenses that aren't covered by SPDX can be listed as exceptions at the
top of lint-000-license-headers.
Change-Id: Ie6642153793d5735c74c5950bc9e27ee7eecacbc
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41602
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Our jenkins instance is also used for flashrom, which can be built with
meson, a mode that we want to be able to test, so add that.
ninja can be used as a backend to both meson and cmake (which coreboot
will use to build cmocka for its unit tests) and may provide some
additional coverage. Plus it's tiny but fast.
Change-Id: If454164852303144eaa72c4071c03ee89e863318
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The code was written on a workstation that has python
pointing to python3.
BUG=b:157140753
TEST=Built trembyle and was able to boot to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I181d87aad1ffb10e12f8ffd7513318f6d6bcbc3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41739
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Convert the remaining files in src/drivers to use SPDX identifiers.
int15.h and default_brightness_levels.asl did not have license headers,
but they were both copied from other GPL2 files, so they should be under
the GPL2 as well.
ne2k.c and drm_dp_helper.h are licensed under custom BSD-like licenses
that do not have an SPDX equivalent, so they are added as exceptions
to the license header lint.
Change-Id: I87fb1c637b8d11b0463f7c19f70b847413e14aed
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Had to increase MAX_PSP_ENTRIES to accommodate the 16 APCBs we have
the ability to add.
BUG=b:150862063
TEST=Boot Trembyle
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I64eccfa28839768788f53327caf187a564842162
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2090323
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41580
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On the Picasso architecture, the PSP is responsible for setting up DRAM
before releasing the x86. The APCB (AGESA PSP Configuration Block)
contains multiple SPDs and the GPIO numbers used to select the correct
SPD. Since the source to build the APCBs is not public, it can't be
built as part of the coreboot build. To work around this problem, we use
a template APCB and inject the relevant information.
BUG=b:147042464
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I88a09743f8e8a184c47071ee5e417f5b6bdb7467
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2123799
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fix unterminated array.
When looking for a type not specified in filetypes (cbfs.h:204), the
loop in lookup_name_by_type (cbfs_image.c:60) will run into a buffer
over-read.
Found-by: AFL++ 2.64d rev 1317433
Signed-off-by: Philipp Bartsch <phil@grmr.de>
Change-Id: Ib82bb92e82b09fa1e26b9ca34529ec7b98e8f7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41421
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
genrelnotes moves the tree between commits and so a relative location
like HEAD isn't stable. Since I ran into the HEAD issue while preparing
for two consecutive releases, let's guard against it.
Change-Id: I70c6812cdfe0d0671b3d653744a062d9920a2394
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41339
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
genrelnotes checks for cloc, git and rename but only reported about
needing the first two, so mention `rename` in missing message.
Change-Id: If91d759fc68760fd89b98756ac5b19ac3589c197
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Picasso has an LPC and eSPI bridge on the same PCI DEVFN. They can both
be active at the same time. This adds a way to specify which devices
belong on which bus.
i.e.,
device pci 14.3 on # - D14F3 bridge
device espi 0 on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end
device lpc 0 on
end
end
BUG=b:154445472
TEST=Built trembyle and saw static.c contained the espi bus.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently inteltool uses the addresses and names of the PCH of
previous generations. It's wrong for Lynx Point LP and Wildcat Point.
The addresses and names of the I/O registers can be found in "Mobile
4th Generation Intel Core Processor Family I/O Datasheet" (Document
Number: 329003-003) for Lynx Point LP and "Mobile 5th Generation Intel
Core Processor Family I/O, Intel Core M Processor Family I/O, Mobile
Intel Pentium Processor Family I/O, and Mobile Intel Celeron Processor
Family I/O Datasheet" (Document Number: 330837-004) for Wildcat Point.
Change-Id: If6ba718ccff077aa89affec89018bd7923527466
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40273
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Historical Permission Notice and Disclaimer (with and without
permission to sell) is a BSD-style license family that OSI and SPDX
consider deprecated - and yet, it's right here in our tree.
Change-Id: I61624b6e54e9aba6e2f54822c1f68967c416ad3d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41221
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In a few cases a license was added: Stuff coming from Linux is
"GPL-2.0" (not GPL-2.0-only!), build-release is by me and got the
usual GPL-2.0-only treatment. uio_usbdebug and spkmodem had their
licenses propagate to all their files.
Change-Id: Ia5712bbaa417cb9e937834512351fcc0acfa16be
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41202
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As requested by Stefan.
For nvramtool some of these lines are part of a paragraph of fluff,
so manual processing was easier than adapting the script used for
the rest of the tree.
Change-Id: Id52c4c264cded0582a97da131b695a046cbd67c6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
This is all code coming from the outside, so let's keep these files
untouched as much as possible.
A couple of files is added to the list by name because their license,
while free, can't be properly modelled in SPDX:
- lzmadecode is (LGPL OR CPL) WITH special-exception
- stack.c and start16 are some weird (but free) US Gov't license grant
- two XGI related files have "BSD except for Linux, where it's GPL"
Change-Id: I42dec503b9c427a66792d3fec99ca8df1a360e47
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
We have the git history which is a more reliable librarian.
Change-Id: Idbcc5ceeb33804204e56d62491cb58146f7c9f37
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
chip_instance structure currently uses a ref_count to determine how
many devices hold reference to that instance. If the count drops to
zero, then it is assumed that the chip instance is a duplicate in
override tree and has a similar instance that is already overriden in
base device tree.
ref_count is currently decremented whenever a device in override tree
matches the one in base device tree and the registers from the
override tree instance are copied over to the base tree instance. On
the other hand, if a device in override tree does not match any device
in base tree under a given parent, then the device is added to base
tree and all the devices in its subtree that hold pointers to its
parent chip instance are updated to point to the parent's chip
instance in base tree. This is done as part of update_chip_pointers.
However, there are a couple of issues that this suffers from:
a) If a device is present only in override tree and it does not have
its own chip (i.e. pointing to parent's chip instance), then it
results in sconfig emiiting parent's chip instance (which can be the
SoC chip instance) in static.c even though it is unused. This is
because update_chip_pointers() does not call delete_chip_instance()
before reassigning the chip instance pointer.
b) If a device is added under root device only in the override tree
and it does not have its own chip instance (i.e. uses SoC chip
instance), then it results in sconfig emitting a copy of the SoC chip
instance and setting that as chip_ops for this new device in the
override tree.
In order to fix the above issues, this change drops the ref_count
field from chip_instance structure and instead adds a forwarding
pointer `base_chip_instance`. This is setup as per the following
rules:
1. If the instance belongs to base devicetree, base_chip_instance is
set to NULL.
2. If the instance belongs to override tree, then it is set to its
corresponding chip instance in base tree (if present), else set to
NULL.
State of base_chip_instance is then used when emitting chips and
devices using the following rules:
1. If a chip_instance has non-NULL base_chip_instance, then that chip
instance is not emitted to static.c
2. When emitting chip_ops for a device, base_chip_instance is used to
determine the correct chip instance name to emit.
BUG=b:155549176
TEST=Verified that the static.c file generated for base/override tree
combination is correct when new devices without chips are added only
to override tree.
Change-Id: Idbb5b34f49bf874da3f30ebb6a6a0e2d8d091fe5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41007
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves the assignment of id for chip instance from
new_chip_instance() to emit_chips(). This is similar to the previous
change for moving dev id assignment to happen much later.
This ensures that the same ID gets assigned to a chip when adding
support for device trees which makes it easier to compare static.c
files.
BUG=b:155549176
Change-Id: I3efa9af5ed91123675be42bce1cb389bad19cb62
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change drops the id field from struct device as used by
sconfig. It was primarily used for generating unique device names. This
was maintained within device structure so that the order in which the
device tree entries were parsed is clear. Since the ids are assigned
in parsing order, it is problematic when a device is moved from base
devicetree to override tree. The entire parsing order changes which
makes it really difficult to compare what really changed in static.c
file.
By moving the dev name assignment to happen later when doing pass0 of
static.c generation, the difference in static.c file is minimized when
adding support for override trees.
BUG=b:155549176
Change-Id: I31870ace5a2fd7d5f95ab5e30d794c3bc959ed46
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This replaces GPLv2-or-later and GPLv2-only long form text with the
short SPDX identifiers.
Commands used:
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Also split "this is part of" line from copyright notices.
Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
That makes it easier to identify "license only" headers (because they
are now license only)
Script line used for that:
perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist...
Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Every device belongs to a chip. And we already keep that relation by
inheriting the `.chip_info` pointer if downstream devices don't have
another chip specified. So we can also allow to specify `register`
settings at the device level.
Change-Id: I44e6b95d0cd708fef69b152ebc46b869b2bb9205
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40803
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was always defined to the same value, and only used twice.
Change-Id: I2736eb7ea2cf15475f7bb99d7d12450730eb8be0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40864
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
It replicates the functionality of savedefconfig because back when the
script was added, savedefconfig didn't work for us. It now does, is
the official way of doing things, is recommended in our documentation
and is also a fair bit faster.
Change-Id: Ia8e0377537ff7cd638c564037ea6a77b01a87243
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update all occurrences of vboot and spell it lowercase.
Change-Id: I432b0db8a3dda43b71844e557a3d89180f25f1c3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There are microcodes in .inc format out in the wild which contains
lines with just a comment. So these files look like the following
example:
; External header
dd 000000001h
dd 00000001bh
...
; Data
dd 000000000h
...
The lines with just a comment starts with a ';' and will break
the current awk formatting which is performed to reformat the content
into C code style. As we are just interested in the data we can simply
drop all lines that start with a ';' which sed can do pretty easy.
Change-Id: I9ff5db51667672cffd9d776fb9497962b4a6083a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The double quotes around the remaining shell parameters '${@:2}' causes
that the provided *.h files in $(CONFIG_CPU_MICROCODE_HEADER_FILES),
which is a space separated list, cannot be broken down to every single
file as needed but stay as a single parameter in the for-loop.
Therefore, the called function 'include_file' will get a single
parameter with all files which will lead to a broken C code in
terms of a wrong #include-syntax. This causes the script to fail.
To fix this remove the double quotes which works just fine.
Change-Id: Iab7b0dc8d850973d6af764899907d383e9ec7743
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Newly added code in commit CB:25546 contains spaces instead of TABs for
line indent. Replace every 4 spaces by a single TAB to match our coding
guides.
Change-Id: Ie3633bb42643f4abb5f1a8827a7dc2c9e023d6aa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Remove entries for old utilities and add entries for new ones.
Generated using util/util_readme, with some tweaks to preserve the
markdown.
Change-Id: I3a4d8a6bf15a677aa07aa72b8809328110fb72da
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
CB:29744 ("util/cbfstool: Add optional argument ibb") added support
for non-ASCII characters for long_options. However, there is a check
later on which errors out since this character is not one of the
commands[i].optstring.
This change adds a function valid_opt() which does the following
things:
1. Checks if the returned optchar is among the list of optstring
supported by the command.
2. Checks if the returned optchar is a valid non-ASCII
option. Currently, we do not maintain a list of non-ASCII options
supported by each command. So, this function returns true if the
optchar returned by getopt_long falls within the allowed range.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I27a4f9af9850e4c892573202904fa9e5fbb64df6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
DSDT can be bigger than 0x10000 bytes, so increase the space up to 1MB
for an ACPI table and support lines in acpidump.log with address
higher than 0x10000.
Change-Id: Iaadcfd0964c1c516e9e39d6cbfe41ec9a8c45e9d
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31759
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To provide sane defaults for most of the user base, this patch switches
on the USE_BLOBS option by default. Since it only changes the default,
this behaviour can still be easily disabled.
With this abuild doesn't have to select USE_BLOBS any more, so what
abuild tests becomes the coreboot default again.
Change-Id: Ia0632b9ae7a1f212a8640b3faec2695d17d238c5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
'result' is already defined as 'unsigned long long result = 0;' so no
need to re-write 'result = 0;'.
Change-Id: Ie897453fb5e7b09af755ce8d61ee8e80943ffc1c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We can make our lifes much easier by removing its dependency on
`ADD_FSP_BINARIES`. Instead, we imply the latter if the repository
is to be used. We can also hide a lot of unnecessary prompts in
this case.
Also, remove default overrides and selects for the two that are
now unnecessary.
Change-Id: I8538f2e966adc9da0fbea2250c954d86e42dfeb3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39882
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's helpful to see the sibling field, even when it's NULL, when
debugging the static.c output from a devictree.cb file. Ensure the
NULL fields are emitted for fullness.
Change-Id: Ib6d5b8164769a6512e762d5a525c7df1f429c866
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently, there are a lot of uploads in the board status repository,
where the logs say, that the coreboot image or payload were built from a
dirty source tree. Add a check to reject such uploads.
Change-Id: I920e26a10f74e1f3b9b4e5f8c9284c59692a519b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The `link_frequency_270_mhz` setting was originally used by the native
graphics init code for Sandy/Ivy Bridge, which is long gone.
The value of this information (which board had it set) is questionable.
The only board that had an LVDS panel and set it to 0 was the ThinkPad
L520, where native graphics init was never reported to work. Also, the
native graphics init only used it for calculations, but never confi-
gured the hardware to use a specific frequency. A look into the docu-
mentation also doesn't reveal any straps that could be used to confi-
gure it.
Change-Id: Ieceaa13e4529096a8ba9036479fd84969faebd14
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39763
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the inteltool path to the include path to be able to avoid ugly
include hacks like `#include "../inteltool.h"`.
Change-Id: Id363fa20fe3b52248a224ca14b2626a8e3ce44a2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39744
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a script generated list of vboot enabled devices to the
documentation. Add a entry to the release checklist.
Change-Id: Ibb57d26c5f0cb8efd27ca9a97fd762c25b566f93
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently cbfstool cherry-picks a few files from vboot and hopes these
files will work standalone without any dependencies. This is pretty
brittle (for example, CL:2084062 will break it), and could be improved
by building the whole vboot library and then linking against it.
Therefore, this patch creates a new target $(VBOOT_HOSTLIB) and includes
it as a dependency for cbfstool and ifittool.
To prevent building the vboot lib twice (one for cbfstool and the other
for futility) when building coreboot tools together, add the variable
'VBOOT_BUILD' in Makefile to define a shared build path among different
tools so that vboot files don't need to be recompiled.
Also ignore *.o.d and *.a for vboot library.
BRANCH=none
BUG=none
TEST=make -C util/cbfstool
TEST=make -C util/futility
TEST=Run 'make tools' and make sure common files such as 2sha1.c are
compiled only once
TEST=emerge-nami coreboot-utils
Change-Id: Ifc826896d895f53d69ea559a88f75672c2ec3146
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This adds the code required to dump config registers.
Change-Id: Ic78f847ba07240c112492229f9a23f9a88275ad9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The single apostrophe confuses the shell that's calling the command.
Change-Id: I7d3183e9a612de0121b2d208c06a45645b8d67f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Split common flags that are not specific to the C language out of
$CFLAGS_GCC into $FLAGS_GCC. This way, we can test for C specific
flags, too, without adding them to $ADAFLAGS_*. Currently this is
done for `-Wno-address-of-packed-member` which only applies to C.
Change-Id: Ib793c62656efb07b6e5b3385f1ed1c96a40efd1d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39633
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Additionally provide a simple script for decoding spd hex files using bincfg.
BUG=b:148561711
TEST=Decoded spd files in zork
BRANCH=None
Change-Id: Ic62868d59e075fd6816d7be55cc935e3e3f82499
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/2067697
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Uppercase `AFE` is an acronym for `Analog Front-End`. As it is a valid
spelling, comment out its entry to prevent false positives.
Change-Id: Ib8612d970d33d4955c572838bda217cfdb49dfe6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
If they were removed instead, it would be too easy to end up adding them
back again. They are kept in a comment so that they can be tracked.
Also, explain why these two entries have been commented out.
Change-Id: I8225944b5e3d1e022af169dda33e0344d4c3bccd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The existing Sunrise Point ids are assigned to the wrong implementation,
which would never work for these chipsets. Assign them to the right
dumping implementation, which works for both Sunrise Point PCH-H and
PCH-LP.
This also adds some missing device ids from doc#332691-003EN and
doc#334659-005.
Change-Id: Id102ef3809d675dc9a915d2cb3062e093487fa27
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There is no need to use hexadecimal values in azalia codec IDs, nor need
to print a redundant "LPC bridge PCI-LPC bridge" comment.
Change-Id: I6658051c7a3d5b65a86ccca8bab7834bf4628a16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Print out the name of the file that failed to open.
BUG=none
TEST=rerun build-board.sh with missing files
BRANCH=none
Signed-off-by: Eric Peers <epeers@google.com>
Change-Id: Id8543f25ea827fc8764e0315434b834e65bfa7fb
Reviewed-on: https://chromium-review.googlesource.com/2090667
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a bunch of missing chipsets to print_bioscntl.
Change-Id: I96c010a1d64dcf5296f78a6decd1a218aba4b04f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This adds the Sunrise Point AHCI config and SIR registers from
doc#332691-003EN.
Change-Id: Id4a462d625194a6ccfdb88fb415d5eb278f2900a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39506
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds the code required to dump config and SIR registers.
Change-Id: I3726c52d415ff4dd6b19513b310f11254f7fbf92
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39560
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rework AHCI to align the code with the rest of inteltool.
Change-Id: I37116f8e269d0376e147dd6de7365c45ac90bda0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39504
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
So far printing the GPIO groups chose the community definition. As the
list of supported platforms grows the massive switch case gets repetetive
and hinders the readers view.
It also reduces the ability to reuse the code in a potential libinteltool.
To takle these issues the detection logic was split into its own function.
Change-Id: I215c1b7d6ec164b8afd9489ebd54b63d3df50cb9
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38631
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moved the Denverton definitions into its own header.
Change-Id: I6ce672c24059b9f3a4a984766184066f14df3013
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38630
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Angel Pons