Commit Graph

26042 Commits

Author SHA1 Message Date
Angel Pons 392e886552 util/superiotool: Add Winbond W83667HG register dump
This SuperIO is supported by coreboot and used in two Asus boards. However,
superiotool was lacking a register dump for this chip. Add the corresponding
data from datasheet W83667HG-B revision 1.3 into superiotool.

The SuperIO's datasheet was obtained by requesting it to Nuvoton.

Change-Id: Ie51dc492c761d9c3d4b6100017bb730b1ae6d1e0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-13 13:30:46 +00:00
Angel Pons cde835e39e src/mainboard/*/*: Set Mini-ITX boards' category to "mini"
Change-Id: I637792d3bf22d2e452144d44ba03cfe45b47501d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-09-13 08:29:16 +00:00
Angel Pons a52016cc46 src/*/intel: introduce warning when building with no IFD
Add a warning as suggested in patch CB:28233 with the
"CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED" option.

Change-Id: I42b6b336bb519f3d18b5a41eb20b380636ff5819
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-09-13 08:25:59 +00:00
Stefan Tauner ef8b95745f src/*/intel/: clarify Kconfig options regarding IFD
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid
Inter Flash Descriptor to exist. It does *not* identify platforms or boards
that are capable of running in descriptor mode if it's valid.
Refine the help text to make this clear.

Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply
declare that IFD is supported by the platform. Select this value everywhere
instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to
y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected.

Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to
the mainboard directory.

Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-13 08:25:31 +00:00
Raul E Rangel 9fc7b8e973 libpayload/x86/delay: Make arch_ndelay call apic_delay if delay is long
This reduces power consumption on grunt by over 3W when sitting at the
depthcharge recovery screen.

BUG=b:109749762
TEST=Booted grunt in the recovery screen and made sure it continued to
work.

Change-Id: Id079c099ee4cf6a07724241af4400063f4551668
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28245
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Julius Werner <jwerner@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12 14:15:48 +00:00
Raul E Rangel 370c116ca5 libpayload/x86/delay: Add an x86 arch_ndelay
This method has a pause instruction to help the CPU relax a little bit.
Measuring grunt it saves about 80mW.

BUG=b:109749762
TEST=Made sure that grunt boots.

Change-Id: I045a941ed42fcc4f2dbdd65b5cbb42d84813f50c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28244
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12 14:15:25 +00:00
Raul E Rangel d63627fb84 libpayload/libc/time: Add an arch_ndelay()
Replace _delay with an arch_ndelay(). This way each arch can setup their
own delay mechanism.

BUG=b:109749762
TEST=Verified delay's still work on grunt.

Change-Id: I552eb30984f9c21e92dffc9d7b36873e9e2e4ac5
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28243
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12 14:15:18 +00:00
Raul E Rangel 24ae85c3ff libpayload/x86/apic: Add an apic_delay method and calibrate the timer
The apic_delay method will halt the CPU and wait for a timer interrupt
to fire. I went with usec because nsec is too granular to guarantee.

This method will be called from an arch_ndelay() method when the delay
is large enough to justify a sleep.

BUG=b:109749762
TEST=Tested it on grunt by changing the _delay method to call
apic_delay().

Change-Id: I80363f06bdb22d0907f895885e607fde1c4c468d
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-12 14:15:11 +00:00
Raul E Rangel ac8ebd0e73 libpayload/arch/x86: Add support for initializing the APIC
This is just the bare minimum required to initialize the APIC. I only
support xAPIC and chose not to support x2APIC. We can add that
functionality later when it's required.

I also made the exception dispatcher call apic_eoi so that the callbacks
won't forget to call it.

BUG=b:109749762
TEST=Booted grunt and verified that depthcharge continued to function
and that linux booted correctly. Also verified GDB still works.

Change-Id: I420a4eadae84df088525e727b481089ef615183f
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-12 14:14:46 +00:00
Philipp Hug 3d398ad37a soc/sifive/fu540: Initialize PLL and clock
Change-Id: Iba0669e08940e373aaf42cbba3a1ceffd68a4f52
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-12 12:31:28 +00:00
Patrick Georgi 803cf02801 mainboards: Add SMMSTORE region in chromeos configs
Only for those that are x86 and also have a RW_LEGACY region.
The assumption is that all devices touched have 64k block sizes when
choosing size and alignment of the region.

Change-Id: I12addb137604f003d1296f34f555dae219330b18
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-12 12:25:30 +00:00
Jonathan Neuschäfer 15192da7c7 soc/amd/stoneyridge: Fix more GPIO functions
Instead of gpio_num, gpio_address should be used as the address in
write32. This lets us also get rid of a few casts.

Commit c9ed3ee8d8 ("soc/amd/stoneyridge: Fix gpio_set function") fixed
one instance of this bug, but it was more widespread.

TEST=None

Change-Id: I0cf87aac2f1b87b6eac2b506515e48fe908c1f2b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-12 11:54:09 +00:00
kane_chen 8c4561d2ef rammus: add SPD mapping for rammus and shyvana support
Add MICRO 4G and 8G SPD file.

BUG=none
BRANCH=master
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure system boots up.

Change-Id: I7cb5b7f2bcdc6fbe0cbc640cad4af014f1a0edd6
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28484
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12 07:06:40 +00:00
Marshall Dawson 9a32c41c03 amd/stoneyridge: Enable BERT table generation
Add a duplicate ACPI_BERT symbol with a 'y' default setting and additional
help text.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I817111cbd3e81b93d8b02d0654ba68c8678b1bbe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-11 20:36:24 +00:00
Marshall Dawson f0de242df0 amd/stoneyridge: Set BERT region size when no TSEG used
Expand the BERT reserved region size setting to account for the
possibility of no TSEG configuration.  This change is only for
completeness, as stoneyridge must always use TSEG.

Change-Id: I90753fa408cfac4de38aff08979c45349bb62a66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-11 20:36:11 +00:00
Paul Menzel 63ebb5bde1 soc/intel/baytrail: Remove trailing space in log message
Currently, there is a trailing space in the log message below.

> Enabling VR PS2 mode: VNN VCC

So, put the space before the word.

Change-Id: Ic536d77aa910b1b98a3c2f35d595dee4251b1c18
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/28525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-09-11 12:39:11 +00:00
Elyes HAOUAS 05b1cb8be3 src/device/dram: Fix typo
Change-Id: I5d8e5f978c538d2b9f74b29e21eb39ce6455315f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-09-11 12:38:41 +00:00
Philipp Hug e0568595ee soc/sifive: fix compiler warning
Fix the following compiler warning on the latest toolchain:
src/soc/sifive/fu540/otp.c:48:1: error: useless storage class specifier in empty declaration [-Werror]
 } __packed;
 ^

Change-Id: Ice87c821de7650ac547394efa2a4bcc5ae1ea668
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28553
Tested-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-10 20:37:17 +00:00
Philipp Hug 2cf9990ec8 soc/sifive/fu540: Makefile: include mtime_init in ramstage
Fix compilation issue
clint.c/mtime.c is needed as well in ramstage due to CR 28372 and 28355

Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28551
Tested-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-10 20:36:45 +00:00
Ren Kuo 7f60d24fbd mb/google/poppy/variants/nami: Add SPD for two memory parts
add two memory parts and ram id:
hynix_dimm_H5ANAG6NCMR-VKC
micron_dimm_MT40A1G16KNR-075E

BUG=b:113983573
BRANCH=Nami
TEST=emerge-nami coreboot chromeos-bootimage

Change-Id: Ia052f16b6c1e64ee6458fbdeea56a482a728c35a
Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/28536
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10 15:05:54 +00:00
Philipp Hug ea81928e94 soc/sifive/fu540: Add driver for OTP memory
Provides minimal functionality to read the SOC s/n from the NeoFuse
one time programmable memory.

Change-Id: I14b010ad9958931e0a98a76f76090fd7c66f19a0
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-10 15:05:11 +00:00
marxwang 3b8ef2b01d mainboard/google/poppy/variants/rammus: Enable DA7219
On rammus, headset uses DA7219 so that we need to enable it.

BUG=b:112945714
BRANCH=master
TEST=emerge-rammus coreboot chromeos-bootimage
Flash FW and check in kernel to see if DA7219 is up.

Change-Id: I92dd412374d007aab264661e698fbbbbcf1eae45
Signed-off-by: marxwang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28537
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10 15:04:50 +00:00
Maulik V Vaghela b2e56c1160 soc/intel/cannonlake: Correct number of root ports for CNL PCH H
CNL PCH H supports maximum 24 root ports while CNL PCH LP supports
maximum 16 root ports.

Change-Id: I2cc3ae282d4eb5da8b0618451e062a6c061f1d6f
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/28399
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10 15:04:32 +00:00
Xiang Wang cda59b56ba riscv: update misaligned memory access exception handling
Support for more situations: floating point, compressed instructions,
etc. Add support for redirect exception to S-Mode.


Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-10 15:03:58 +00:00
Xiang Wang aa5f821ee3 soc/sifive/fu540: add CLINT support
Change-Id: Ibc3a8644dcb83d5697d9d6e551c7682377285116
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-10 15:03:37 +00:00
Xiang Wang 2e38dbe5f1 riscv: update mtime initialization
Add a interface, which is implemented by SoC.

Change-Id: I5524732f6eb3841e43afd176644119b03b5e5e27
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-10 15:03:08 +00:00
Aaron Durbin 0370bcf40c complier.h: add __noreturn and use it in code base
Add a __noreturn macro that wraps __attribute__((noreturn)) and replace
current users with the macro.

Change-Id: Iddd0728cf79678c3d1c1f7e7946c27375a644a7d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-10 15:02:51 +00:00
Shaunak Saha 261d626669 mb/google/poppy: Set UPD CmdTriStateDis for Nocturne
This patch sets the MRC UPD CmdTriStateDis for the
nocturne boards.Nocturne is LPDDR3 design without RTT
for CMD/CTRL.

BUG=b:111812662
TEST=Run memtester app and also webgl fishtank on
     the LPDDR3 kabylake boards and also check the
     margin data is proper in FSP.

Change-Id: I0f593761dcbd121e7e758421af178931b9d78295
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/28379
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10 15:02:17 +00:00
Shaunak Saha ef250c47e4 soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree
This patch adds the support for CmdTriStateDis FSP upd in skylake
soc structure so that we can define it in devicetree.CmdTriStateDis
needed to be set for the skylake/kabylake based boards where LPDDR3
design is without RTT for CMD/CTRL.We need to set this bit for those
designs for the margin to be proper.

BUG=b:111812662
TEST=Run memtester app and also webgl fishtank on
     the LPDDR3 kabylake boards and also check the
     margin data is proper in FSP.

Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/28424
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10 15:02:05 +00:00
Raul E Rangel f47ccbdd47 libpayload/x86/gdb: Migrate to use set_interrupt_handler
BUG=b:109749762
TEST=Verified GDB still functions by hitting Ctrl+G on the developer
screen and stepping through some code.

Change-Id: I723a8a95f681c500d9d8e35e49fd1d893cb1f133
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-10 15:01:19 +00:00
Raul E Rangel 80d5c19590 libpayload/x86/exception: Add ability to handle user defined interrupts
I need to setup the APIC timer to fire interrupts. I would like to reuse
the existing interrupt table. So I extended it to support user defined
interrupts. I just added all 255 vectors so there wouldn't need to be
any additional build time configuration.

I'm going to deprecate exception_install_hook and remove it in a follow
up. It will be replaced with set_interrupt_handler. This way the
exception lookup does not have to manage a list of callbacks, or have to
worry about the order they are processed.

BUG=b:109749762
TEST=Wrote an interrupt handler and fired an APIC timer interrupt and
verified that vector 32 was returned.

Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-10 15:01:04 +00:00
Patrick Rudolph 28cee59ca2 drivers/vpd: Add VPD support
VPD reference: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md

Copy ChromeOS VPD driver to add support for VPD without CROMEOS.
Possible use case:
* Storing calibration data
* Storing MAC address
* Storing serial
* Storing boot options

+ Now it's possible to define the VPD space by choosing
  one of the following enums: VPD_ANY, VPD_RW, VPD_RO.
+ CHROMEOS selects now VPD as part of it.
+ VPD is implemented as driver.

Change-Id: Id9263bd39bf25d024e93daa57053fefcb1adc53a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25046
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-09 17:51:37 +00:00
Martin Roth c4b0fd0a86 mainboard/google/kahlee: Reset trackpad & touchscreen
AMD chips don't hold off a reset to the end of I2C transitions, so
devices on the i2c bus can be left in a bad state.  To avoid this,
make sure the trackpad and touchscreen chips get disabled
during boot.

BUG=b:114411165
TEST=build, reboot watch trackpad enable go low

Change-Id: Ie50f4a102249df79517da571a6e768dba804cd57
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28538
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-09 16:18:25 +00:00
Caveh Jalali 41979d862a mb/google/poppy/variants/atlas: enable NVMe
This adds support for a x2 NVMe device on PCIe bus PCIe lines 5+6 and
clock#4.

BUG=b:113369699
TEST=booted on atlas

Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-07 23:40:08 +00:00
Patrick Georgi dce4d465a6 util/crossgcc: Tell gcc that it'll use gnu as and ld
Otherwise it reduces its expectations on what as and ld take in terms
of arguments, which breaks some edk2 related builds because tons of
-I$path_to_stuff arguments aren't passed along.

Change-Id: I53f87442de03d5ead8a6632d3102d5502065b828
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07 19:17:15 +00:00
Richard Spiegel 7160766ebf lib/gpio.c: Fix _gpio_base3_value invalid shift
Coverity CID 1395334: (BAD_SHIFT) - In function _gpio_base3_value(), if
gpio_num is 32 and gpio[31] is floating, the end result is 1 << 32, which
does not fit into a int. To avoid a possible error, make it an error to have
num_gpio > 31. Function _gpio_base2_value also have the same issue, but the
limit would be 32. As in practice it'll never be used with more than 20 GPIO,
create a helper function to limit it to 31 and call it everywhere needed.

BUG=b:113788440
TEST=Add a fake code to southbridge_final calling the function and printing
the result. Build and boot grunt, check result.

Change-Id: I0b79725bcbaf120587c7440e176643aaa7a1d5bb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28445
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:53:54 +00:00
Marshall Dawson 653f760b13 amd/stoneyridge: Construct ACPI BERT table
Add a Boot Error Record Table to the ACPI information.  Avoid a driver
error message by skipping the table altogether when no errors are found,
or support isn't built in.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I6fe38eefacaad0bc73d0cb4ae44a339a45857128
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28478
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:52:53 +00:00
Marshall Dawson 64e1fcaaf9 amd/stoneyridge: Construct BERT region from machine check
Add functions to build a Boot Error Record Table region based on
settings found in the MCA registers.

Two entries are reported for each error due to the nature of the ACPI
driver.  The first is a Generic Processor Error, which the OS recognizes
and parses.  Generic errors cannot convey much error description or
processor context.  Therefore an IA32/X64 Processor Error is also added,
which allows reporting the values found in the MCA MSR registers.

Follow-on work could decode the MC errors more precisely, and better
completing the Generic Error and the Check structure.  The current
level of support is sufficient to identify a (i.e., human readable)
problem in dmesg, and provides adequate context information for
analysis.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I4d4ce29ddefa22aa29e6d3184f1adeaea1d5f837
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28477
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:52:32 +00:00
Marshall Dawson e1bd38bec5 amd/stoneyridge: Create an MCA structure
Convert the Machine Check reporting to use a newly defined structure.
This will facilitate later patches that will pass pointers to the MSR
values.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I0a98aecc83a0fa1c5ca7926849a89145a595d9ff
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28476
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:52:03 +00:00
Marshall Dawson 0b4a1e220a amd/stoneyridge: Relocate MCA error identification
Move the process of interrogating the Machine Check registers into
its own file.  This rearranges source code in preparation of supporting
a Boot Error Record Table, which stoneyridge will use to report latent
MC errors to the OS.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: Ia3275e9135dc96ba4a717c9371f38843fa1e3e64
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07 14:51:42 +00:00
Marshall Dawson 4b0f6fa156 amd/stoneyridge: Adjust memory map for reserved
Carve out memory to be reported to the OS as reserved.  This makes
room for a region usable for Boot Error Record Table information.
The BERT region reserved size is larger than likely requried, however
the SMM region's base must be on a boundary matching the granularity
of its size.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I0958f6b6bab3fe9dae36c83e1fd9ae6ed0290a18
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28474
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:51:31 +00:00
Marshall Dawson bb7f1b41e7 amd/fam15: Add more MCA information
Add more definitions to be used for Machine Check Architecture
support, mainly for determining the type of error that is being
interpreted.  MCA is described in detail in the BKDG.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I0682288aa58c69aee323fb43f74027f7a1905b68
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07 14:51:03 +00:00
Marshall Dawson 1d8d369dad x86/acpi: Add BERT table
Create a structure for the Boot Error Record Table, and a generic
table generator function.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: Ibeef4347678598f9f967797202a4ae6b25ee5538
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07 14:50:34 +00:00
Marshall Dawson 44705c6e5e x86/acpi: Add BERT to the revision table
Add the proper table revision level for the Boot Error Record Table.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
    data plus a failing Grunt system.

Change-Id: Ib4596fe8c0dd2a4e2e98df3a1bb60803c48d0256
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28471
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:50:16 +00:00
Marshall Dawson 991467da4d arch/x86: Add BERT region support functions
Add code for generating the region pointed to in an ACPI Boot Error
Record Table.

The BERT region must be reported as Reserved to the OSPM, so this
code calls out to a system-specific region locator.  cbmem is
reported as type 16 and is not usable for the BERT region.

Events reported via BERT are Generic Error Data, and are constructed
as follows (see ACPI and UEFI specs for reference):
 * Each event begins with a Generic Error Status Block, which may
   contain zero or more Generic Data Entries
 * Each Generic Data Entry is identifiable by its Section Type field,
   and the data structures associated are also in the UEFI spec.
     * The GUIDs are listed in the Section Type field of the CPER
       Section Descriptor structure.  BERT doesn't use this structure
       but simply uses its GUIDs.
     * Data structures used in the Generic Data Entry are named as
       Error Sections in the UEFI spec.
         * Some sections may optionally include a variable number of
           additional structures, e.g. an IA32/X64 processor error
           can report error information as well as machine contexts.

It is worth noting that the Linux kernel (as of v4.4) does not attempt
to parse IA32/X64 sections, and opts to hexdump them instead.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I54826981639b5647a8ca33b8b55ff097681402b9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28470
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:50:02 +00:00
Marshall Dawson 03b99772f7 include/cper.h: Add max of enum
Define the maximum value of the cper_x86_check_type enum, for use later
in determining a legal function argument.

Change-Id: I73df4c6daa5d232c2d38b0896442b5bcab5aa15f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28533
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:49:51 +00:00
Mikolaj Walczak fad5395879 wedge100s: Add TPM support
Change-Id: Id7e8ad63de2a6094c66cbd47ae9b7707a9af4e81
Signed-off-by: Mikolaj Walczak <mwalczak@fb.com>
Reviewed-on: https://review.coreboot.org/28529
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 10:59:58 +00:00
Okash Khawaja dd5411a8b1 fsp_broadwell_de: enable spi console
this enables spi console for wedge100s with broadwell_de. the console
size is 64kb. enabling spi console in `board.fmd` enables code which
calls into `timer_monotonic_get` (from `spi_flash_cmd_poll_bit`) and
`udelay` (from `ich_status_poll`). this patch selects `TSC_CONSTANT_RATE`
in fsp_broadwell_de's Kconfig to satisfy that.

Change-Id: Ib925c5aee88b65c46a81534405c364dd5649f8e8
Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com>
Reviewed-on: https://review.coreboot.org/28528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-07 10:25:52 +00:00
Furquan Shaikh 2d602098f9 mb/google/octopus: Configure H1 interrupt pad using Rx level config
This change configures GPIO_63 (which is used for H1 interrupts) as Rx
Level. This ensures that the signal gets passed on to the next logic
state as is and the APIC entry can be configured to trigger interrupt
on level or edge as per the kernel driver expectation.

TEST=Verified that no H1 interrupt timeouts are seen with 100
iterations of warm and 100 iterations of cold reboot.

Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06 22:45:23 +00:00
Michael van der Westhuizen 401f8c59bd qemu-q35: Use the TSC for udelay
Use the TSC for delays on q35, ensuring that the TSC delay code is
included in the correct stages when selected.

Tested on qemu-35 and wedge-100s (for no regressions).

Change-Id: I3f8368509807974bfcf2a0fcff7a4aa21adf47ed
Signed-off-by: Michael van der Westhuizen <rmikey@fb.com>
Reviewed-on: https://review.coreboot.org/28526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-06 16:31:10 +00:00