While FORCE_PWR is set high, it prevents retimer from entering low power
state. S0ix failure occurs while USB4 Gatkex is connected on Port-0.
This change sets FORCE_PWR(GPP_H10) low. This FORCE_PWR GPIO will be
toggled by kernel through DSM method while updating retimer firmware.
BUG=b:174166586
Cq-Depend: chromium:2594438
TEST=Verifed s0ix cycles with USB4 Gatkex connected on Port-0.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ie4b442e1078379c522a94bfdc00cd99e6f9b8170
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin
board. This update configures these USB2 ports for Type C which will
allow USB2 port reset message upstream from PCH to CPU to recover a USB3
device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892
TEST=Booted to kernel on Delbin board and verified usb2 port reset
message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE
where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4.
Validated various USB3 devices enumeration.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49202
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add memory table to "mem_list_variant.txt", and command to generate files:
go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/copano/memory/ src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt
DRAM Part Name ID to assign
MT53D512M64D4NW-046 WT:F 0 (0000)
H9HCNNNCRMBLPR-NEE 0 (0000)
MT53D1G64D4NW-046 WT:A 1 (0001)
H9HCNNNFBMBLPR-NEE 2 (0010)
BUG=b:175896481
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot
Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Change-Id: I2ace17e8fff12d3f5de15a35f609265d8b6ed6b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48948
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make CHROMEOS_DSM_CALIB depend on CHROMEOS, rather than force-select it.
Change-Id: I4c3fd04ec00e0787381c58810938dd48f414635c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
On Voema port 0 (MB PORT) does not have a retimer so the port needs
to be configured for the SOC to handle Aux orientation flipping.
BUG=b:176462544
TEST=tested on voema
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
This patch add SSD D3 cold support for lindar.
BUG=b:172405687
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ie343bbff3bde4ff2a7e89bd384d5661af372b560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable Runtime D3 for the volteer variants that have GPIO power control
of the NVMe device attached to PCIe Root Port 9.
Enable the GPIO for power control for variants that do not already have
it configured to allow the power to be disabled in D3 state.
BUG=b:169356808
TEST=tested on voema
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I28ef074225c533e1a97b6ec4a1a5dd1dcc198168
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48848
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Runtime D3 for the volteer variants that have GPIO power control
of the NVMe device attached to PCIe Root Port 9.
Enable the GPIO for power control for variants that do not already have
it configured to allow the power to be disabled in D3 state.
BUG=b:161270810
TEST=tested on eldrid
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I941c8a9bb3221ad90528c323cd0f267dc77d2af3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Move the manual calls to fw_config_probe() into the devicetree; the
AUDIO probe is trivial, and the TCSS devices (DMA0, iTBT RP0 & RP1) are
already guarded with probe statements in the baseboard devicetree, so
the code in romstage.c was redundant. The variants seem to have their
USB4 probe statements correct as well, so the manual UPD setting in
mainboard.c was also unnecessary.
BUG=none
TEST=abuild google/volteer
Change-Id: I1d067ff3d181b152c784634ff99202bb2b9202f7
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In cases when a volteer device is unprovisioned, the safest thing to do
for GPIOs that will normally be used for audio codec buses is to leave
them disabled (configured as PAD_CFG_NC). This patch adds support for
that.
BUG=none
TEST=add debug print to new if branch; remove fw_config from CBI and
see print on console
Change-Id: I8efd101174f6e3d7233d2bf803b680673cada81a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47972
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct IOM setting and TCSS AUX setting to fix type C C0 port display can't output after flip.
BUG=b:173093980
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS, test USB function normally.
Change-Id: I827a2d8a5b01dce412b4170fde0f638670ab8baf
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
BT_DISABLE_L (GPP_A13) has to asserted in early_gpio_table to reset
bluetooth on reset.
BUG=b:171085081
TEST=volteer2 boots; scope shows assertion of the signal
Change-Id: Iaa5799e9cab69c074b7920604c8a6c85ad07358a
Signed-off-by: Alex Levin <levinale@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Commit b0e169ac85 included a few small omissions and typos when
converting 'device pci xx.y' to 'device ref blah' after adding the new
chipset.cb file for TGL. This patch fixes these errors:
1) MIPI camera support requires I2C2 & I2C3 enabled
2) Malefor SAR sensor is on I2C2, not I2C3
BUG=b:175165653
TEST=abuild -p none -t google/volteer -x -a -c max
Change-Id: I577957d67f47bbe88bbc2535fb1cb5c8f7390438
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This change reorganizes FMAP for volteer to make use of the lower
16MiB of the SPI flash for RW_SECTION_A and RW_MISC in addition to
RW_LEGACY. This is now possible because TGL supports memory mapping of
BIOS region greater than 16MiB.
Following changes are made in chromeos.fmd as part of this:
1. Move RW_SECTION_A and RW_MISC to lower 16MiB.
2. Reduce size of RW_LEGACY to 2MiB since we longer need to use it as
a placeholder in the lower half of the SPI flash.
3. Reduce size of RW_ELOG to 4KiB as coreboot does not support a
larger region for ELOG.
4. Increase WP_RO to 8MiB to allow larger space for firmware
screens. GBB size is thus increased to 448KiB.
BUG=b:171534504
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I0c3c0af94183a80c23d196422d3c8cf960b9d9f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch adds the PMC MUX and CONx devices for lindar. Device
specific method contains the port and orientation details used
to configure the mux.
BUG=b:172533907
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Id5ee78b7ece8421144086af9b95f5f0d849be56c
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Update lindar gpio settings for Synaptics trackpad no function issue.
Update I2C5 bus freq to 400kHz.
Improve Goodix Touchscreen power on sequence.
BUG=b:160013582
BRANCH=firmware-volteer-13521.B
TEST=emerge-volteer coreboot and check system dmesg and evtest can get
device. Verify trackpad function workable.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I8c1ab6bab1f9de187e2a78ead7b5bbaf758f5fcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Unique among the Volteer devices, the volteer2_ti50 variant connects to
the TPM via I2C. This CL introduces the proper devicestree declarations
for the Linux kernel to recognize that.
overridetree.cb is shared between "sub"-variants volteer2 and
volteer2_ti50, so both will have two TPM nodes, the I2C being disabled
by default. The odd _ti50 variant then has code in variant.c to enable
the I2C node and disable the SPI node.
BUG=b:173461736
TEST=abuild -t GOOGLE_VOLTEER2{_TI50,} -c max -x
Change-Id: I5576a595bbabc34c62b768f8b3439e35ff6bcf7b
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48223
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update Power Limit2 (PL2) minimum value to the same as maximum value for
volteer variants like baseboard, delbin, eldrid, terrador and todor.
All other variants uses the DTT entries from baseboard devicetree since
there is no override present for those variants. DTT does not throttle PL2,
so this minimum value change here does not impact any existing behavior on
the system.
BUG=None
BRANCH=volteer
TEST=Build and test on volteer system
Change-Id: I568e87c87ef517e96eaab3ff144b1674d26ae1e6
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
refer to cb:45878
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices
can be hooked up together via devicetree aliases.
BUG=b:174735512
BRANCH=volteer
TEST=build and type-c display work
Change-Id: I0bf84e2691856c9760d8fa9b6d853b04be10390a
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48268
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the copano variant of the volteer reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.3.1).
BUG=b:174413884
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_COPANO
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ib06625f492f68a6a6f5c6b382772b68f1eb681ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
According to the spec provided by Bayhub, the 3.3V power rail must be enabled at least 100ms before reset is released.
To ensure this, set the power enable signal in the bootblock GPIO table.
BUG=b:173676531
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS, test USB function normally.
Change-Id: I0c536f36c138ace93766f3024f6ec5d47b38269f
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47799
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the fw_config entries for the newly added boot device fields.
These are added as separate fields since a board may have more
than one selected.
BUG=b:173129299
TEST=abuild google/volteer
Change-Id: I2af9ffcf0b90d4f4b7f2f31613ee110d8f350454
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The initial commit only focused on GL9755S and RTS5261, but there
were recently other cards added to the fw_config and those also
need to be added to the probe lists.
BUG=b:173207454
TEST=abuild google/volteer
Change-Id: Ic27074a016ffbd4c4dd86104a6d85437357c4b82
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Create the drobit variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:171947885
BRANCH=none
TEST=emerge-volteer coreboot
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I63b7312bba236bd5af028359804d042f6850d8ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47787
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec.
This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring
the bus frequency closer to 400kHz.
BUG=b:173670150
TEST=Verified that I2C5 frequency is between 386-387kHz.
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47736
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices
can be hooked up together via devicetree aliases.
BUG=b:172528109
BRANCH=firmware-volteer-13521.B
TEST=built and USB3.0, type-c display work.
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: Iedf9b972b341064ff62a4443bfa83f69c8c60108
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48066
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
update the DPTF parameters received from the thermal team.
BUG=b:167523658
TEST=emerge-volteer coreboot
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Iafc3fb389ade5cfec79a816a28880262bdce7c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47858
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A new field was defined for different keyboard layouts, so add this field
to the list and provide the two options that were defined.
Change-Id: Ic357446725e34221040705929d54cbce94c5ab8b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Set the default state of the TCSS PCIe RP0 to hidden so that coreboot
does not allocate resources to this hotplug root port. The default
behavior on the reference design is that there is only one USB4 port
attached to port C1 while port C0 is only a USB3 port.
Meanwhile the Voxel and Terrador variants do have USB4 on both C0 and
C1 ports, so these boards change the default to 'on' so that coreboot
does allocate resources for the hotplug port.
BUG=b:159143739
BRANCH=volteer
TEST=build volteer and voxel and check the resulting static.c to
ensure the device is hidden or not. Also boot with the two different
configurations and ensure resources are assigned or not. Finally
check that S0ix still functions with the C0 port set to 'hidden'
after authorizing a PCIe tunnel on port C1.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I8bb05ae8cd14412854212b7ed189cfa43d602c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47198
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
