Commit Graph

22683 Commits

Author SHA1 Message Date
Richard Spiegel 9305704454 src/mainboard/google/kahlee: Remove legacy tables
Remove IRQ and MP tables. Modern OS use ACPI instead of legacy tables.
Use Kconfig for reversable configuration if using old OS.

BUG=b:62241143

Change-Id: I5fc833c8af47b5f6fad757e129250e6202810dbb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-16 01:32:28 +00:00
Youness Alaoui b6b1b237eb console/flashconsole: Enable support for postcar
If FSP 2.0 is used, then postcar stage is used and the flashconsole
as well as spi drivers needed to be added.

Change-Id: I46d720a9d1fe18a95c9407d08dae1eb70ae6720e
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16 00:21:49 +00:00
Piotr Król f57f1310c5 util/docker: add nasm to fix tianocore payload compilation
This patch address problem with Tianocore compilation in coreboot-sdk
container. Without it compilation fails asking for nasm installation.

Change-Id: I546f9d42b380799d1cd80a70f33be2a768745080
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-16 00:20:27 +00:00
Kane Chen 6708d3abc7 mb/google/fizz: enable AER for PCIe root ports
Enable PCIe Advanced Error Reporting for PCIe
root port 2, 3, 4 ,8.

BUG=b:64798078
TEST="lspci" shows that AER is enabled in the capabilities list.

Change-Id: I6438250d674e7d06cdecd8f25fadebca1973721e
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21946
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16 00:20:07 +00:00
Shaunak Saha ec1a24ca02 src/soc/skylake: Fix Null pointer dereferences
Fix bug detected by coverity to handle the NULL pointer dereference

Coverity Issues:
* 1379849
* 1379848

TEST=Build and run on skylake platform

Change-Id: Iec7a88a03531bbfeb72cedab5ad93d3a4c23eef5
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21909
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-16 00:19:44 +00:00
Naresh G Solanki f329f0c3af intel/common: CAR setup CQOS
Enable CQOS on Geminilake.

In Apololake, CBM_LEN is 0x7. Whereas the same in Geminilake is 0xF.

Thus get CBM_LEN using cpuid instruction & generate CBM_LEN_MASK.

Later use the CBM_LEN_MASK when writing to IA32_L2_MASK_* to set right
bits.

BUG=None
TEST= Build for Geminilake platform i.e., glkrvp & check for successful
CAR setup. Even verified the same on APL platform i.e., on Reef

Change-Id: Ic736dba1a46629ff5bf3183082799c0c1468e6d9
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com
Reviewed-on: https://review.coreboot.org/21701
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-16 00:16:53 +00:00
Frank Vibrans 7151778847 soc/amd/common: Clean up file includes
Remove unnecessary header file includes.

Change-Id: I9ad9e86f3c75903e278e898602caec04351f64b6
Signed-off-by: Frank Vibrans <frank.vibrans@scarletltd.com>
Reviewed-on: https://review.coreboot.org/21989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16 00:13:23 +00:00
Kamil Wcislo c5d3944ad5 mainboard/pcengines/apu2: use GENERIC_SPD_BIN
Use GENERIC_SPD_BIN method of adding the SPD bins to final rom.

Change-Id: I242e393bafac41aa7743f83b52cadf027019ee6e
Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-16 00:13:03 +00:00
Marshall Dawson a5f225f288 soc/amd/stoneyridge: Check UART index
The Stoney Ridge APU has only two internal UARTs.  Add checks for
invalid settings.  When enabling the UART, return if the console is
on any UART not equal 0 or 1.  The base address returned is 0 if an
invalid configuration is used.  All callers check the return value
before using the returned value.  Finally, provide an assert at the
earliest availability of the console to get the notice into the
cbmem console.

BUG=b:62201567
TEST=Build with UART = -1, 0, 2.  Inspect objdump and boot to OS.
     Build without ST UART and inspect with objdump.

Change-Id: I9432571712bae15a604f4280ea5e0f81fd68604d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16 00:12:48 +00:00
Marshall Dawson 78130663e5 drivers/uart8250mem: Check for zero base address
Before adding a new UART to the coreboot/lb table, verify that it
has a non-zero base address.  This is consistent with all other
functions that use the uart_platform_base() function.

This was tested on google/kahlee by using an invalid UART number
and forcing the base address to 0.  Execution was able to complete
through depthcharge and into the OS.

Change-Id: I6d8183a461f0fedc254bf88de5ec96629a2a80ef
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21996
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16 00:12:35 +00:00
Martin Roth 30f9b953a8 soc/amd/stoneyridge: Update AMD firmware placement options
- Don't force the selection of placing the firmware outside of cbfs
when using vboot.
- Set a prompt to allow the option of placing it outside of  cbfs.
- Leave all Kconfig defaults the same.
- Place the AMD firmware directory table in the specified location
even when using the 'outside of cbfs" option.
- Print where the firmware is being placed when placing it outside
of cbfs.

BUG=b:65484600
TEST=Assign PSP firmware location, build & test.  Firmware shows up
inside CBFS.  Set 'outside of cbfs' option, verify firmware gets
written to the correct location.

Change-Id: Ia8258b5c2ecfaaa42d623e3376ec3233115aed58
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21867
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-16 00:11:46 +00:00
Martin Roth fc9d5011a9 src/mainboard/kahlee: Default AMD FW position to 1MB
For Kahlee, the AMD firmware directory should be in the 1MB location
so that it's in the RO cbfs section.

BUG=b:65484600
TEST=Build & boot

Change-Id: I650d8bc0bfa773f5fb5dc11167fe3db3b9550b68
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22003
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-16 00:11:37 +00:00
Paul Menzel 95c4aa5121 arch/x86/gdt: Correct format of multi-line comment
Change-Id: I87148315cdf7e420eac2f3f680251f8e963a9707
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-10-16 00:10:33 +00:00
Kyösti Mälkki 1d24b96310 amd/inagua: Drop unused Broadcom 5785 support code
Remove sample configuration code for internal
Broadcom GbE device in AMD A55E aka Hudson-E1.

Change-Id: Ib0262805aafc62513d9237019ade473cb1efbf1c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15 23:44:58 +00:00
Marshall Dawson 813462ec31 amd/stoneyridge: Add function to find PmControl register
Find the PmControl register's I/O address by checking the hardware in
PMx62.  Don't rely on the address being the coreboot default.  PmControl
is the first register in the AcpiPm1CntBlk.

Change-Id: Ibb608dcaa7801af067d6edd86f92c117c2ac08a6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-15 23:43:27 +00:00
Marshall Dawson f8bf9a7eaa google/kahlee: Add SMI sleep handler
Notify the EC the system is going to sleep.

Change-Id: I025e268a4f806d827348d91effff43a6a339a148
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-15 23:43:21 +00:00
Marshall Dawson 79df1fb090 google/kahlee: Add SMI apmc handler
Forward the apmc call to the chromeec.

Change-Id: Id724c1abf15617ad1ba28f2c0247455b014c1867
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-15 23:43:17 +00:00
Marc Jones 7e710e047f amd/soc/common: Print an error if an AGESA callout isn't supported
Let the developer or user know that a callout isn't supported.

Change-Id: I73a6c6930a6661627ad76e27bbb78be99e237949
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21998
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15 22:33:37 +00:00
Matt DeVillier f4dc596a38 google/wizpig: add new board as variant of cyan baseboard
Add support for google/wizpig (white label Chromebook) as
a variant of the cyan Braswell baseboard.

- Add board-specific code as the new wizpig variant
- Add new shared SPD file to the baseboard

Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)

Change-Id: I424d2256eb79ca3ea0a62620954c57c09ae0c0b2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15 22:23:18 +00:00
Matt DeVillier 94bc265b64 google/ultima: add new board as variant of cyan baseboard
Add support for google/ultima (Lenovo Yoga 11e G3) as
a variant of the cyan Braswell baseboard.

- Add board-specific code as the new ultima variant

Sourced from Chromium branch firmware-ultima-7287.131.B,
commit 3ef9e73: Revert "Revert "soc/intel/braswell: Put SERIRQ in quiet mode""

Change-Id: Ib38b110f50f4d6ae6eda40e787cd3c1c8dd5ece7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-10-15 22:23:05 +00:00
Matt DeVillier 81b5bde7e4 google/setzer: add new board as variant of cyan baseboard
Add support for google/setzer (HP Chromebook 11 G5) as
a variant of the cyan Braswell baseboard.

- Add board-specific code as the new setzer variant
- Add new I2C touchscreen device and SPD files to the baseboard
for potential reuse by other variants

Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)

Change-Id: Ibcebebeb469c4bd6139b8ce83a1ca5ca560c2252
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15 22:23:01 +00:00
Richard Spiegel aa1838577d soc/amd/stoneyridge/lpc.c: Refactor lpc_enable_childrens_resources
Factor out the code into separate functions.

Create set_lpc_resource that will set the resource for a particular child while
lpc_enable_childrens_resources finds all children and calls set_lpc_resource
for each child found. This creates well defined boundaries for each function.

Change-Id: I265cfac2049733481faf8a6e5b02e34aadae11f5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-15 22:10:02 +00:00
Michał Żygowski 1a81a4d135 pcengines boards: Update board_info files
This updates board info of PC Engines platforms, changes board names
to official manufacturer's names and adds info about ROM. Removing 
"Clone of" option for ALIX platforms makes them independent.

Change-Id: Ie76d65ea84f14b9043a8e5b86678a9da4c187cc9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15 21:37:24 +00:00
Paul Menzel 38a906b0e1 util: Make TZ environment variable POSIX compatible
`TZ='UTC'` is not a portable setting for the TZ environment variable.
POSIX says you’re supposed to use something like `TZ='UTC0'` instead.
Although `TZ='UTC'` works when GLIBC is used, this is not necessarily
true on other POSIX platforms. [1][2]

[1] http://lists.alioth.debian.org/pipermail/reproducible-builds/Week-of-Mon-20170918/009289.html
[2] http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/V1_chap08.html#tag_08_03

Change-Id: I1dca0b84de0ec0af3a103e2cbbf731512eb59497
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/21721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-14 11:28:14 +00:00
Damien Zammit fe5030eceb biostar/a68n_5200: Fix hang with board due to SPI
SPI mode needs to be set early to normal and Quad I/O disabled
on this board for some reason

Change-Id: I4dbc52010eebf492087d0b1c155a24a307bcc8b0
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-14 08:02:16 +00:00
Damien Zammit b93fb1ab16 biostar/a68n_5200: Do actual port
TESTED on Biostar A68N-5200: boots to GNU/Linux

With proprietary VBIOS, even the gfx works in SeaBIOS.

Change-Id: Id44b81345ba189f82413042760d570a746294a1e
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-14 08:01:51 +00:00
Damien Zammit d2b5b734e8 biostar/a68n_5200: Clone amd/olivehill
Altered Kconfig board names to make it pass lint

Change-Id: I9ccfe014a0e3a70148463fc9f8de02b500fac69e
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-14 08:00:34 +00:00
Youness Alaoui 66030fa5ab intel/skylake: Use Sata related registers from devicetree
Enable the use of the SataPortsEnable and SataPortsDevSlp registers
which were being ignored from the devicetree and were not affecting
the resulting UPD parameters.

SataPortsEnable was only being copied for the first SATA port, while
the other ports were left ignored.

Change-Id: Iae70a4d6375fa5d1b05ee89f6b97c65dbbf28dda
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-14 00:25:08 +00:00
Marc Jones 43a285f983 google/kahlee: Add AGESA_DO_RESET in bootblock
Support the required AGESA_DO_RESET in bootblock.

BUG=b:64719937
BRANCH=none
TEST=Check AGESA reset request in booblock does a reset in the serial
console or ec console.

Change-Id: I462a1f81b8d209c15417946a314f2bfb9b226e4d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13 16:48:49 +00:00
Marc Jones 4f886cc19a amd/stoneyridge: Make all AGESA reset requests immediate
The AGESA RESET_WHENEVER request were never doing a reset in coreboot.
We don't have a way to collect a whenever and reset at some later time,
so just do the reset immediately.

BUG=b:64719937
BRANCH=none
TEST=Check AGESA reset request in booblock does a reset in the serial
console or ec console.

Change-Id: If2654ec0c5c5dbdcea6fc9374371c3388d29fdc7
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21978
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-13 16:48:33 +00:00
Shelley Chen 3918887c18 google/fizz: Enable cr50 over SPI
We are changing the bootstraps in the EVTs so that the SOC
communicates with cr50 over SPI instead of cr50.  SPI is more reliable
than I2C.  Thus, disabling cr50 over I2C and enabling cr50 over SPI.

BUG=b:65056998, b:62456589
BRANCH=None
TEST=make sure that we can boot into kernel
     run cold_reset and warm_reset and make sure both
     boot successfully.
CQ-DEPEND=CL:714237

Change-Id: I85b9a61f0305e3c7ccada79d7702234a285a6d2a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-13 16:29:20 +00:00
Aamir Bohra 2188f57a80 src/device: Update LTR configuration scheme
This patch moves out LTR programming under L1 substate
to pchexp_tune_device function, as substate programming
and LTR programming are independent.

LTR programming scheme is updated to scan through entire
tree and enable LTR mechanism on pci device if LTR mechanism
is supported by device.

BRANCH=none
BUG=b:66722364
TEST=Verify LTR is configured for end point devices and max
snoop latency gets configured.

Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/21868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-13 15:21:48 +00:00
Matt DeVillier c8374e3292 google/relm: add new board as variant of cyan baseboard
Add support for google/relm (white label Chromebook) as
a variant of the cyan Braswell baseboard.

- Add board-specific code as the new relm variant
- Add new shared SPD files to baseboard

Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)

Change-Id: Ife10f5f75435f356cd896588dd6f425e54f3c88e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-10-13 15:19:55 +00:00
Matt DeVillier 35213664cf google/kefka: add new board as variant of cyan baseboard
Add support for google/kefka (Dell Chromebook 11 3180) as
a variant of the cyan Braswell baseboard.

- Add board-specific code as the new kefka variant
- Add new shared SPD file to baseboard

Sourced from Chromium branch firmware-strago-7287.B,
commit ef41a46: Kefka: Modify USB2 settings to match the eye diagram

Change-Id: Ic6c8c5e5b6029bb99039c64b0182214e93552fa2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13 15:19:44 +00:00
Patrick Georgi 9681cdc1b4 util/crossgcc: Add bootstrap-only mode
buildgcc -B (--bootstrap-only) builds only a bootstrap compiler. That
useful if you want to package the cross compilers: first build the
bootstrap compiler, then all required cross compilers in a separate
directory (using the bootstrap compiler through an adjusted PATH).

Change-Id: I089b51d1b898d4cf530845ba51283997fd229451
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-13 14:51:41 +00:00
Matt DeVillier d6735b0f14 google/cyan variants: fix non-functional typo in gpio.c
Typo found/fixed in to-be-merged boards; applying same fix to
already-merged boards.

Change-Id: I15f97467a5442888165399be997b0b690a3c312a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13 14:30:27 +00:00
Matt DeVillier a34cf52469 google/cyan variants: fix single/dual channel reporting
Fix typos in determining single/dual channel in cyan variants
which resulted in all boards being reported as 4GB/dual channel
in the cbmem console log.
These typos were found and fixed in yet-to-be-merged variants;
this patch applies the same fixes to already-merged boards.

Change-Id: I615463668e77bd817d5270f0f04d4d01f74e3b47
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13 14:30:21 +00:00
Martin Roth 8a02727f50 Makefile: Exclude util directory from project_filelist
This list should be about files included in the ROM output, not related
files.

Change-Id: I390d58ef9ab76ff05062b5fbc1e031b7c6d2f388
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-10-13 14:29:35 +00:00
Patrick Rudolph f6aa7d94c8 nb/intel/*/gma: Port ACPI opregion to older platforms
Port the ACPI opregion implementation that resides in
drivers/intel/gma to older platforms.

It allows to include a vbt.bin and allows GNU/Linux to load the
opregion as ASLS is being set.

Windows' Intel will likely ignore it as it relies on legacy VBIOS
to be loaded at 0xc0000.

Tested successfully on DG43GT (x4x) with vbt.bin,
with X200 (gm45) with vendor option rom and
D945GCLF (i945) with fake vbt.

Change-Id: I1896411155592b343e48cbd116e2f70fb0dbfafa
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-13 05:19:03 +00:00
Matt DeVillier 53e4195625 drv/intel/gma/opregion: Add common init_idg_opregion()
Add a new common method to initialize ACPI OpRegion.
* Try to locate vbt.bin in CBFS.
* Try to locate VBIOS in CBFS.
* Keep existing code to probe at 0xc0000.

Tested on Lenovo T430 (sandybridge) using vbt.bin, tested using buggy
VBIOS with wrong vbt_offset, tested with fake vbt written by NGI at
0xc0000.

Tested with https://review.coreboot.org/#/c/21766/ on i945 (using fake
vbt at 0xc0000), x4x (using vbt.bin) and gm45 (using vendor VBIOS).
In all cases linux was successfully provided with VBT from ACPI
opregion.

Change-Id: I8ee50ea9900537bd9e3ca5ab0cd3f48d2acec970
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-13 05:17:45 +00:00
Furquan Shaikh 74145f7615 intel/common/pmc: Disable all GPEs during pmc_init
If GPEs are not cleared during pmc_init, it could result in issues if
standard wake events are generated while coreboot is
initializing. e.g. (Observed on soraka):
1. Suspend to S3
2. Lidclose
3. Lidopen
4. EC wakes up the host using WAKE# pin
5. On wakeup, pmc_init occurs which does not clear GPEs
6. MP init enables SMI
7. In order to add wake event to elog, coreboot sets wake mask on the
EC, which causes the EC to assert WAKE#.
8. Since WAKE# is asserted, it results in an SMI#. However, EC does
not de-assert WAKE# until host queries and clears the host event
bit (which does not happen since coreboot is stuck in handling the
SMIs).

This is one of the issues that can occur when GPEs are unnecessarily
enabled in coreboot. Before the move to PMC common library, SKL PMC
driver set all GPEs to 0 and hence this issue did not occur.

This change explicitly disables all GPEs during pmc init in order to
avoid any side-effects.

BUG=b:67712608
TEST=Verified that device resumes fine using lidclose/lidopen to
suspend and resume.

Change-Id: Ic5be02a23a8dbf43c4d7adf00251639ded4a94c9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21969
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12 22:13:42 +00:00
Furquan Shaikh c4e652ff57 soc/intel/common: Clean up PMC library GPE handling API
1. Update gpe handling function names to explicitly mention if they
are operating on:
 a. STD GPE events
 b. GPIO GPE events
 c. Both
2. Update comment block in pmclib.h to use generic names for STD and
GPIO GPE registers instead of using any one platform specific names.

BUG=b:67712608

Change-Id: I03349fe85ac31d4215418b884afd8c4b531e68d3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21968
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12 22:13:39 +00:00
Martin Roth bbd5ee4187 vboot: Exclude platform specific files from RW cbfs
Add a Kconfig option to allow platforms to exclude specific files
from being copied from RO into RW sections.

BUG=b:65484600
TEST=Exclude apu/amdfw from the RW cbfs sections

Change-Id: I7723b63392c1620b75ceb6d8e25fe1ce2c75cf18
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-12 18:33:42 +00:00
Bora Guvendik 630b644cec soc/intel/cannonlake: add length information for communities
TEST = Boot to OS, check if pinctrl probed successfully

Change-Id: Ib20c955d535cd9c48175b4d3934b4699b6186874
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-12 18:26:52 +00:00
Vaibhav Shankar b4e275f97b mainboard/intel/cannonlake_rvp: Add Sleep states
Add sleep state to DSDT table.

Change-Id: Ic14e34e29d5f881949765dee5c6b433c1499c491
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/21976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-12 18:26:38 +00:00
Vaibhav Shankar 4df1c4cedb soc/intel/cannonlake: Add ACPI platform sleep capability
Add the required ACPI sleep states

Change-Id: I7750062554f087e4f88da56790e4122d5fa20529
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/21975
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-12 18:26:33 +00:00
Richard Spiegel 63300f7292 soc/amd/stoneyridge: Clean up sata.c
Clean up ahci_ptr declaration. Remove incorrect PCI device IDs.

BUG=b:62200375

Change-Id: I9058d9102fc8ea0bd03ea089ba98da4590dd3533
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21973
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12 16:33:20 +00:00
Werner Zeh c0d1e31617 siemens/mc_bdx1: Add delay to wait for legacy devices
Like happend in commit efd0eb35af
(siemens/mc_apl1: Add delay to wait for legacy devices) add the
feature to mc_bdx1 as it uses the same legacy devices.

Change-Id: I355a53ce7aea70098d7bc08f24dc6a4e43d1d618
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-10-12 16:20:56 +00:00
Werner Zeh 0ccc3c49e4 intel/fsp_broadwell_de: Add timestamp functionality
Add a little code to enable timestamps on FSP based implementation
of Broadwell-DE. I have tested it by reading back the timestamps
with cbmem utility once the board has booted into Lubuntu.

Change-Id: Idaa65a22a00382bf0c37acf2f5a1e07c6b1b42d9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-12 16:20:50 +00:00
Arthur Heymans 0315b6740a sb/amd/sb700/lpc.c: Optimize code flow for less indentation
This changes the code flow so less indentation has to be used.

This also changes some lines to limit their length.

Change-Id: I50ca99a759a276e9d49327c6ae6c69eeab2a8c90
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21234
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12 08:08:22 +00:00