Commit Graph

11316 Commits

Author SHA1 Message Date
Edward O'Callaghan 3e570d4ca5 AGESA f14: Add "const" modifiers
Apply commit 283ba78415 to f14 (literally, plus one adaptation).

Change-Id: Ieea47470e5852ec8a46596ce23a2d18444618624
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7361
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-10 08:01:21 +01:00
Patrick Georgi c32b4a40d2 abuild: pass compiler configuration options to tool building step
This is required to run abuild parallely with clang
without the canonical coreboot toolchain installed.

Change-Id: Iea56d3f552d50ab6e762afa134091b0d8e38792c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7369
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-09 22:46:47 +01:00
Felix Held fac95e3bfe inteltool: add more hardware IDs and PCIEXBAR/PXPEPBAR read support
Add IDs of some SNB and Haswell chips; use more descriptive names.
Add PCIEXBAR and PXPEPBAR read support for SNB/IVB/Haswell.

Change-Id: I16753bf90061fc2065b813b1c2169e7b7bcc89e8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/7360
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
2014-11-09 21:11:27 +01:00
Gabe Black a6aecc41ef libpayload: serial: Move the depthcharge serial drivers into libpayload.
These drivers need to be ready right away and never really fit into the
depthcharge driver model anyway.

CQ-DEPEND=CL:194063
BUG=None
TEST=Built and booted on nyan and peach_pit. Built for nyan_big, nyan_blaze,
and daisy.
BRANCH=None

Original-Change-Id: I9570dee53c57d42ef4cd956f66a878ce39a2dc20
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/194057
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 26e18f680c93fc990a3d1057c164f19859634a9f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ia2233e2bd821d8de8d2d57a9423aeb74be7efd93
Reviewed-on: http://review.coreboot.org/7224
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2014-11-09 13:39:11 +01:00
Vladimir Serbinenko d1069e0a40 sch: Move to implicit length patching
Change-Id: I057e7d30fa3c661e83db09e27278ce9f0bec69d4
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7330
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-09 12:55:13 +01:00
Edward O'Callaghan 48b6b97eb4 src: Too many terminators ';;' at end of stmts, stop Skynet
Change-Id: I3e9b7e0e5558a6942067dcea04b83fe3bccbbaf9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7362
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09 12:26:34 +01:00
Patrick Georgi 27cf24727c car globals: add "used" attribute
Otherwise clang feels free to optimize away that variable
(somewhat) and revive it in a different form inside .bss.

They probably have the language lawyery excuse for why
that's perfectly legal, so let's play it safe.
(relevant URL, sorry ron: http://llvm.org/bugs/show_bug.cgi?id=9520)

Change-Id: I603312ceea7207088dd29453cc8fb8f48c31af21
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7357
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-09 12:25:58 +01:00
Vladimir Serbinenko 5560188849 i945: consolidate sb & nb early inits
Change-Id: I00c2c725de5b982a5e4f584b77b09017a5bc0a72
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7062
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-11-09 04:56:11 +01:00
Vladimir Serbinenko 385743acbc i945: Consolidate common GNVS init
Change-Id: Idc3522807b17e56bdaf8f04b4bd68c6ed9777363
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7110
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-09 04:55:57 +01:00
Vladimir Serbinenko 39bbc8cb97 Kconfig: Hide DYNAMIC_CBMEM.
Only one setting actually works (exact value depends on board). So
no need to show it.

Change-Id: I2a85719264bbac07791ef6a9279590ba768c309e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7359
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-11-09 02:03:24 +01:00
Vladimir Serbinenko bcb3abe130 lenovo/wacom: Move to implicit length patching
Change-Id: Ica8a54ab215d09a2d2de93f316e3831ae4bfe5f5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7331
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-09 02:03:08 +01:00
Vladimir Serbinenko f7c75dbe07 i82801ix: Move to implicit length patching
Change-Id: I4027bc8c017901781ae56c7d3bd751bac50719f2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7329
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-09 02:01:43 +01:00
Vladimir Serbinenko 1bad88e6eb i82801gx: Move to implicit length patching
Change-Id: Idba0f33d231084d02392e23026f567c30f77b316
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7328
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-09 02:01:41 +01:00
Vladimir Serbinenko be0fd0a44f haswell: Move to implicit length patching
Change-Id: I662ba2a08f9a176a84b8318c8004aa5db7239567
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7327
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09 02:01:26 +01:00
Vladimir Serbinenko 226d784377 ibexpeak, bd82x6x: Move to implicit length patching
Change-Id: I43eef7f97398d7c4c3f8d9790920fa4402019dd7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7326
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09 02:01:21 +01:00
Vadim Bendebury b1709bd0b2 Provide ability to integrate with QComm SBLs
Ipq8064 SBLs initialize the hardware to prepare it to run an arbitrary
user provided bootloader. The only bootloader requirements imposed by
the SBLs are that it is concatenated with the SBL chunks in the
bootprm AND it uses MBN encapsulation (mostly to specify the size and
load address).

This patch adds configuration options to specify the location of the
SBL blobs and to require MBN encapsulation of the bootblock.

BRANCH=none
BUG=chrome-os-partner:27784
TEST=manual

  - the below demonstrates added encapsulation, no code run attempts
    have been made yet:

    $ FEATURES=noclean emerge-storm coreboot
    $ cd /build/storm/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999
    $ \od -t x4 build/cbfs/fallback/bootblock.bin | head -3
    0000000 00000005 00000003 00000000 2a010000
    0000020 00000be0 00000be0 2a010be0 00000000
    0000040 2a010be0 00000000 e32bf0df e59f0030

Original-Change-Id: Iae30ad08059e2b35c434ac25a410ac2017752957
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/193511
(cherry picked from commit bf16ea915c723ab124d817e3b0d950282e3cf1c1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I53c71d382ec1d826f530d7afb545f64ec4eaf96b
Reviewed-on: http://review.coreboot.org/7261
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-09 02:00:46 +01:00
Julius Werner 25a282dabc arm: Thumb ALL the things!
This patch switches every last part of Coreboot on ARM over to Thumb
mode: libpayload, the internal libgcc, and assorted assembly files. In
combination with the respective depthcharge patch, this will switch to
Thumb mode right after the entry point of the bootblock and not switch
back to ARM until the final assembly stub that jumps to the kernel.

The required changes to make this work include some new headers and
Makefile flags to handle assembly files (using the unified syntax and
the same helper macros as Linux), modifying our custom-written libgcc
code for 64-bit division to support Thumb (removing some stale old files
that were never really used for clarity), and flipping the general
CFLAGS to Thumb (some more cleanup there as well while I'm at it).

BUG=None
TEST=Snow and Nyan still boot.

Original-Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/182212
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 5f65c17cbfae165a95354146ae79e06c512c2c5a)

Conflicts:
	payloads/libpayload/include/arm/arch/asm.h
	src/arch/arm/Makefile.inc
	src/arch/arm/armv7/Makefile.inc

*** There is an issue with what to do with ramstage-S-ccopts, and
*** will need to be covered in additional ARM cleanup patches.

Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/6930
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-09 01:37:13 +01:00
Marc Jones a38ccfdee1 build: Add ccopts back into the build
The ccopts mechanism is needed for passing ARM assembler flags to GCC.
There are many gotchas in adding ASFLAGS. As things have moved
around, the revert doesn't remove cleanly, so this reverts and cleans
up the ccopts.

This reverts commit 25b56c3af5.

Change-Id: I44c025535258e6afb05a814123c10c24775a88e8
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7352
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-09 01:36:43 +01:00
Vladimir Serbinenko 430363ace7 acpigen: Add new function acpigen_pop_len
acpigen_patch_len doesn't really need its argument: length always includes
everything from length bytes to current pointer and never bytes before it.
Hence just infer all the info implicitly.

Argument is wrong in several places through the codebase but ACPI parsing
is lax enough to swallow incorrect SSDT. After this function is used throughout
the codebase, these issues will be fixed.

Change-Id: I9fa536a614c5595146a7a1cd71f2676d8a8d9c2f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7325
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2014-11-08 22:28:44 +01:00
Vladimir Serbinenko 689ddf6832 fsp_rangeley: Switch to per-device ACPI
Change-Id: Ic8b2204a6d08d63ac7f05836bf1424f1ca6ee50e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7046
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2014-11-08 20:12:31 +01:00
Vladimir Serbinenko 67bfbfdfeb ibexpeak: Move to common FADT
Change-Id: Ibb4dcc4356876f6385e79c10d8296fb680937827
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7201
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-08 13:42:05 +01:00
Vladimir Serbinenko 5b044ae607 bd82x6x: Move to common FADT.
Change-Id: I04ed600796c55f5af4f0a07687f676e6484a9830
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7200
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-08 13:41:48 +01:00
Edward O'Callaghan 986e85c098 intel: Use 'FORCEWAKE_ACK_HSW' define over '0x130044'
Change-Id: I1cf87b3c73d8bf8846e5870b19b089f85c299567
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7241
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-08 08:08:23 +01:00
Edward O'Callaghan 31cef1f46e device/dram/ddr3.c: Fix sizeof on array func param overflow
The sizeof on array function parameter will return size of 'u8 *'
instead of 'spd_raw_data' (aka 'u8 [256]' leading to an overflow.

Found-by: Clang
Change-Id: I78e113a640b2953c853eb43bd6874e4694260b1f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7353
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-11-08 07:09:34 +01:00
Marc Jones cfa06c7460 blobs: Update to IPQ blob commit
Update the 3rdparty repo to the IPQ binary commit

Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7354
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-08 01:05:03 +01:00
Edward O'Callaghan bf9d122ecd mainboard: Trivial - Make AGESA board include consistent
Change-Id: If6cb99469f56fff8f88b294b625f0a5205ec540b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7238
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-07 23:13:22 +01:00
Edward O'Callaghan 0d84a2c03e drivers/ioapic: DEVICE_NOOP some stub function callbacks
Just when you thought you found them all..
Reduces loc and makes NOP's explicit.

Change-Id: I416e0468b7f2f462c940daae695d67fb409aa4c6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7350
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-07 12:50:22 +01:00
Edward O'Callaghan 2014111786 drivers/net/ne2k.c: Collect headers and defines to top of file
Change-Id: I2ffb0dd9fe400132f6d430f115f962b5f8578efa
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7292
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-07 12:49:35 +01:00
Edward O'Callaghan e81b1f1699 cpu/intel/fsp_model_406dx: Invaild include path
Found-by: Clang
Change-Id: Iac54755caadc3ffbe8a09d40aed8500c2359e829
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7349
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-07 09:30:15 +01:00
Edward O'Callaghan 2837ab2cdf northbridge: DEVICE_NOOP some stub function callbacks
Reduces loc and makes NOP's explicit.

Change-Id: I8a117b150b8b421c7a18b48a2ac36d15679f20b0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7344
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-06 22:20:53 +01:00
Mathias Krause 5ad6ec55f8 inteltool: Fix message in case of multiple LPC controllers
If we find multiple LPC controllers, we want to tell the user that we'll
ignore all but the first. However, we use 'dev' in the message (the
current device found) instead of 'sb' (the one we want to use).

Fix the message by using 'sb' and break the loop right away in this
case. It's sufficient to tell the user once which LPC controller we'll
use.

Change-Id: Ibd27e40525fabe8c63b112691ad49fd994c70a48
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/7342
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2014-11-06 06:45:48 +01:00
Felix Held 0cc8f29316 inteltool: Add support for Sandy Bridge desktop processors
Change-Id: I5e68b89c30d5550e4bce5c3e4c7b0689c38756bc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/7337
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Mathias Krause <minipli@googlemail.com>
2014-11-06 06:44:29 +01:00
Edward O'Callaghan 5e1d34b19a mainboard/packardbell/ms2290: Missing romstage header
cpu/intel/romstage.h is needed so the the main() has a
prototype in freestanding.

Change-Id: I5e6afef82a4f63ab42927725adf3881084a1e25c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7235
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2014-11-05 21:28:25 +01:00
Edward O'Callaghan 3ec9c95d02 Use 'pci_devfn_t' over 'device_t' mixed type in 'reset.c'
Change-Id: I1a1412a1ee4125dcf1f01dc1f2ec6fd43b5d3c1f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7196
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-11-05 14:53:56 +01:00
Edward O'Callaghan 016732fec9 pci_ops.{c,h}: Don't hide pointers behind typedefs
Change-Id: I7cf7c236f94314d7970b19063d73db788c8267e5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7227
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-11-05 14:45:57 +01:00
Edward O'Callaghan 9a817ef183 soutbridge/*/bootblock: Use pci_dev_t over device_t typedef
Change-Id: I693b09d588ed6d56177cf86c23497231623b69c0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7193
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-11-05 14:41:47 +01:00
Gabe Black 169c0df6b8 ARM: Use local versions of libgcc functions instead of linking against libgcc.
The flags used to compile libgcc may make it incompatible with the code it's
linked against, and/or the hardware it's going to run on. Rather than try to
tease the right libgcc from the compiler, lets just leave it out and use our
own implementations of the necessary functions.

Most of these implementations were taken from the Linux kernel, except for
uldivmod.S which was taken from a CL originally written for U-Boot by
Che-Liang Chiou in December of 2010. It was modified to not use the CLZ
instruction on machines that don't have it, anything earlier than ARMv5. The
top block was taken from an earlier version of the same CL which didn't use
CLZ in that spot. The later block was written from scratch.

BUG=None
TEST=Built and booted into the bootblock on nyan. Ran a series of tests which
divided and modded a 64 bit value by various 32 bit values which were powers
of 2. Confirmed that this function was used and that the returned value was
correct. Printed decimal and hex versions of some values and verified that
they equaled each other. Built and booted on pit with serial enabled.
BRANCH=None

Original-Change-Id: I7527e28af411b7aa7f94579be95a6b352a91a224
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/172401
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit be8c7a8f3292a7d7651b7c6dafc9a2c53afbd402)

*** This second patch is cherry-picked and squashed again to
*** pick up the libgcc changes that were skipped previously.

arm: Move libgcc assembly macros to arch/asm.h

libgcc/macros.h contains some useful assembly macros that are common in
Linux kernel code and facilitate things such as unified ARM/THUMB
assembly. This patch moves it to a more general place where it can be
used by other code as well.

BUG=None
TEST=Snow still boots.

Original-Change-Id: If68e8930aaafa706c54cf9a156fac826b31bb193
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/182178
Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit a780670def94a969829811fa8cf257f12b88f085)

*** Additional changes for stage specific builds

Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie3e48f34ebf6fbe20c3dd76ecbcbea7844e9466e
Reviewed-on: http://review.coreboot.org/7322
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-05 01:49:06 +01:00
Vladimir Serbinenko 44bc11c3eb inteltool: Show more info on sandy/ivy.
Change-Id: I408614e743ab6f0f447b327c01d8f4dacf787124
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6692
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-05 00:02:25 +01:00
Vladimir Serbinenko ab83ef02c7 i82801gx: Handle whole FADT in southbridge.
Do all the handling in SB code with few parameters from devicetree.cb
instead of having mobo callbacks.

Change-Id: I8fd02ff05553a3c51ea5f6ae66b8f5502509e2bc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7199
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04 23:02:27 +01:00
Vladimir Serbinenko 9c4f1b8e05 inteltool/sandybridge: Kill mch_registers codepath.
It never worked.

Change-Id: Ic68614bb8ed481babf54b4f9d8db00635755f4d1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7324
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04 23:01:05 +01:00
Patrick Georgi 511f82398e abuild: fix cross compiler test
Actually abort if a cross compiler is missing, but also handle
subarchitectures (currently: armv4 and armv7 for arm)
properly.

Change-Id: Idf37fb029178df6f2ac029466c66aaa2010bdbd2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7297
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04 17:28:42 +01:00
Dennis Wassenberg ae6685fe4f inteltool: Add support for Haswell ULT and Lynx Point LP
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Change-Id: I2d5a31c831afeb92522b2673fde82922dc4efca5
Reviewed-on: http://review.coreboot.org/7275
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-11-04 15:01:04 +01:00
Edward O'Callaghan 51a2d0e461 amd/agesa/f16kb: Invalid inline asm in gcc-intrin.h
Forward port commit:
db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm

Change-Id: Ia857f76d3782aea07e09df1352eeb286e40b2689
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7302
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-04 13:33:54 +01:00
Edward O'Callaghan e408dced63 Redundant addr '&' operator on func ptr's in struct initiator
Bring code inline to be consistent with the rest of coreboot.

See standard - c99std (n1256) 6.3.2.1p4 - to paraphrase,
'expressions that refer to functions get converted to pointers to
those functions'

Change-Id: I63a7bed5efade37dd7076dbfc9c85d420cf6c92b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7290
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-04 13:31:36 +01:00
Edward O'Callaghan 009600beaf mainboard/dmp/vortex86ec: Unused variable in romstage.c
Change-Id: I9cc549b7862ee535928bd06b5fb4bd38bb67a992
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7279
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-04 12:22:30 +01:00
Edward O'Callaghan 0f7ec31239 superio/ite: Use common dispatch for pnp entry/exit functions
We already have these implemented under superio/common, use
those instead of this copy-paste syndrom.

Change-Id: I7c7737e0b3c284d8b14b36c70681ab2269bb1d4b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7310
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-04 11:36:32 +01:00
Patrick Georgi 88883163c4 build: fetch submodules as required
Also document the unusual git feature we employ for 3rdparty

Change-Id: I1d1c986f9d1c4dd8db687d746dbdeb510679141a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7243
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04 08:59:04 +01:00
Furquan Shaikh b4ce4d4814 romstage: Pass .car.data as ignored section while adding romstage
We don't want segment for .car.data section to be considered while elf_to_stage
transformation is being done. Thus, use -S option for add-stage.

Change-Id: I04868c892e3aa94113189b012d284d52bacea5f0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/7305
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-04 00:52:48 +01:00
Furquan Shaikh 405304aca3 cbfstool: Add option to ignore section in add-stage
Allow add-stage to have an optional parameter for ignoring any section. This is
required to ensure proper operation of elf_to_stage in case of loadable segments
with zero filesize.

Change-Id: I49ad62c2a4260ab9cec173c80c0f16923fc66c79
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/7304
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04 00:52:33 +01:00
Furquan Shaikh cc6f84c411 cbfstool: Convert cbfs-mkstage.c into pelf
Change cbfs-mkstage to use parsed elf instead of calling elf_headers. That
allows us to have access to the complete elf including the string table.

Change-Id: Ie767d28bdf41af38d1df0bce54bc0ada45123136
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/7303
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04 00:52:17 +01:00