Commit Graph

23619 Commits

Author SHA1 Message Date
Marc Jones 3e9694ef48 Update blobs submodule to upstream master
Updating from commit id a5efee5:
2018-01-04 16:24:19 -0700 - (Kahlee/Grunt: Move remaining stoneyridge blobs)

to commit id 19dea8d:
2018-02-01 08:51:06 -0700 - (soc/amd/Stoneyridge: Update PSP binaries to AGESA 1.3.0.9)

This brings in 2 new commits.

Change-Id: I7858ad8be13d9992949effb0216723d2480fa74d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23562
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-02-05 19:51:22 +00:00
Jenny TC 867d0df736 google/lars: Turn on keyboard backlight in romstage
Cherry-pick from Chromium:
a60ac10 [Lars: Turn on keyboard backlight in romstage]

Use the keyboard backlight to provide indication that the system is
booting.  This is useful for determining that a system is in S0 and
is running BIOS code.

TEST=boot on Lars and see keyboard backlight come on early

Original-Change-Id: I4fede6cff85f4487cedfbccf6cc24c6380d905e0
Original-Signed-off-by: Jenny TC <jenny.tc@intel.com>
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I4b1fed10d9bd1ae1b265e848417836f816f252f3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05 19:50:53 +00:00
david 01976815e4 google/lars,lili: Update GPIO mapping
Combination of several commits from Chromium tree:
949037c [Lars: coreboot GPIO changes for EVT]
c286789 [Lars: Set USB Type A current limit to 2A]
0f1b26d [lars: set BOOT BEEP GPIO GPP_F_23 to output and Low]
4a0650d [Lili: Support touchscreen]

Disable unused GPIOs based on schematic and
adds GPIO mappings for HSJ_MIC_DET, PCH_BUZZER and AUDIO_INT_WAK.

Set GPIOs USB_A0_ILIM_SEL & USB_A1_ILIM_SEL low to enable 2A
charging from the USB Type-A port.

GPP_F_23 is set to NC currently and is floating, causing the on-board
speaker to have no audio or the audio has noise; set to output/low.

These commits bring lars' GPIO mapping in line with the Chromium tree.

Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6
Original-Change-Id: I328a8be22dc59492477cbe362a5d5b94aa80a397
Original-Change-Id: I253e55bf2b423363a00347778cabaa4184d85aec
Original-Change-Id: I761f7c5ea5fc7a173c07a8c37da1338a1b2cd269
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Tested-by: Balaji Manigandan <balaji.manigandan@intel.com>
Original-Tested-by: Kuen Liu <kuen.liu@quantatw.com>

Change-Id: Ic2d188fbf913a11fbf6ad1f0eb3a5e72ba4cb1cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05 19:50:38 +00:00
Duncan Laurie d2abed5a3c google/lars: Update the MAINBOARD_FAMILY string in Kconfig
Cherry-pick from Chromium:
99cd8f8 [lars: Update the MAINBOARD_FAMILY string in Kconfig]

This string was left at the default for kunimitsu and should be
updated to indicate the proper mainboard.

Original-Change-Id: Icc0e162d57242e7b0610fb570ef1a8a45ee16e4f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ia4b70227c8cfdfe939e40ea6258d494337a2907b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05 19:50:30 +00:00
Matt DeVillier 9f1bd35b6d google/lars,lili: Update SPD Data
Combination of several commits from Chromium tree:
3b875a2 [Lars: Update Memory ID for DVT board]
b6d7c63 [Lili: Update Memory IDs]
f203f99 [Lili: Add new SPD for Hynix H9CCNNN8GTALAR-NUD]
a6571bf [Lili: Update Memory IDs]
80e1841 [Lili: Update Memory IDs]
58d4487 [Lili: Fix memory string show error in spd data]

These commits bring lars' SPD data in line with the Chromium tree.

Original-Change-Id: I54d0e6d2bbe86d5dc2ee5825f332d36abfa99084
Original-Change-Id: I9431393f369a1d2870bdabba1fc55d9cefae5c39
Original-Change-Id: I3b325a1801f49109429eb647d8d98a5537ce1b7b
Original-Change-Id: Ie8a32d8a26ea1054e2df8432084a95d1cb03f991
Original-Change-Id: I64c73950e3bea57b6c5a90257211b3d6d7f1baab
Original-Change-Id: I0e425fa4f0bae544680d5522c2e05a4f7a3be95a
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Tested-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>

Change-Id: I7cc9b01012b0b9ed72804192bb5953243fc859b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05 19:50:22 +00:00
Matt DeVillier 6598bdf2b8 google/lars: Add sdmode-delay property for max98357a
Adapted from Chromium commit:
af3ec09 [Lars: Add sdmode-delay device property for maxim98357a]

Add "sdmode-delay" as a device property for the maxim98357a codec.
This speaker amp requires both SFRM & BCLK to active and stable
before it is unmuted. If there is a BCLK and no SFRM,
that results in a pop noise.

Adding a configurable delay parameter for all Skylake platforms
to allow sufficient time for the BCLK & SFRM on I2S to be stable
before the amp unmutes itself to avoid a pop noise at the start of playback.
Setting the delay to 5ms since the observed delay between SFRM and unmuting
of the amp is around 2ms.

Adaptation needed to account for parameters having moved
from mainboard.asl to devicetree in upstream tree.

Original-Change-Id: I1fff4f86ff816e907553e7a6f1d05713f9d85084
Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I8a1c52ccdb08df9a4ab293e12bb266309e08737b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05 19:50:14 +00:00
Matt DeVillier e5eaa4b5a5 google/lars: update device properties for Nuvoton codec
Adapted from Chromium commit:
848ee3a [Lars: Add device properties for Nuvoton codec]

Update sar-threshold, sar-compare-time, sar-sampling-time
properties to match values in lars' Chromium branch.

Adaptation needed to account for parameters having moved
from mainboard.asl to devicetree in upstream tree.

Original-Change-Id: Id0c28e50406a29e6f33d04ca78fd2a3e3974fa90
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Original-Tested-by: David Wu <david_wu@quantatw.com>

Change-Id: I2748a315d27eb947197109808b4d5fa8a82c8cf3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05 19:50:06 +00:00
david ea942169f9 google/lars,lili: Set new thermal parameters
Cherry-pick from Chromium:
55c0eb3 [Lili: Set new thermal parameters]

Set new parameters of DPTF for both Lars and Lili.
The acoustic will have higher 1.6dB in transition mode,
when using Lili fan table on Lars.

Original-Change-Id: I730ac483e2a6d43c8dcfe94da6761194c14f3163
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>

Change-Id: I3bf16db43bb90a542c6526f3bc891f820da00ca0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05 19:49:26 +00:00
david 850df4d3dd google/lars: Update DPTF setting
Cherry-pick from Chromium:
dff141b [Lars: Update DPTF setting]

Original-Change-Id: I1f2686eced07c7fb1bde3c660df6d6efac607695
Original-Signed-off-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: Ifd3e844688588b6d1c69459f75c0d7da93ba3688
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05 19:49:15 +00:00
Shelley Chen 50db9a208e soc/intel/skylake: Set PsysPl3 and Pl4
If given a value for PsysPl3 and/or Pl4, set the
appropriate MSR.

BUG=b:71594855
BRANCH=None
TEST=boot up and check MSRs in OS to make sure values are set as
     expected.  Test on Fizz, which will set these values in
     mainboard.

Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
2018-02-05 19:22:44 +00:00
Hannah Williams 1177bf5165 soc/intel/common/block/pmc: Fix ACPI BAR and PCI_COMMAND in PMC config space
read_resources in common/block/pmc/pmc.c is corrupting the BAR
at offset 0x20.

pch_pmc_read_resources
                      |
                      pci_dev_read_resources
                                            |
                                            pci_get_resource
Within pci_get_resource, the BAR is read and written back. Since read of
ACPI BAR does not return the correct value, the subsequent write
corrupts the BAR. Hence re-programming the BAR. Also, reading PMC
STATUSCOMMAND register does not return bit 0 correctly in
pci_dev_enable_resources. This causes IO SPACE ACCESS to get disabled.
Hence making sure IO ACCESS gets enabled by setting dev->command

TEST=Can boot to OS
Without this change coreboot will be stuck at "Disabling ACPI via APMC:"

Change-Id: I27062419d06127951ecbbb641835d06ca39ff435
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23230
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05 18:53:16 +00:00
Martin Roth 8b40b675a8 mb/google/kahlee: Enable wlan card so it can be detected
The wifi card was not being powered, and was being held in reset during
PCI enumeration, so it was not being brought up.

BUG=b:72738963
TEST=Verify wlan card shows up in lspci

Change-Id: I5a1e83298af35aa80c67c75cd6ec0a2c3213891e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23552
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-05 17:13:01 +00:00
Nico Huber 310abe0bde coreboot_tables: Document coreboot framebuffer
A discussion around the `bytes_per_line` field (it was ignored in
CorebootPayloadPkg for some reason) made the lack of documentation
obvious.

Change-Id: I5e1343b5fe37ac106e61e6907fbcc1737ac56f8b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-05 09:59:36 +00:00
Furquan Shaikh 9d07910d24 soc/intel/apollolake: Clear RTC failure bit after reading it
This change ensures that the RTC failure bit is cleared in PMCON1
after cmos_init checks for it. Before this change, RPS was cleared
in dev init phase. If any reboot occurred before dev init stage
(e.g. FSP reset) then RPS won't be cleared and cmos_init will
re-initialize CMOS data. This resulted in any information like VBNV
flags stored in CMOS after first cmos_init to be lost.

BUG=b:72879807
BRANCH=coral
TEST=Verified that recovery request is preserved when recovery is
requested without battery on coral.

Change-Id: Ib23b1fcd5c3624bad6ab83dce17a469b2f5b5ba8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-05 00:49:12 +00:00
Julius Werner 91ebbfdc5c arm64: Pass COREBOOT flag to ARM TF, always enable logging
This patch changes the way coreboot builds ARM TF to pass the new
COREBOOT flag introduced with the following pull request:

  https://github.com/ARM-software/arm-trusted-firmware/pull/1193

Since the new coreboot support code supports the CBMEM console, we need
to always enable LOG_LEVEL INFO. Supporting platforms will parse the
coreboot table to conditionally enable the serial console only if it was
enabled in coreboot as well.

Also remove explicit cache flushes of some BL31 parameters. Turns out we
never really needed these because we already flush the whole cache when
disabling the MMU, and we were already not doing it for most parameters.

Change-Id: I3c52a536dc6067da1378b3f15c4a4d6cf0be7ce7
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-02-02 22:19:37 +00:00
Julius Werner 89c2e7f77d rockchip/rk3399: Pass coreboot table pointer to ARM TF
This patch passes the coreboot table base address to ARM TF on RK3399
devices to be able to use the new coreboot table parsing support.

Change-Id: I5cb2f13ce71e374207d0fa7a71c38852d680dc56
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23557
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-02 22:19:26 +00:00
Julius Werner 6d643cf722 rockchip: Correct UART reference clock value
The Rockchip UARTs are tied directly to the 24MHz oscillator and are
thus clocked with exactly 24MHz. The reasons why our code instead uses
some 23.xxMHz value have long been lost in time. For the current shared
8250 implementation, the baud rate divisor for 115200 would be the same.

Correcting this does make the information in the coreboot table more
accurate and help payloads chose a better divisor, though.

Change-Id: Ieceb07760178f8ddbb5936f8742b78f8def4072d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-02 22:19:14 +00:00
Julius Werner 8e08a844f7 rockchip/rk3288: Fix includes for <soc/clock.h>
This header uses common types and macros so it needs to include the
headers that provide those itself.

Change-Id: Ieceb0deadbeef8ddbbb00b13542b78f8def4072d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-02-02 22:19:04 +00:00
Julius Werner 98d2d3940e Update arm-trusted-firmware submodule to current upstream master
This patch updates the arm-trusted-firmware submodule from:

commit 9fd4a36c408a254d887106e6e3960d496456be2c
(Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_state)

to

commit 693e278e308441d716f7f5116c43aa150955da31
(Merge pull request #1245 from antonio-nino-diaz-arm/an/checkpatch)

This brings in 79 new commits.

Change-Id: Ieceb07760178f8ddbb5cafebabeb78f8def4072d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-02 22:18:49 +00:00
Lin Huang 1df0c570c3 rockchip/rk3399: extend delay between saradc power up and start command
We found when ambient temperature low, with now saradc frequency and
delay between saradc power up and start command, there may get wrong
adc value, then get the wrong ramid or boardid, so lower the saradc frequency
and add the delay time between power up and start command.

BUG=b:70692504
BRANCH=gru
TEST=test on Dru in 0C temperature, always get right adc value

Change-Id: I42e49ca63299479912fa05e2a62cba6f2de4b337
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/23515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-02 22:18:28 +00:00
Lin Huang 1cce10ed5c google/gru: Use newer version of Innolux P097PFG panel init code
There is a line artifact in the lower third of the display with the
current initialization code. So update it with code provided by
Innolux to fix this issue.

BUG=b:69689064, b:72191820
TEST=boot on dru with an Innolux panel and artifact line disappear.

Change-Id: I9679c4f7f706fd6cd2e1dba7ec79e772fe3f227a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/23561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-02 22:17:46 +00:00
Duncan Laurie 2177ccfac9 ec/google/chromeec: Remove wake flag from keyboard IRQ
The keyboard IRQ was changed to ExclusiveAndWake in order to support
waking from suspend-to-idle (S0ix) with commit
f611fcfaca http://review.coreboot.org/11712

However this is triggering a kernel panic on Windows 10 because it
apparently does not like legacy device interrupts to to be set as
wake capable.

This change is no longer necessary because the linux kernel was
changed to always treat the keyboard as wake capable:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/input/serio/i8042.c?id=f13b2065de8147a1652b830ea5db961cf80c09df

Change-Id: I26e27de68095f8d176108f39312338522d7cfba0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23563
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-02-02 21:48:25 +00:00
Richard Spiegel 9dc5600f86 mb/google/kahlee/mainboard.c: Create mainboard_pirq_data
When booting kahlee, there's an error message: "Warning: Can't write PCI
IRQ assignments because 'mainboard_pirq_data' structure does not exist".
This is generated by write_pci_cfg_irqs due to missing mainboard_pirq_data.

BUG=b:70788755
TEST=Build and boot kahlee. Warning message must be gone.

Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-02 20:51:17 +00:00
Elyes HAOUAS adda3f810f nb/intel/sandybridge: Add required space before opening parenthesis '('
Change-Id: I6dfef118dc2fecf2a8f2f3401c779a3becfb71a9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-02 16:08:39 +00:00
Elyes HAOUAS 879eab8626 arch/x86/acpi/statdef.asl: Remove unnecessary whitespace
Change-Id: I8c49853a54fc301d39dc7c362f2085c25fad7fbd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-02 16:08:16 +00:00
Aaron Durbin 97d58bcc09 drivers/i2c/designware: conform to controller restrictions
The designware i2c controller indicates that the slave address
shouldn't be programmed while the controller is enabled. Therefore,
switch the ordering of the slave target address and the enable.
Additionally, ensure the controller is disabled prior to the
start of the slave programming sequence.

Lastly, chunk up the i2c_msg segments at differing slave address
boundaries. That allows for simpler programming for the controller
by only doing one slave address transaction chunk at a time.

BUG=b:70232394,b:69250772

Change-Id: Iebc08e2db847cb182fad98e0ff3d799b9a64aca7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-02 05:05:39 +00:00
Matt DeVillier f18c0415ef payload/tianocore: Fix patch to preserve coreboot table
Part of the original patch, commit 85a90e1, reverted edk2 commit:
1d7258f [CorebootModulePkg:Removing EFI_RESOURCE_ATTRIBUTE_TESTED]
which had the unintended effect of causing memory above 2GiB
from being unavailable (marked reserved) when booting without a
connected display (aka headles mode).

This commit strips the patch to only the component needed to fix
reading of the coreboot table low memory pointer.

TEST: boot 4GB google/panther without connected display, verify
memory above 2GB available via 'dmesg | grep BIOS-e820' and 'free -m'

Change-Id: I39327929f9b0b940fc12cdca1d744456fdc097e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-02-01 19:31:24 +00:00
Arthur Heymans 85a2c71550 payloads/tianocore: Add a patch to use the proper BytesPerscanline
This fixes tianocore garbled framebuffer when 'x_resolution *
bits_per_pixel / 8' is not equal to 'bytes_per_line'.

This patch was also send to the edk2-devel mailing list:
https://lists.01.org/pipermail/edk2-devel/2018-January/020436.html

Tested on Thinkpad X220 with libgfxinit on 1366x768 display.

Change-Id: Ib9eaf692f86d416cd4ec3cc73a8b0aa0a28a38dd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2018-02-01 18:57:52 +00:00
Arthur Heymans 4ad1f7d67e Add a default path for vbt.bin
FSP_GOP needs a vbt.bin to work but before this patch it was able to
build with the default configuration which was an empty path for
vbt.bin.

To make Jenkins happy don't select FSP_GOP by default, at least until
all boards have the proper vbt blobs in the blobs repo.

Change-Id: Ibc36d6d4dd1a56c53819b169e6f4799ce3c23e03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-01 18:57:28 +00:00
Marc Jones 823dbde2ab vendorcode/amd/pi/00670f00: Update headers to AGESA 1.3.0.9
Update the shared AGESA headers to 1.3.0.9.

This depends on 3rdparty/blobs/pi/amd/00670F00/ binaries updated
to the same version.

BUG=b:72679320
TEST=build and boot Grunt

Change-Id: I783b7318e8273913f753b70f12bfe8b71274e27f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-01 18:42:58 +00:00
Marshall Dawson 0876caa473 lib/stage_cache: Add debug messages for failures
Communicate additional status to the console when the save and load
functions do not function as expected.  The most likely scenario for
an error is when using a cache that is external to cbmem, and restricted
in size.

Change-Id: Ic9a709c11152b3b9cb40abfc204151f9636b5a4c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-01 17:20:39 +00:00
Marshall Dawson 8cc5fdec90 amd/soc/common: Remove cbmem subregions in heap
Revert most of 4f3f47b "amd/common: Define regions in cbmem".  This
puts the management of the heap space back to its traditional
methodology.  Subsequent patches that were to have used these
subregions have been reworked.

BUG=b:69614064

Change-Id: Ib3d40bcf61c50dbc481b60e7b5286f65a529b912
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-01 17:20:09 +00:00
Chris Ching 1f27357829 drivers/i2c/designware: Unset IC_ENABLE when setting target address
To set address on AMD, IC_ENABLE == 0.

BUG=b:69416132
BRANCH=none
TEST=Test communication with i2c TPM on grunt and coral

Change-Id: I7faee8e11439deceab946cc82d30d274b529b90d
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Reviewed-on: https://review.coreboot.org/23293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-01 16:35:20 +00:00
Aaron Durbin 65d78e880a mb/google/kahlee: always load and run display oprom
The kernel requires the display oprom is loaded *and* ran
in order for the kernel to not panic. Therefore, select the
correct settings such that normal mode works for Chrome OS.

BUG=b:72400950

Change-Id: Ibae5bc6b382cbe71a55c2386a24bb420cb8f313f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23506
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-01 00:14:14 +00:00
Aaron Durbin 10510255f7 device: add ALWAYS_RUN_OPROM option
Certain platforms require that the option rom always needs to be
ran in order for display to work correctly. Therefore, provide
this ability for the platform to select such that we force option
rom loading.

BUG=b:72400950

Change-Id: I597bc8af7ac8b68fe8505aac5f1c7e1ccd34ac27
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23505
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-01 00:14:04 +00:00
Aaron Durbin fbed9a5fac device/pci_device: remove #if/#endif in oprom logic
Use C if conditions instead of preprocessor macros.

BUG=b:72400950

Change-Id: I8107f94b9ecb6f32c569cad0bcb3d51ab39aa35c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23504
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-01 00:13:58 +00:00
Marshall Dawson 2a5e15ce11 amd/stoneyridge: Move TValid and SmmLock to end of POST
Delay making TSEG valid until the end of POST.  After the CPU setup,
there are times where coreboot needs to access the SMRAM from outside
of SMM.  Also relocate locking of the SMM settings from the CPU init
to the end of POST (or just before resuming).

Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-31 22:12:50 +00:00
Marshall Dawson 34fa425308 commonlib: Add AGESA S3 resume defines
Extend the values reserved for AGESA to include the Entry Points used
for S3 Resume.

BUG=b:69614064

Change-Id: I6b50e76a0c49c1f317f9294c5f95735e7aa5d95c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31 22:07:48 +00:00
Justin TerAvest f9bfe05bd1 mb/google/kahlee: Add grunt cr50 support
This commit adds an entry for H1/Cr50 into the devicetree for setting up
ACPI entries for H1 communication.

BUG=b:69250772
TEST=See probe messages in dmesg

Change-Id: Id55ce3364ea4acdb62782758e5bcb2a167286cb9
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23514
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31 21:06:28 +00:00
Justin TerAvest b1204aab86 mb/google/kahlee: Add grunt trackpad in devicetree
This commit removes a manually written asl file in favor of configuring
the trackpad through devicetree.

BUG=b:72121803
TEST=cat /proc/interrupts with trackpad connected

Change-Id: I38afcf89ea64ffaf6a10bb317c41154feda57e50
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23508
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-31 20:25:43 +00:00
Martin Roth 215bc53117 util/docker/coreboot-sdk: Add libftdi1-dev
chromeec uses libftdi1-dev, so add it to the image.

Change-Id: I517e3f073062dcc6b0b8e3adaf7b0123290a1698
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-31 16:44:25 +00:00
Patrick Rudolph a88697444a nb/intel/*.h: Remove left-over register definitions
The code has been moved into drivers folder.

Change-Id: I122affffd5108052ed7a95b34d0d66a6d3279d41
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/23487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-31 15:23:56 +00:00
Duncan Laurie 662b6cb3ed soc/intel/skylake: Always add PM1_TMR block to FADT
Provide the PM1_TMR information in the FADT even if PmTimerDisabled is
set because PM timer emulation is enabled via MSR 121h so the timer will
still work and can be used by things like Tianocore and Windows.

Change-Id: I78e435c34dd4e6241d345c4d07470621ea051fb8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-31 09:56:10 +00:00
Duncan Laurie 61e4e1ab6f soc/intel/skylake: Fix common timer frequency
The calculation to set up the PM timer emulation is using an
incorrect common timer clock value that was copied from Apollolake.
According to the PDG Skylake and Kabylake clocks are derived from a
24MHz XTAL, not 19.2MHz like Apollolake.

Fixing this value results in the proper "correction value" to be
programmed into the PM timer emulation MSR that matches the raw value
that would be programmed by FSP.  (if it were doing MpInit)

Old PM timer correction value: 0x2fba2e25
New PM timer correction value: 0x262e8b51

Change-Id: Ib2bb3cb1938ae34cfa7aef177bef6fc24da73335
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23509
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-31 09:55:59 +00:00
Patrick Rudolph 00c0cd2c45 device/pci_rom: Write _ROM method for VGA devices
Write _ROM method and store PCI Option ROM in CBMEM.

Allows an EFI compatible OS to retrieve the Option ROM without the need
to access the PCI BAR. As the Option ROM is no longer present in the
legacy VGA area it's required for mobile platforms. On hybrid devices,
like Lenovo Thinkpads supporting NVIDIA Optimus it's the only way to
retrieve the Option ROM, even with legacy BIOS, as there's no PCI BAR to
map.

Tested on:
* Lenovo T530
* Linux Kernel 4.13.7
* nouveau

Change-Id: I548b730fb64833083cc05af5b21dd6959804224b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31 08:36:52 +00:00
Patrick Rudolph 6be6df0014 arch/x86/acpigen: Add generator for _ROM
Generate ACPI AML code for _ROM method.
This function takes as input ROM data and ROM length.

 Arguments passed into _DSM method:
 Arg0 = Offset in Bytes
 Arg1 = Bytes to return

Example:
 acpigen_write_rom(0xdeadbeef, 0x10000)

 AML code generated would look like:
        Method (_ROM, 2, NotSerialized)  // _ROM: Read-Only Memory
        {
            OperationRegion (ROMS, SystemMemory, 0xdeadbeef, 0x00010000)
            Field (ROMS, AnyAcc, NoLock, Preserve)
            {
                Offset (0x00),
                RBF0,   524288
            }

            Local0 = Arg0
            Local1 = Arg1
            If (Local1 > 0x1000)
            {
                Local1 = 0x1000
            }

            If (Local0 > 0x00010000)
            {
                Return (Buffer (Local1)
                {
                     0x00
                })
            }

            If (Local0 > 0x0f000)
            {
                Local2 = 0x10000 - Local0
                If (Local1 > Local2)
                {
                     Local1 = Local2
                }
            }

            Name (ROM1, Buffer (Local1)
            {
                 0x00
            })
            Local1 *= 0x08
            Local0 *= 0x08
            CreateField (RBF0, Local0, Local1, TMPB)
            ROM1 = TMPB /* \_SB_.PCI0.GFX0._ROM.TMPB */
            Return (ROM1) /* \_SB_.PCI0.GFX0._ROM.ROM1 */
        }

Change-Id: Ie118b15257295b7133c8e585c0fd5218249dec8d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-31 08:36:42 +00:00
Subrata Banik a8733e381d soc/intel/cannonlake: CannonaLake make use of FVI information
Select DISPLAY_FSP_VERSION_INFO Kconfig to get all required
firmware information right after FSP-S.

TEST=Display FW information as below

>> Display FSP Version Info HOB
Reference Code - CPU = 7.1.20.52
uCode Version = 0.0.0.16
Reference Code - ME 11.0 = 7.1.20.52
MEBx version = 0.0.0.0
ME Firmware Version = Consumer SKU
Reference Code - CNL PCH = 7.1.20.52
PCH-CRID Status = Disabled
CNL PCH H A0 Hsio Version = 2.0.0.0
CNL PCH H Ax Hsio Version = 9.0.0.0
CNL PCH H Bx Hsio Version = 5.0.0.0
CNL PCH LP Ax Hsio Version = 13.0.0.0
CNL PCH LP B0 Hsio Version = 7.0.0.0
CNL PCH LP Bx Hsio Version = 6.0.0.0
CNL PCH LP Dx Hsio Version = 2.0.0.0
Reference Code - SA - System Agent = 7.1.20.52
Reference Code - MRC = 0.5.1.19
SA - PCIe Version = 7.1.20.52
SA-CRID Status = Disabled
SA-CRID Original Value = 0.0.0.0
SA-CRID New Value = 0.0.0.0

Change-Id: Ibfcac0002998e8a6594bb6dfc68b2577f62ddbff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23387
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-31 05:57:24 +00:00
Subrata Banik 73b67dcee8 drivers/intel/fsp2_0: Add support to display FSP version info Hob
This patch locates FSP FVI hob in order to extract all firmware
ingredient version information.

So far this feature is only supported for CannonLake SoC onwards.

Change-Id: Ib749e49a9f263d85947b60d4c445faf8c37f5931
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-31 05:57:16 +00:00
Subrata Banik df74577e99 vendorcode/intel/fsp/fsp2_0: Add CannonLake FirmwareVersionInfoHob header
Base patch to create Firmware Version Info (FVI) for CannonLake coreboot
platform using CannonLake FSP new feature.

Expectation is that, FSP will provide version information of all Firmware
ingredient its equip with (i.e. CPU Ref Code, uCode version, MCH Ref Code,
CSE Sku type, CSE version, System Agent Ref Code, OpRom Version, GOP version,
PCH Ref Code version etc.)

Change-Id: Ic388e036709190e8d5c5010f4ea87223291f21d0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31 05:57:02 +00:00
Lijian Zhao e2a7bf16f0 intel/fsp: Update cannonlake fsp header
Update Cannonlake FSP header to revision 7.x.20.52. Following changes
had been made:
1. Hide internal EV related options.
2. Add GT voltage override options.
3. Add PEG IMR selection.
4. Add PCH DMI ASPM options.

TEST=NONE

Change-Id: If186a1eb440266f1eaeb03505fe0ff4c6a521be6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-31 05:56:54 +00:00