So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moves the Cannon Lake definitions into its own header.
Change-Id: I5991c3cebba0e05504940ae66fa7bb63bf280ab1
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38626
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moves the Ice Lake definitions into its own header.
Change-Id: I5735f12480091a9b6c5e5c103a1ca7b7b1f3f997
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38625
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Revert the upgrade as it breaks at least the devicetree parser on
aarch64, tested on qemu aarch64 target.
This reverts commit dfd3f21174.
Change-Id: I65607817188db21533014caa6d15be9a2004d498
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The latest debian builder image doesn't compile GDB correctly. Disable
the build test until I can get it working again.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I7852a39ed40a7364d24d0bbf014fd25058491083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39575
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code in coreboot is actually for the Arrandale processors, which
are a MCM (Multi-Chip Module) with two different dies:
- Hillel: 32nm Westmere dual-core CPU
- Ironlake: 45nm northbridge with integrated graphics
This has nothing to do with the older, single-die Nehalem processors.
Therefore, replace the references to Nehalem with the correct names.
Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code is for Arrandale CPUs, whose System Agent is Ironlake.
This change simply replaces `nehalem` with `ironlake` and `NEHALEM`
with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as
changing some of them would impact the resulting binary.
Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and packardbell/ms2290 does not change.
Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop dummy entry.
Change-Id: I1257115bd73fe90c6435116c8705cb5c98d945e1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39559
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add template files for making a new barebones-copy of Volteer.
BUG=b:147483699
BRANCH=None
TEST=N/A
Change-Id: I8cc69b8ce7dbc6809de058019bdc466a060069e7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Intel supplies microcode (at least for MinnowBoard) in Intel Assembly
*.inc format rather than C header. This change allow to pass in
configuration directory with *.inc files rather than list of *.h
files.
Change-Id: I3c716e5ad42e55ab3a3a67de1e9bf10e58855540
Signed-off-by: Bartek Pastudzki <Bartek.Pastudzki@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Abuild allows us to add config files below `configs/` for each
mainboard. So far, these were built instead of the default config.
However, that allows to hide errors in the default config. Hence,
we should build that too in any case.
Change-Id: I94075dbaa6fabeb75bdbc92e56f237df80c15cef
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39382
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Changes allow to use the integrated panel logic (power sequen-
cing and backlight control) for more connectors. The Kconfigs
GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set
to any port, e.g.
config GFX_GMA_PANEL_1_PORT
default "DP3"
Now that the panel logic is not tied to the `Internal` port
choice anymore, we can properly split it into `LVDS` and `eDP`.
This also adds Comet Lake PCI IDs which should still work the
same as Kaby and Coffee Lake.
Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SCH5317 can have either 0x85 or 0x8c as device ID. However, the
former results in false positives on any ITE IT85xx series embedded
controller, which has led some people to think that chip was actually in
their laptops. Moreover, there is no register dump for the SCH5317.
Since nobody has touched this in over a decade, avoid further confusion
by dropping the misleading definition.
Change-Id: I4d1d34d1b88b878461499e52f1a916ee1e33210d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For some reason, this symbol gets redefined, which causes a warning.
Hide the warning by checking whether it is already defined.
Change-Id: I70ffc9a799e0b536d6aba7d00f828bd6d915d94c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
I received feedback that people were confused by "Error: foo", so
replace it with something more user friendly that serves the same
purpose.
Change-Id: I17b902a62020109e079437c8d9ffd7ea5979a3a1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This also drops individual copyright notices, all mentioned authors in
that part of the tree are listed in AUTHORS.
Change-Id: Ib5a92bb46ff2b9d2928aae3763daec71747044c2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This also drops individual copyright notices, all mentioned authors in
that part of the tree are listed in AUTHORS.
Change-Id: I770c1afd9b68a40ec0e69818f24b5ef3ad4f1d35
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
While a 4 clause BSD license "with advertising" is incompatible to the
GPL, the University of California declared the problematic clause null
and void.
See ftp://ftp.cs.berkeley.edu/pub/4bsd/README.Impt.License.Change
Change-Id: I4ebb822f64989a5fc8f686e548a94653508d1113
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This also drops individual copyright notices, all mentioned authors in
that part of the tree are already listed in AUTHORS.
Change-Id: I19b1c379b474dd011e2d0f8c8202ff1351c9290d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This also drops individual copyright notices, all mentioned authors in
that part of the tree are already listed in AUTHORS.
Change-Id: Ic5eddc961d015328e5a90994b7963e7af83cddd3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This also drops individual copyright notices, all mentioned authors in
that part of the tree are already listed in AUTHORS.
Change-Id: Ic2bab77edaf7ad97b7f3278cb108226a18cf3791
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Otherwise there will, after make gitconfig,
be (hidden) shell command failures with 'git commit -s':
gmake: util/lint/check-style: Command not found
gmake: *** [Makefile.inc:632: check-style] Error 127
Change-Id: I3891dee53702ee10e5e44dae408193e49d7a89f1
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38227
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BSD grep (on macOS) doesn't like repeated repetition operators, it
throws the error
grep: repetition-operator operand invalid
This removes the superfluous repetition operator to make the commit-msg
hook work on macOS and other platforms not using GNU grep.
Change-Id: Id0f57d0f14634f7844b889d71342b2982fcadeb2
Signed-off-by: Patrick Elsen <pelsen@xfbs.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It somehow creeps into `make clean`, but is not used at all. Since no
VIA platform remains in coreboot, drop the utility as well.
Change-Id: Ia7e11379a6db650b5190a056226a9101c2be7dec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
unzip might not be installed by default, so it is added as a
dependency in crosfirmware script.
Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc
Signed-off-by: Mete Balci <metebalci@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add an optional commandline flag to define the filename of the resulting
output file. If this flag is not defined, it will behave like before by
using the old filename with a ".new" suffix.
With this additional flag it is not necessary to move the output file at
build-time, and the stdout print "Writing new image to <filename>" makes
more sense in the build context.
Change-Id: I824e94e93749f55c3576e4ee2f7804d855fefed2
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
They are downright useless and result in ACPI errors. So, burn them.
Also, do a minor update to autoport's README about these values.
Change-Id: Idb5832cfd2e3043b8d70e13cbbe8bd94ad613120
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Relocate the first size check. This was automatically continuing
and not looking for the caller incorrectly passing a destination.
New information indicates that the APOB_NV should always be present
in the system. Augment the missing size check to inferring whether
a missing size is valid, as in the case of older products, or truly
missing when it's needed.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I51f5333de4392dec1478bd84563c053a508b9e9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix two out-of-bounds reads in lz4 decompression:
1) LZ4_decompress_generic could read one byte past the input buffer when
decoding variable length literals due to a missing bounds check. This
issue was resolved in libpayload, commonlib and cbfstool
2) ulz4fn could read up to 4 bytes past the input buffer when reading a
lz4_block_header due to a missing bounds check. This issue was resolved
in libpayload and commonlib.
Change-Id: I5afdf7e1d43ecdb06c7b288be46813c1017569fc
Signed-off-by: Alex Rebert <alexandre.rebert@gmail.com>
Found-by: Mayhem
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
nds32 and GNAT bad constant patches are integrated in upstream
so we don't need them anymore.
Change-Id: Id6f65548764654ae5539ac3c835853ea2fa1c5e0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32564
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When compiling with GCC, use the special wrappers around ar and nm that
provide the path to the plugin they need to understand LTO object files.
These wrappers forward all other functionality to the underlying
programs, so they should otherwise be equivalent.
Change-Id: Ibdae4faabf67bf6a4bb8c38970f6189646ee74b3
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38290
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested on a laptop with an i7-5500U processor, the device is now found.
Change-Id: I49ddec862520d0d5492d78fec89efd841c141790
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The -M option of ifdtool sets not only AltMeDisable bit, but also
MeDisable bit in ICH0 and MCH0 straps. Make it obvious and mention
in the help message.
Change-Id: I9dba2fa6509a9c833f72414367944bc606671e7b
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
create_coreboot_variant.sh and kconfig.py have moved to the chromium
repo, in src/platform/dev/contrib/variant (see crrev.com/c/2052338),
so remove them from the coreboot repo.
BUG=b:149410618
BRANCH=None
TEST=N/A
Cq-Depend: chromium:2052338
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: Ie27f68bfd978be5e2b1a2f0789d574749825f6fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
named choices can be overridden with a default later-on:
choice FOO
config A
config B
config C
endchoice
...
if BOARD_FOO
choice FOO
default A
endchoice
endif
Reflect that.
Change-Id: I6662e19685f6ab0b84c78b30aedc266c0e176039
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29813
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also reflow the paragraph in which the typo was hiding a bit.
Change-Id: I2fea01fe23af21c2540fa90154ce29af3e74776b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
The coreboot coding style does not insert a space between the function
and argument list.
Change-Id: I740f6c7f513e4f2715c793f61c9d9835c55c9dce
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The pgeorgi namespace is my own and things could change without notice
there. To overcome this issue, encapsulate is now maintained on
review.coreboot.org/encapsulate.git and mirrored over to github, so
let's use that.
Change-Id: I12e43f61f693a6b0392b84dd56ede665a1a2129a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38899
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the create_coreboot_variant.sh and kconfig.py to support the
zork baseboard. Full template files will be added in a later CL.
BUG=b:148161697, b:148281637
BRANCH=None
TEST=`./create_coreboot_variant.sh zork dalboz` and verify that the
changes staged are correct.
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Ie0a29bb9f4bb8f3bb7eaeae8799cef861c395e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I46525243729c1dbcd30b346d4603452eea14ad9d
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add the capability to update the Flash Descriptor directly instead
of raising a Segmentation Fault. In this way it will be possible to
add a Kconfig options to modify the ifd descriptor at build-time.
Change-Id: Id3db09291af2bd2e759c283e316afd5da1fb4ca7
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This CL has changes that allow us to enable a configurable
ramstage, and one change that allows us to minimize PCI
scanning. Minimal scanning is a frequently requested feature.
To enable it, we add two new variables to src/Kconfig
CONFIGURABLE_RAMSTAGE
is the overall variable controlling other options for minimizing the
ramstage.
MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal
PCI scanning.
Some devices must be scanned in all cases, such as 0:0.0.
To indicate which devices we must scan, we add a new mandatory
keyword to sconfig
It is used in place of on, off, or hidden, and indicates
a device is enabled and mandatory. Mandatory
devices are always scanned. When MINIMAL_PCI_SCANNING is enabled,
ONLY mandatory devices are scanned.
We further add support in src/device/pci_device.c to manage
both MINIMAL_PCI_SCANNING and mandatory devices.
Finally, to show how this works in practice, we add mandatory
keywords to 3 devices on the qemu-q35.
TEST=
1. This is tested and working on the qemu-q35 target.
2. On CML-Hatch
Before CL:
Total Boot time: ~685ms
After CL:
Total Boot time: ~615ms
Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Developer/Reviewer, be aware of this patch from Mistral:
https://review.coreboot.org/c/coreboot/+/33425/18
Change-Id: I020d1e4d4f5c948948e1b39dd18af1d0e860c279
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add golang and libelf-dev so LinuxBoot can be built from the
coreboot-sdk docker container.
BUG=N/A
TEST=build
Change-Id: I7a156fc24a6040d73467e06c16139bf298a29740
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38751
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
According to the C standard, accessing the NULL pointer (memory at
address zero) is undefined behaviour, and so GCC is allowed to optimize
it out. Of course, accessing this memory location is sometimes
necessary, so this optimization can be disabled using
-fno-delete-null-pointer-checks. This is already done in coreboot, but
adding it to xcompile will also disable it for all the payloads. For
example, coreinfo compiled with LTO libpayload crashes when this flag
isn't set, presumably because the compiler is optimizing something out
that it shouldn't.
Change-Id: I4492277f02418ade3fe7a75304e8e0611f49ef36
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38289
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This GPIO dumping was implemented using the
Document Number: 341080-001
Intel® 495 Series Chipset Family On-Package Platform Controller Hub
Volume 1 of 2
datasheet. The GPIO community ports can be found in table 36-1, while
the community and pin descriptions are taken from
linux/pinctrl/intel/pinctrl-icelake.c .
This commit was tested on the late 2019 Razer Blade Stealth with 1065G7
and Chipset 495 PCH and the output manually compared against
linux/pinctrl-intel.
Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Newest clang compilers warn about "misleading indentation", and because
warnings-are-errors in our builds, that breaks the build.
The lzma code base is vendored in, so we might just have to update it,
but that's a bigger effort than just removing a couple of spaces (the
coding style of the file is horrible, but I will only change it as much
as the compilers ask for).
BUG=chromium:1039526
Change-Id: I6b9d7a760380081af996ea5412d7e3e688048bfd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The help output suggests clean-docker should be used to remove the
docker coreboot containers and images. The Makefile actually supports
the docker-clean target.
Corrected the help output to reflect the actual Makefile target.
BUG=N/A
TEST=build
Change-Id: Ib24f8e1ecdf3bdc31b3f8b484ce7ca0c19b645ee
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
In glibc feature control macros, _DEFAULT_SOURCE is the shorthand to
tell glibc to enable "all the default stuff", meaning POSIX, BSD and
System V interfaces. However, this macro is somewhat recent and older
glibc versions (e.g. 2.12) are still occasionally in use that don't
recognize it yet. For the benefits of users with these versions, let's
also enable the deprecated _BSD_SOURCE and _SVID_SOURCE macros which
essentially achieve the same thing. We must continue to define
_DEFAULT_SOURCE so that newer glibc versions don't throw a deprecation
warning.
This patch should make BSD-style byteswap macros like le32toh()
available on these older glibc versions.
Change-Id: I019bbcf738a1bcdccd7b299bdde29cd4d4ded134
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Change-Id: Iae8d4f0470f75b47e53c50790f06902acb9a24cc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The Intel docs also call it "Scalable Bus Speed", so the typo is on us.
Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace
--strict --terse -f util/msrtool/*.c
Change-Id: I84bdba687060e695d29420b9dd8eeb5f4ec44610
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38634
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 1191c09201b43aab55333a70d056d0c355abe329 at
https://salsa.debian.org/agx/lintian/tree/master/data/spelling provides
a much more comprehensive collection of misspellings, so merge it in.
While at it, also sort the file for future easier merging which is the
main reason that some lines appear to be removed: they're merely moved.
For sorting, I adapted their make rule:
make -f - sort-spelling.txt <<'EOF'
.RECIPEPREFIX=%
sort-%: %
%csplit --prefix $<- $< '/^$$/'
%LC_ALL=en_US sort -u $<-01 | cat $<-00 - > $<
%rm -f $<-0[01]
EOF
Change-Id: I939e3a8820c88d0e639bd29b46a86b72bce1a098
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38632
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch creates a new commonlib/bsd subdirectory with a similar
purpose to the existing commonlib, with the difference that all files
under this subdirectory shall be licensed under the BSD-3-Clause license
(or compatible permissive license). The goal is to allow more code to be
shared with libpayload in the future.
Initially, I'm going to move a few files there that have already been
BSD-licensed in the existing commonlib. I am also exracting most
contents of the often-needed <commonlib/helpers.h> as long as they have
either been written by me (and are hereby relicensed) or have an
existing equivalent in BSD-licensed libpayload code. I am also
relicensing <commonlib/compression.h> (written by me) and
<commonlib/compiler.h> (same stuff exists in libpayload).
Finally, I am extracting the cb_err error code definitions from
<types.h> into a new BSD-licensed header so that future commonlib/bsd
code can build upon a common set of error values. I am making the
assumption here that the enum constants and the half-sentence fragments
of documentation next to them by themselves do not meet the threshold of
copyrightability.
Change-Id: I316cea70930f131e8e93d4218542ddb5ae4b63a2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Values as per "IT8772E Preliminary Specification V0.4 (For F Version)".
Some values are unclear on this document, but is the only one I have.
Change-Id: I6d74984f453c47d6ec71963a7dcab961a22a5964
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The existing rule created a potential race condition between creating
the directory and putting files in there, so use our existing
infrastructure for directory creation instead.
Change-Id: If52a9f558c7d9ce85f71ba53232594699c9d357a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37798
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When regions are resized they are always aligned to the top of the
region. For the BIOS region this is correct. The other regions however
should be aligned to the bottom of the region.
Update the region handling to only align BIOS region to top of region.
BUG=N/A
TEST=verified image resize
Change-Id: Ied0e763b5335f5f124fc00de38e5db1a4d0f6785
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Update the two flashrom URLs to use HTTPS. All other URLs are already
using HTTPS.
Change-Id: I8e9861b2748289522ab418960a463ae55ab0d2d3
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
According to intels datasheet
Document Number: 341078-001
10th Generation Intel® Core™ Processor Families
Volume 2 of 2
we can dump the ICL MCHBAR similiar as on 8th / 9th gen CPUs.
The difference is that on ICL the MCHBAR address is definited by
the bits 38:16 instead of 38:15 giving the constraint that it has
to be 64kbit instead of 32kbit aligned. (Section 3.1.13)
Change-Id: Ia597a4b3738c11cb48ce5808d8459b4a2a768077
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Build the smcbiosinfo tool with other tools.
Fixes possible race condition on jenkins.
Change-Id: I38f7ee2fdef2818ad685b3de53ad74f7da50600f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Match each of the possible APCB items with a corresponding backup APCB.
A missing backup copy can prevent the system from booting.
Change-Id: I400194b2763239896214ea42cfe6fbeb8ed261a8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The BMC and tools interacting with it depend on metadata placed inside
the ROM in order the flash the BIOS.
Add a new tool smcbiosinfo, integrate it into the build system, and
generate a 128byte metadata file called smcbiosinfo.bin on build.
You need to provide the BoardID for every SMC mainboard through a new
Kconfig symbol: SUPERMICRO_BOARDID
Some fields are unknown, but it's sufficient to flash it using SMC
vendor tools.
Tested on Supermicro X11SSH:
* Flashing using the WebUI works
* Flashing using SMCIPMITool works
No further validation is done on the firmware.
Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In preparation to update to SPDX license headers, add identifiers
for the licenses seen in the coreboot project and create a command
line parameter allowing only SPDX license identifiers to be detected.
Here are example locations of these licenses:
Apache-2.0 - src/soc/sifive
BSD-3-Clause - Throughout coreboot & libpayload source
GPL-2.0-only - Throughout coreboot source
GPL-2.0-or-later - Throughout coreboot source
GPL-3.0-only - util/amdtools
GPL-3.0-or-later - src/lib/[gcov/libgcov/gnat]
ISC - src/lib/ubsan.c, soc/qualcomm/ipq806x/include/soc/gsbi.h, others
MIT - soc/nvidia/tegra210/mipi_dsi.c, files in mainboard/cavium/
X11 - include/device/drm_dp_helper.h, drivers/aspeed/common/ast_tables.h
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I07a7ca408ac8563e03e189d05ef7729dfb6fc24e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
create_coreboot_variant.sh now supports the Volteer baseboard in
addition to Hatch. The shell script and supporting python code are
moved up one level, while retaining the ${BASE}/template/* file
structure for each supported baseboard.
kconfig.py has to add slightly different text to Kconfig.name
depending on which baseboard is selected.
BRANCH=None
BUG=b:146646594
TEST=Create variants of Hatch and Volteer, check that the staged
commits are correct.
$ ./create_coreboot_variant.sh hatch sushi b:12345
src/mainboard/google/hatch/Kconfig and Kconfig.name will have new
sections for SUSHI. src/mainboard/google/hatch/variants/sushi
will have a copy of util/mainboard/google/hatch/template
$ ./create_coreboot_variant.sh volteer ripto b:12345
src/mainboard/google/volteer/Kconfig and Kconfig.name will have new
sections for RIPTO. src/mainboard/google/volteer/variants/ripto
will have a copy of util/mainboard/google/volteer/template
Also run the script with an existing board name to verify that you
can't create a variant that already exists.
Change-Id: I084b6c50bb76af0d11dc86a96b3c3c434569a0dd
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Running the x86_64 qemu mainboard target with '-accel kvm' results in hang,
as the 'D' and 'A' bits needs to be set in read only page tables.
Tested on QEMU Q35: Boots into payload with '-accel kvm'.
Change-Id: I4beae8deec6bf34f9762e7b54c5da4e5b63f6d24
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36778
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Johanna Schander