Commit Graph

38993 Commits

Author SHA1 Message Date
Arthur Heymans 42a6f7e417 soc/intel/xeon_sp: Lock down DMI3 PCI registers
This is required for CBnT.

Change-Id: If5637eb8dd7de406b24b92100b68c5fa11c16854
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28 13:39:23 +00:00
Yuchen Huang b0ab41e027 soc/mediatek/mt8192: add rtc MT6359P driver
Add rtc MT6359P driver for rtc init and rtc eosc calibration. Refactor
mt8173 and mt8183 code by extracting common API. Move rtc_read and
rtc_write to each SoC folder, because mt8173 and mt8183 access rtc via
pmic wrapper, while mt8192 accesses it via pmif.

Reference datasheet:
  Document No: RH-D-2018-0101.

Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: I57d6738fdec148c7458b2024a0a8225415ca2f3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-28 13:39:01 +00:00
Nina Wu 87c30a064c soc/mediatek/mt8192: devapc: add basic devapc drivers
Add basic devapc (device access permission control) drivers.

DAPC driver is used to set up bus fabric security and data protection
among hardwares. DAPC driver groups the master hardwares into different
domains and gives secure and non-secure property. The slave hardware can
configure different access permissions for different domains via DAPC
driver.

Change-Id: I2ad47c86b88047c76854a6f8a67b251b6a9d4013
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-28 13:38:38 +00:00
Huayang Duan 3960351141 soc/mediatek/mt8192: Do dramc pre-settings before calibration
Before calibration, dramc resets the delay of each PHY IO, calculates
TX path and sets CKE to be rank independent.

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-28 13:38:20 +00:00
Jack Rosenthal 32ed65611d kconfig: remove non-existent source
src/northbridge/amd/pi/00660F01/Kconfig does not exist.  Remove the
source statement.

Also, no kconfig files under src/soc/intel/common/basecode/.  Clean
that up.

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I10917b76ff6c2a9d5a97d5c7dfa9e8925cd8c8a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-12-28 13:37:56 +00:00
Benjamin Doron d0701c96f2 soc/intel/skylake: Enable CHAP device depending on devicetree
Now that CHAP device is declared in chipset devicetree, hook it up to
devicetree configuration.

Change-Id: Icc51f7b9cda32d5058dce958e386921b6d3d8ffb
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48323
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28 13:37:47 +00:00
Kyösti Mälkki b8cb142ccd sb/amd/pi/hudson: Enable use of common GPIO API
The code in soc/amd/common has an implementation of
GPIO register space that is compatible with the hardware
sb/amd/pi/hudson supports.

Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-28 13:37:15 +00:00
Felix Singer 219caf8358 mb/siemens/chili/base: Add SMBIOS slot descriptions
Add SMBIOS slot descriptions for M.2 ports and remove duplicate
comments.

Change-Id: Ieff03ad3167aec054cdc6b67ddc20fc64394e347
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-27 15:57:09 +00:00
Nico Huber c00ffef47c vpd: Add vpd_get_int() function
Change-Id: I1c1b5710a5236fe4a3bdda1fc978393e636e9817
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45773
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-27 15:33:24 +00:00
Idwer Vollering bdb37982d6 src/superio: trim and move Makefile.inc, instead use wildcard matches
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: If77d59485451c77dcea752bc4fe0dfadba8fec45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48900
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-27 14:46:07 +00:00
Angel Pons 7e3126dbc5 cpu/intel/model_206ax: Add more CPU steppings
The Sandy Bridge steppings appear in the BWG, and Ivy Bridge steppings
appear in reference code. Add them for the sake of completeness.

Change-Id: I7d17cdd04a771ca319c908fc757f868e95ea7944
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-25 22:01:00 +00:00
Angel Pons 47a80a045d nb/intel/sandybridge: Move steppings to CPU header
The steppings correspond to the CPUID bits 3:0, so move them to the CPU
scope, and include the CPU header from files using the stepping macros.

Change-Id: Idf8fba4911f98953bb909777aea57295774d8400
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48409
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-25 21:41:55 +00:00
Angel Pons 5db1b15147 nb/intel/sandybridge: Rewrite constant values
Rewrite some constants to make their meaning somewhat clearer.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.

Change-Id: I321f5e61d7c695ae77e61b84728e34930f69d400
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-25 21:41:28 +00:00
Angel Pons 3170e9c0ef nb/intel/sandybridge: Allow to ignore XMP voltage
Native raminit only supports 1.5V operation, but there are DIMMs which
request 1.65V operation in XMP profiles. Add an option to force XMP to
be used when the requested voltage isn't supported, which will run the
DIMMs at 1.5V with XMP timings. Consider this to be overclocking.

Change-Id: I64bfac8f72dadf662ceadfc7998daf26edf5a710
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-25 21:41:17 +00:00
Kyösti Mälkki e0183d6540 ACPI: Allocate GNVS early in ramstage
We need this to happen prior to SMM module loader. If
there is some debugging output it's better they do not
appear in the middle of CPU bringup.

Change-Id: I45b4b5c0c5bf8bee258a465d1e364bfe98190e44
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-25 02:29:14 +00:00
Kyösti Mälkki 61bc2191c3 ACPI: Fix some GNVS field comments
Change-Id: I0d1e7b86d5b98da85bf539a4a3ec23e0eeaa4dfc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-25 02:28:02 +00:00
Kyösti Mälkki e1b4be1470 sb,soc/intel: Fix GNVS OperationRegion
Structure with chromeos_acpi_t is expected to have size
0x1000. Only ones with device_nvs_t have size 0x2000.

Change-Id: I2eaa3a008566853b4144fa34ccffaa232d5d8e24
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-25 02:27:37 +00:00
FrankChu 39f582815d mb/google/dedede: Update galtic device tree
Update galtic device tree override to match schematics.

BUG=b:170913840
BRANCH=dedede
TEST=emerge-dedede coreboot

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I270cd2a9783030ad3a080b9cfda8a133e801c5ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-25 02:27:08 +00:00
Matt DeVillier 395ab9da93 soc/intel/common/gfx: rename and guard graphics_soc_init()
Rename to graphics_soc_panel_init, to more accurately convey
operations performed by the function. Guard execution so we
don't attempt to reconfigure the panel after FSP has already
done so.

This fixes FSP/GOP display init on APL/GLK, which was broken by
attempting to configure the panel after FSP had already done so.

Change-Id: I8e68a16b2efb59965077735578b1cc6ffd5a58f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48884
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-25 02:25:57 +00:00
Patrick Rudolph 09cdeba606 drivers/ipmi: Add Supermicro OEM commands
Add a new driver for OEM commands and select it from x11-lga1151-series.

The driver communicates the BIOS version and date to the BMC using OEM
commands. The command should be supported on all X11 series mainboards,
but might work with older BMC, too.

Tested on X11SSH-TF:
The BIOS version strings are updated on boot and are visible in the
BMC web UI.

Change-Id: I51c22f83383affb70abb0efbcdc33ea925b5ff9f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-25 02:25:49 +00:00
Sam Lewis 1c18f8679f Documentation: Add Beaglebone Black documentation
Change-Id: If1a9808d1f20ee61048182d416f25e9a81c631af
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-24 08:30:28 +00:00
Nico Huber 4f7b687fb7 libpayload/i8042: Add API to peek on keyboard input queue
Change-Id: I60699e044b5bacd3f5292fed7edbf529ae133284
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47592
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:29:18 +00:00
Nico Huber 6e021d31f9 libpayload/keyboard: Add debug output to all state transitions
Change-Id: I643a821d4c41fc068f2bab0bd571b0a4a359f59a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:29:07 +00:00
Nico Huber b2569eaa82 libpayload/keyboard: Hide console output by default
Change-Id: I855d975a4729da34a6fa73a63dbbd12c856bdc00
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:20:32 +00:00
Nico Huber e9c572f203 libpayload/keyboard: Implement self-test
The keyboard self-test is required for some devices. At least one
device (integrated keyboard in a ThinkPad X201) actually starts the
test automatically leading to spurious output and no response for
the first seconds.

We wait up to 5s for the self-test result. On failure or timeout,
the command will be repeated until the 30s init timer runs out. This
happens all in the background of the UI polling loop.

To not unnecessarily delay the boot process, we first try an oppor-
tunistic initialization which skips the self-test.

Change-Id: Ie07b31e74d06e116ac81e76309621eed39a19b49
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:20:16 +00:00
Nico Huber 777c599747 libpayload/keyboard: Add timestamp to track time spent in a state
Will be used to time out in states that don't always advance.

Change-Id: I28235e7638d8157cedf81fd915a41d28a1fc070b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47087
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:20:01 +00:00
Nico Huber 260dd9eb7e libpayload/keyboard: Turn init sequence into a state machine
We'll process the init sequence as part of the polling loop. This
should have several advantages:

* It eases error handling, i.e. we can return to an earlier state.
* We don't have to stall initialization when a keyboard takes a
  little longer.
* Generally, these keyboards can be hot-plugged (albeit not by
  design).

Change-Id: I9cf5cf31eb420b3994bec20e56a72d37f3d2996e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:19:48 +00:00
Nico Huber 828f6b428e libpayload/keyboard: Avoid races around input draining
Draining the keyboard's buffer is only possible when the keyboard
port is enabled. We should also disable input scanning before, as
the buffer could be filled again with new keystrokes otherwise.

Change-Id: Ibac9c0d04880ff4a3efda5ac53da2f9731f6602c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:19:18 +00:00
Nico Huber f7faac151a libpayload/keyboard: Introduce keyboard_drain_input()
Move the input-buffer draining into a function. It uses the low-level
i8042 API directly to avoid conflicts with changes in the high-level
keyboard API.

Change-Id: I9427c5b8be4d59c2ee3da12d6168d34590043682
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47084
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:18:57 +00:00
Nico Huber a160d93dda libpayload/keyboard: Revise keyboard_cmd() error handling
Even if we are careful, it's still possible that we read spurious
data from the keyboard, e.g. keystrokes. Namely, when we send the
reset/disable command, there is a race before the command is pro-
cessed.

So we should always process data from the keyboard in a loop. We
break it, when an ACK (0xfa) or a NAK (0xfe) is received, and warn
on unexpected data unless it might be due to the mentioned race.

This also gives us the opportunity to use command-specific timeouts
which we take from Linux: 1s for the keyboard self-test (as there
are keyboards that perform the test before acking the command) and
200ms for all other commands.

Change-Id: I60a2643a8ff4b9231c63bf970c8749c97c7d8926
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24 08:18:41 +00:00
Angel Pons f651022df3 mb/prodrive/hermes: Drop EEPROM address function parameters
Only one EEPROM is used to store the board settings, and its I2C address
is constant. Thus, there's no need to pass its address as a parameter.

In addition, reduce the scope of the `I2C_ADDR_EEPROM` definition, since
using it outside of eeprom.c would bypass the API's abstraction layer.

Change-Id: I958304e6ed6df05af923139d44ff4fd1de204738
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-24 08:17:05 +00:00
Angel Pons 707e03d8b9 mb/prodrive/hermes: Use already-defined SMBus macros
Drop chipset register definitions in mainboard code in favor of existing
definitions in a header. These definitions are not mainboard-specific.

Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.

Change-Id: I29d6f35ec27bff43cf52ae697e905b6a7b48a8d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-24 08:16:53 +00:00
Patrick Rudolph 3e4f4e0229 mb/supermicro/x11-lga1151-series: Select DRIVERS_UART_8250IO
Change-Id: I0251d1193bb36ae73d592a0d17f580b7edaddbf6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48853
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:16:37 +00:00
Kevin Chang 1cfc3a68e2 mb/google/volteer/variant/lindar: Add SSD D3 cold support
This patch add SSD D3 cold support for lindar.

BUG=b:172405687
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ie343bbff3bde4ff2a7e89bd384d5661af372b560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-24 08:16:28 +00:00
David Wu 9e2761fe2b mb/google/volteer/var/voema: Disable PCIe 7 and 8 for WLAN and SD card
Based on latest schematic, disable PCIe 7 and 8 for WLAN and SD card.

BUG=b:169356808
TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I2a4658a382c094c2a5b16b7acaf464f54e9897b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-24 08:16:19 +00:00
Felix Singer b8d614f8cc 3rdparty/fsp: Update submodule pointer to newest master
Newest master introduces the FSP for Tiger Lake client SKUs.

Change-Id: Id437faf72f1b8c5bc5310596bdab980e64614fa0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48712
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:16:05 +00:00
David Wu f0df12dd17 mb/google/volteer/var/voema: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control
of the NVMe device attached to PCIe Root Port 9.

Enable the GPIO for power control for variants that do not already have
it configured to allow the power to be disabled in D3 state.

BUG=b:169356808
TEST=tested on voema

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I28ef074225c533e1a97b6ec4a1a5dd1dcc198168
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48848
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:15:51 +00:00
Johnny Lin 749a78d179 soc/intel/xeon_sp/cpx: Disable isoch operation for performance
Isochronous operation negatively impacts memory performance, as
per Intel MLC (Memory Latency Checker) benchmark results. Thus,
disable isochronous operation, like analogous UEFI firmware does.
The MLC results after disabling isoch:

"--max_bandwidth"
ALL Reads :         106948.17
3:1 Reads-Writes :  101580.46
2:1 Reads-Writes :  100523.26
1:1 Reads-Writes :  99059.44
Stream-triad like : 97762.47

"--peak_injection_bandwidth"
ALL Reads :         105724.3
3:1 Reads-Writes :  100655.8
2:1 Reads-Writes :  99463
1:1 Reads-Writes :  98708
Stream-triad like : 91515

The MLC results before disabling isoch:

"--max_bandwidth"
ALL Reads :         88824.96
3:1 Reads-Writes :  94820.81
2:1 Reads-Writes :  94867.53
1:1 Reads-Writes :  92567.36
Stream-triad like : 91900.43

"--peak_injection_bandwidth"
ALL Reads :         88859.6
3:1 Reads-Writes :  94064
2:1 Reads-Writes :  94186.2
1:1 Reads-Writes :  92516.1
Stream-triad like : 85147.4

TEST=On OCP Delta Lake, verify that MLC benchmark results have
improved.

Change-Id: I08c22ee001b601e607452b3f23fad969ecb484b4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48738
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:15:43 +00:00
Sunway a858ec86e4 mb/google/kukui: Add a new config 'Katsu'
A new board introduced to Kukui family.

BUG=b:176206134
TEST=make # select Katsu
BRANCH=kukui

Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I09fe2b8f6922dfd2af6424830568466fb98f7aee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-24 08:14:06 +00:00
Marc Jones 3c13af7ec9 soc/intel/common: Remove unused SOC_INTEL_COMMON_ACPI
Remove the unused SOC_INTEL_COMMON_ACPI Kconfig option.

Change-Id: Id62cd44e0f7e4175ae65c9388569231d5c8c1fbc
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-23 19:03:58 +00:00
Marc Jones 5da265c53e src/soc/intel/xeon_sp/acpi.c: Remove unnecessary .h
Remove the unnecessary header file includes.

Change-Id: I0d849cb236f304b87332aa64b2f10c73cad2d4dd
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-12-23 19:03:38 +00:00
Angel Pons d4d3ba0414 nb/intel/sandybridge: Refactor ODT stretch table code
Leverage existing `ch_dimms` value and use constants for brevity.

Change-Id: I4e08166c8e9fbd15ff1dcd266abb0689e4b159f7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-23 16:22:37 +00:00
Angel Pons 323c0aeb64 nb/intel/sandybridge: Refactor `dram_find_spds_ddr3`
Pointers to structs can be very useful, especially when they point to an
array element. In this case, changing one pointer allows the function to
be rewritten more concisely, since most redundancy can be eliminated.

Tested on Asus P8Z77-V LX2, still boots. No functional difference.

Change-Id: I7f0c37ea49db640f197162f371165a6f8e9c1b9c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-23 16:14:45 +00:00
Angel Pons 9f4ed3b550 nb/intel/sandybridge: Always wait for IOSAV after starting it
Ensure that IOSAV is finished before continuing. This might solve some
random failures on the I/O and roundtrip latency training algorithm.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: Ic08a40346b6c60e372bada10f9c4ee42eb974f9f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48403
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:11:35 +00:00
Angel Pons a853e7acdb nb/intel/sandybridge: Introduce `iosav_run_once_and_wait`
Most ofte, `iosav_run_once` precedes a `wait_for_iosav` call. Add a
helper function to reduce clutter. The cases where `iosav_run_once`
isn't followed by `wait_for_iosav` will be handled in a follow-up.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: Ic76f53c2db41512287f41b696a0c4df42a5e0f12
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48402
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:10:53 +00:00
Angel Pons edd7cb4d67 nb/intel/sandybridge: Remove unnecessary comments
These comments were helpful before the massive IOSAV refactoring, but
they are no longer needed since the function names are clear enough.

Change-Id: Ieb9bdf3f7fc72f63a8978f2b98e0bc8228c55868
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48401
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:05:50 +00:00
Angel Pons 7e439c9a5d nb/intel/sandybridge: Print delays in decimal
Print delay values in a suitable format for human consumption.

Change-Id: I0d86187d3e458ee2cb3fd11ec896ac363b8d3249
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48400
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:05:26 +00:00
Angel Pons 4d192820cd nb/intel/sandybridge: Add comment to TC_RWP write
Change-Id: I164daa59696f2fe8de3a4b3e7da46c7c723778eb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48602
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:05:06 +00:00
Angel Pons 30791639f8 nb/intel/sandybridge: Use proper names to refer to training steps
Now that the purpose of each training algorithm is clear, replace the
last instances of the original names in comments and print statements
with the current, correct names. Also, print which channel has failed
command training, for completeness and consistency with other errors.

Change-Id: I9cc5c4b04499297825ca004c6bd1648a68449d2c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48601
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:04:43 +00:00
Angel Pons 3aed6ac613 nb/intel/sandybridge: Add comments about I/O and RT latency
Document the algorithm to adjust I/O and roundtrip latencies.

Change-Id: Ic8b9aed54a34bb3252c457e87e81387fd410e305
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48397
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:04:22 +00:00