Commit Graph

30712 Commits

Author SHA1 Message Date
Elyes HAOUAS f2e1d0ae9a soc/cavium/common/Makefile: Convert STACK_SIZE value to decimal
STACK_SIZE value needs to be changed from hex to decimal,
since -Wstack-usage doesn't recognize hexadecimal numbers anymore.

Change-Id: I73606d347194af5de5882a3387a4a5db17f9d94b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04 16:27:36 +00:00
Elyes HAOUAS 496fedfa2a mb/intel/{galileo,wtm2}: Use macro instead of magic number
Change-Id: Ib8a08e9f854b2b0786c69943d6dbb66abe3ad4d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33438
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04 16:26:38 +00:00
Hung-Te Lin b763b37411 mb/google/kukui: Extend FMAP to 8MB layout
The SPI flash component requirement for Kukui family is 8M so we should
update FMAP for that:

- Add more comments for alignment and size recommendation.
- Enlarge RO to 4M, and RW_SECTION_{A,B} both ~1.5M.
- BOOTBLOCK: 32K->128K, aligned with other ARM boards.
- Preserve RW_DDR_TRAINING for new calibration.
- Reorder the sections for better alignment.
- RW_MISC to contain RW sections that should be merged when creating AU image.

BUG=b:134624821
TEST=Built Kukui image and boots. dump_fmap -h image-kukui.bin:
     # name              start       end         size
     RW_LEGACY           00700000    00800000    00100000
     RW_SHARED           006f7000    00700000    00009000
       RW_UNUSED           006f8000    00700000    00008000
       SHARED_DATA         006f7000    006f8000    00001000
     RW_SECTION_B        00580000    006f7000    00177000
       RW_FWID_B           006f6f00    006f7000    00000100
       FW_MAIN_B           00582000    006f6f00    00174f00
       VBLOCK_B            00580000    00582000    00002000
     RW_MISC             00577000    00580000    00009000
       RW_ELOG             0057f000    00580000    00001000
       RW_DDR_TRAINING     0057d000    0057f000    00002000
       RW_NVRAM            0057b000    0057d000    00002000
       RW_VPD              00577000    0057b000    00004000
     RW_SECTION_A        00400000    00577000    00177000
       RW_FWID_A           00576f00    00577000    00000100
       FW_MAIN_A           00402000    00576f00    00174f00
       VBLOCK_A            00400000    00402000    00002000
     WP_RO               00000000    00400000    00400000
       RO_VPD              003f8000    00400000    00008000
       RO_SECTION          00000000    003f8000    003f8000
         RO_FRID             003f7f00    003f8000    00000100
         GBB                 003f5000    003f7f00    00002f00
         COREBOOT            00021000    003f5000    003d4000
         FMAP                00020000    00021000    00001000
         BOOTBLOCK           00000000    00020000    00020000

Change-Id: Id342d57dc95c6197d05b8a265742a2866c35ae09
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-04 16:25:56 +00:00
Frans Hendriks b3d597b1dd mb/facebook/fbg1701: Remove ONBOARD_MICRON_MEM
ONBOARD_MICRON_MEM and ONBOARD_SAMSUNG_MEM are available.
These are used to determine if Samsung or Micron onboard memory is
assembled. This can not detected run-time.

Choice is replaced by one config.
Only oldest HW revision contains Samsung module, so set
CONFIG_ONBOARD_SAMSUNG memory to default No.

BUG=N/A
TEST=Boot and verified on Facebook FBG-1701

Change-Id: Id65e92bd4b8d4fe3a6b87dec9bf77e3a62e1be96
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-04 16:25:17 +00:00
Michael Niewöhner 258f52b520 mb/supermicro/x11-lga1151-series: rework documentation
This splits the x11-lga1151-series' documentation into a generic and a
board specific section as a preparation for CB:35427.

Additionally this adds some more information on the x11ssh board.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I40ddd0b5cce0b1a3306eae22fc0a0bc6b2a6263c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-04 16:24:59 +00:00
Frans Hendriks b71181adc3 device/pci_device.c: Use verified boot to check oprom
Before oprom is executed, no check is performed if rom passes verification.
Add call to verified_boot_should_run_oprom() to verify the oprom.

verified_boot_should_run_oprom() expects and rom address as input pointer.
*rom is added as input parameter to should_run_oprom() which must be parsed
to verified_boot_should_run_oprom()..

BUG=N/A
TEST=Created verified binary and verify logging on Facebook FBG1701

Change-Id: Iec5092e85d34940ea3a3bb1192ea49f3bc3e5b27
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-04 16:24:44 +00:00
Maxim Polyakov 9d68cb2144 soc/skl/vr_config: fix KBL-U GT3 detection bug
Some VR parameter values for KBL-U with GT3 graphics are different from
values for other CPUs in this series [1]. However, GT3 iGPU will never
be detected, since the igd_id variable is compared with the LPC device
PCI ID. The patch fixes this bug.

[1] page 109, 7th Generation Intel(R) Processor Families for U/Y
    Platforms and 8th Generation Intel(R) Processor Family for U Quad
    Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019.
    Document Number: 334661-006

Change-Id: I33527d90550a1de78c9375d3d3b0e046787a559b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-04 16:23:32 +00:00
Maxim Polyakov 723591376e soc/skl/vr_config: fix GT Loadline for KBL-U/GT3
According to the documentation[1], the Loadline in the unslased GT VR
domain should be 2 mOhms for KBL-U (2 Core, GT3 + OPC).

[1] page 109, 7th Generation Intel(R) Processor Families for U/Y
    Platforms and 8th Generation Intel(R) Processor Family for U Quad
    Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019.
    Document Number: 334661-006

Change-Id: I433036e76d456a725ab27cf57c9bc2fe01a7ace1
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35781
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04 16:23:17 +00:00
Maxim Polyakov 8595469093 src/pci_ids: add missing Intel Kaby Lake iGPU PCIIDs
Adds missing Intel HD/Iris iGPU PCI IDs for Kaby Lake processors and
updates the platform report for these devices.

These changes are in accordance with the documentation:
[*] page 10, Intel(R) Open Source HD Graphics and Intel Iris(TM) Plus
    Graphics for the 2016 - 2017 Intel Core(TM) Processors, Celeron(TM)
    Processors, and Pentium(TM) Processors based on the "Kaby Lake"
    Platform. Programmer's Reference Manual. Volume 4: Configurations.
    January 2017, Revision 1.0
    Doc Ref # IHD-OS-KBL-Vol 4-1.17
[*] Linux kernel sources: include/drm/i915_pciids.h

Change-Id: I1cd1e4ab82f756141f8f13edf1c17f726166dffb
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-04 16:22:35 +00:00
Maxim Polyakov 95636813a4 src/pci_ids: add missing Intel Skylake iGPU PCIIDs
Adds missing Intel HD/Iris iGPU PCI IDs for Skylake processors

These changes are in accordance with the documentation:
[*] page 11-12, Intel(R) Open Source HD Graphics, Intel Iris(TM)
    Graphics, and Intel Iris(TM) Pro Graphics, Programmer's Reference
    Manual. Volume 4: Configurations. May 2016, Revision 1.0
    Doc Ref # IHD-OS-SKL-Vol 4-05.16

Change-Id: I0ba6e58ec3916dceea00519ac5a51503573e8935
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35493
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04 16:22:16 +00:00
Maxim Polyakov b4383fc759 soc/skl/vr_config: set Iccmax_gt depends on CPU/GT
According to the DC Current Specifications [1], the current limit for
the graphical VR domain (Iccmax_gt) isn't same for different Kaby Lake S
CPUs. This value should depend on the iGPU model and processor TDP:

  +---------------------+-----+------------+
  |       Segment       | TDP | Icc_max GT |
  +---------------------+-----+------------+
  | Dual Core GT2/GT1   | 35W |            |
  | Dual Core GT2       | 51W |    48 A    |
  | Dual Core GT1       | 54W |            |
  +---------------------+-----+------------+
  | Quad Core GT2       | 35W |    35 A    |
  +---------------------+-----+------------+
  | Quad Core GT2       | 65W |    45 A    |
  | Quad Core GT2 K-SKU | 91W |            |
  +---------------------+-----+------------+

This patch adds the remaining Iccmax_gt current limit values from the
documentation [1].

[1] 7th Generation Intel(R) Processor Families for S Platforms and
    Intel(R) Core(TM) X-Series Processor Family Datasheet, Volume 1,
    December 2018, Document Number: 335195-003

Change-Id: I19766e4f8fab6b48565b65ed4cf13efbc213e654
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-04 16:21:43 +00:00
Frans Hendriks 33ed3ebf6a mb/facebook/fbg1701: Add measured boot support
No support is available in mainboard.
Add support to mainboard:
- Add mb_log_list[]
- Add routine mb_crtm()

BUG=N/A
TEST=Boot Embedded Linux 4.20 and verify logging on Facebook FBG-1701

Change-Id: I5120ffb6af0b41520056e1773f63b7b2f34a2460
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-10-04 13:39:09 +00:00
Frans Hendriks 744c70dcc7 mb/facebook/fbg1701: Add verified boot tables
The vendorcode for verified boot is uploaded, but not used by a mainboard.
Add support to the mainboard for verified boot.

The items to be verifed are placed in board_verified_boot.c

BUG=N/A
TEST=Boot Embedded Linux 4.20 and verify logging on Facebook FBG-1701 rev 0-2

Change-Id: I3ea0a95287977df0dea13e05acedd5406538a6ee
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33463
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04 13:38:25 +00:00
Frans Hendriks 72b3c3c838 vendorcode/eltan/security/verified_boot: Add verified boot support
Create verified boot support, which includes verifiication of bootblock.
This feature use the vendorcode/eltan/security/lib.

cbfs_locator is used to init the verified boot support.
vendor_secure_prepare() and vendor_secure_locate() are used to preform the
required action in each stage.

The next lists will be used for verification:
 * bootblock_verify_list
 * postcar_verify_list
 * romstage_verify_list
 * ramstage_verify_list

BUG=N/A
TEST=Created binary and verify logging on Facebook FBG-1701

Change-Id: If6c1423b0b4a309cefb7fe7a29d5100ba289e0b4
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-04 13:37:03 +00:00
Frans Hendriks 7c82dbcc51 vendorcode/eltan/security/mboot: Add measured boot support
Create measured boot.
This feature uses the vendorcode/eltan/security/lib.
Measure boot can work with and without Verified boot enabled.

The function mb_measure() is starting point for the support. This
function will be called by the common Verified boot code.

BUG=N/A
TEST=Created binary and verify logging on Facebook FBG-1701

Change-Id: I7f880a17e240515dd42d57383b5ddddf576985b0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-04 13:36:13 +00:00
Patrick Rudolph cfe08ff197 arch/x86/acpi: Add SSDT for QEMU
Add a SSDT on qemu and place BOOT0000 inside it to allow testing
the google firmware kernel module in qemu.

Tested on Qemu Q35.

Change-Id: Ibd1b2c2f4fc3db9ae8f338b0d53b2d00ea2c4190
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HIMANSHU SAHDEV <sahdev.himan@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-04 06:44:44 +00:00
Patrick Georgi 8be1fdf26f Update arm-trusted-firmware submodule to upstream master
Updating from commit id 42cdeb93:
2019-09-13 12:09:21 +0000 - (Merge "stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver" into integration)

to commit id ace23683:
2019-09-27 09:54:27 +0000 - (Merge changes from topic "ld/stm32-authentication" into integration)

This brings in 83 new commits.

Change-Id: I273b5014db76d307d8735d78a8fdd5db3d07146c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-03 18:30:08 +00:00
Kyösti Mälkki 5a2bbcaa93 cpu/intel/: Fix regression with smmrelocate
Fix regression with commit d53fd70 intel/smm/gen1: Use smm_subregion().

The bitmask on SMRR register parameter was inverted for
selected models.

Change-Id: Ia572ca3bdd4da371985691b5d249f998382fbe48
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-03 15:34:13 +00:00
Martin Roth 30d3c9ed48 ec/google/chromec: Default EC_GOOGLE_CHROMEEC_LPC to disabled
Don't set a default bus type for the Chrome EC on x86.  The platform
must select the bus, typically  LPC or ESPI.

BUG=b:140055300
TEST=Build tested only

Change-Id: I736cb9e43292a1b228cd083ca81a8e5db383e878
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-03 15:30:12 +00:00
Martin Roth dcf86e0cff mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPI
Previously all boards using eSPI for the Chrome EC just called it
LPC as the code for the chrome EC is the same between the two
busses.

I'm adding a new Kconfig symbol to specify eSPI, so switch the
boards that actually use eSPI to that symbol and add the LPC
symbol to all the others.

The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default
to enabled for x86 platforms, so one symbol or the other needs to be
specified for each platform.

BUG=b:140055300
TEST=Build tested only.

Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-03 15:29:53 +00:00
Mathew King d8b150f0d5 southbridge/intel: Add config option to validate firmware descriptor
Add new config option to validate the Intel firmware descriptor against
the fmap layout. This will prevent a firmware descriptor from being used
that could corrupt regions of the bootimage in certian circumstances.

BUG=chromium:992215
TEST=Build firmware image with mismached decriptor and fmp
     Without VALIDATE_INTEL_DESCRIPTOR set firmware builds
     With VALIDATE_INTEL_DESCRIPTOR set error is shown with mismached
     regions

Change-Id: I9e8bb20485e96026cd594cf4e9d6b11b2bf20e1f
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 15:28:58 +00:00
Mathew King c7ddc999fc ifdtool: Add validate option to ifdtool
Add an option to ifdtool which validates that the flash regions defined
in the descriptor match the coresponding areas in the FMAP.

BUG=chromium:992215
TEST=Ran 'ifdtool -t' with a good bios image and verify no issues
     run 'ifdtool -t' with a bad bios image and verify expected issues

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Idebf105dee1b8f829d54bd65c82867af7aa4aded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 15:28:15 +00:00
Patrick Georgi 006eb9d8c8 libpayload: refactor fetching cbmem pointers
There's a recurring pattern of reading cbtable entries that point into
cbmem entries. Move that pattern into its own function.

Coccinelle patch used for this:
  @@
  identifier T, T2;
  expression TARGET;
  @@
  -struct cb_cbmem_tab *const T2 = (struct cb_cbmem_tab *)T;
  -TARGET = phys_to_virt(T2->cbmem_tab);
  +TARGET = get_cbmem_ptr(T);

Change-Id: I7bd4a7ad8baeeaebf0fa7d4b4de6dbc719bc781f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 15:27:30 +00:00
Petr Cvek c49869b424 sb/intel/i82801gx: Use symbolic name for register, code rework
An original code had a wrong register address 0x27 for AHCI BAR.
The value was aligned incidentally by the code specific of
the pci_read_config32 function to the correct address 0x24.

All 0x24 values in sata.c were changed to the symbolic name
PCI_BASE_ADDRESS_5 and the code was optimized.

An equivalent code was tested on a real hardware.

Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35737
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03 15:24:42 +00:00
Frans Hendriks be81685887 mb/facebook/fbg1701/devicetree.cb: Use 64MB framebuffer size
Connected 4K monitor is not configured at max resolution. The
framebuffer size is too small.

Increase the framebuffer size to 64MB. This is sufficient for max
configuration of 1 HDMI monitor combined with internal LCD panel.

BUG=N/A
TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701

Change-Id: I25d2cd696830fc5bda84ea2b87538f526373998e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-03 14:06:21 +00:00
Frans Hendriks f26a1985bf soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMB
Add defines to have some more readable code for devcietree.cb.

BUG=N/A
TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701

Change-Id: Ifc1a7657a528d1fc570dd16df66b078e37e014cb
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-03 14:05:53 +00:00
Frans Hendriks 0b20b83b7d mb/facebook/fbg1701: Add mainboard_read_pcb_version()
PCB version is determined using inb() in actual code.

Create function mainboard_read_pcb_version to read pcb version.

BUG=N/A
TEST=Boot and verified on Facebook FBG-1701

Change-Id: I7c16627f468d84ca4ad2aab8bf9fb555f50dc23c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-03 14:04:35 +00:00
Patrick Georgi 22f009901d Update chromeec submodule to upstream master
Updating from commit id 860fe2962:
2018-12-29 05:45:29 -0800 - (mt_scp/ipi: Support host command.)

to commit id a1afae4e0:
2019-10-02 11:47:45 +0000 - (juniper: initial setup)

This brings in 1723 new commits.

Change-Id: Ieb4f00b21a4354bb634c3427c73260123b54ac2a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 04:43:36 +00:00
Patrick Georgi 4685e53fe6 Update opensbi submodule to upstream master
Updating from commit id ce228ee:
2019-07-02 11:11:08 +0530 - (include: Bump-up version to 0.4)

to commit id e561c63:
2019-10-02 17:03:58 +0530 - (lib: Fix coldboot race condition observed on emulators/simulators)

This brings in 44 new commits.

Change-Id: Ide6e3c2bb98e79750b40a9b8ca9f2f1d2c123628
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 04:43:28 +00:00
Patrick Georgi 193eefb2e8 Update vboot submodule to upstream master
Updating from commit id e6700f4c:
2019-08-13 04:36:52 +0000 - (vboot: update vboot2 functions to use new vb2_error_t)

to commit id b2c8984d:
2019-10-01 06:01:59 +0000 - (vboot: fix compile error with MOCK_TPM)

This brings in 71 new commits.

Change-Id: Id7cefa3ad5b30c955d18e469494fec32f6f58a48
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 04:43:17 +00:00
Kyösti Mälkki d46bc60413 intel/fsp_baytrail: Drop some PCI scratchpad register definitions
These were unused and somewhat cryptic, assumed purpose was to store
pre-CBMEM timestamps in various PCI config space locations.

Change-Id: I074294446501d49a9bd3c823a2a794c33f443168
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35731
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03 03:12:31 +00:00
Martin Roth ce005dac68 util/release: add gerrit stats script
This tool downloads, caches and analyzes commits pushed to gerrit
for a specified range of commits.  Currently it only works over SSH.

Data that is printed about the range of commits:
CSV Data about each individual commit:
- Commit ID
- Commit Date
- Author
- Commiter
- Submitter
- Lines added
- Lines removed
- Title
- Reviewers

It then prints the analysis it did on the data:
- Total Commits
- Total lines added
- Total lines removed
- Total difference
- Authors - Number of commits
- Total Authors
- Authors - Lines added
- Authors - Lines removed
- Reviewers - Number of patches reviewed
- Submitters - Number of patches submitted

The script relies on a number of perl modules
which must be installed separately.

Change-Id: I74896a97b5fe370c0b08562ac85d29435e438a31
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/14225
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 02:12:45 +00:00
Stefan Reinauer f5fa96f9c3 buildgcc: Run aclocal before configure
Ubuntu 19.04 will fail looking for aclocal-1.15 if the scripts
are not regenerated because 19.04 ships with 1.16.
There are not enough eyes to roll when working with GNU autotools.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4aa9f520499930ffc984ab0b0144c9c6b2e544a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03 02:06:35 +00:00
Martin Roth f47c32a12d util/crossgcc: Add patch for __alloca missing on ubuntu 18.04
Bring this over from the HEADS repo.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I36dc9860f4c4a2675fd3fa24fa3e534215ceb43e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 02:06:30 +00:00
Kyösti Mälkki da33b75e7d intel/quark: Drop xx_DEV_FUNC
Intel adopted xx_DEVFN_xx naming for macros expanding to
PCI_DEVFN() starting with apollolake. The ones named
xx_DEV_FUNC are being renamed, or dropped, if they
were generally not used at all for a platform.

Change-Id: Ice1062d10b793dcbeb5b2ce9e2788fd3b6b6250b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02 20:14:27 +00:00
Kyösti Mälkki 85b6c66c83 intel/skylake: Refactor IRQ assignments
When creating the IRQ routing, referenced device and
function number are always of the same PCI device.

Change-Id: Ifc4795245187f8d70650242a56e6ce771ef2167a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35735
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02 20:13:55 +00:00
Kyösti Mälkki 0b4298c242 intel/pci_devs: Regroup PCI xx_DEVID entries
Change-Id: I953e9a7746232b4c40deca55eb6cb3bd7af91496
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02 20:13:24 +00:00
Furquan Shaikh 3d4923d85a libpayload: Add fmap_cache to sysinfo_t
Now that FMAP is cached in CBMEM and its pointer is added to coreboot
table for quick lookup, this change adds a new member "fmap_cache" to
sysinfo_t that can be used by payloads to get to FMAP cache.

BUG=b:141723751

Change-Id: If894c20c2de89a9d8564561bc7780c86f3f4135a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02 11:26:53 +00:00
Thejaswani Putta 86cb421df6 mb/google/drallion: Disable GBE in firmware for drallion variants
BUG: None
TEST: Build successful, checked the CBMEM log if 1f.6 is disabled with this patch

Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com>
Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35509
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02 11:23:45 +00:00
Kyösti Mälkki 459f493486 intel/baytrail: Replace config_of(dev) with config_of_soc()
The function does not otherwise need dev.

Change-Id: I75d3283b537151258ed48f7e4e0991dff53a803c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35670
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02 11:21:27 +00:00
Kyösti Mälkki d5f645c6cd soc/intel: Replace config_of_path() with config_of_soc()
The previously provided device path made no difference, all
integrated PCI devices point back to the same chip_info
structure.

Change reduces the exposure of various SA_DEVFN_xx and
PCH_DEVFN_xx from (ugly) soc/pci_devs.h.

Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02 11:21:10 +00:00
Himanshu Sahdev d3d38c95b7 coreinfo/coreinfo.c: Support both lower and upper case alphabets
Modify handle_category_key to handle both upper and lower case alphabets
in the coreinfo payload.

Change-Id: I3ccbf69e90ba7824ad6ec85d2ca59aa8f40b3006
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-02 11:20:06 +00:00
Eric Lai 0f47ff1be5 mb/google/drallion: Dynamicly disable memory channel
Disable memory channel by HW strap pin. Using for factory
debug.

BUG=b:139773082
BRANCH=N/A
TEST=Rework HW strap pin and check /proc/mem_info

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35241
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02 11:19:23 +00:00
Yu-Ping Wu cf9588040d mediatek/mt8183: Rename fields of struct sdram_params
Two fields of struct sdram_params are renamed for future CL of DRAM full
calibration. Field 'impedance' is also removed.

BUG=none
BRANCH=none
TEST=emerge-kukui coreboot

Change-Id: I2f9673fd5ea2e62ee971f0d81bdd12aaf565e31c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35738
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02 11:17:25 +00:00
Arthur Heymans 4c80425f30 sb/intel/common/smihandler: Hook up smmstore
TESTED on Asus P5QC.

Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30012
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02 11:15:30 +00:00
Michael Niewöhner 6238563b2b soc/intel/skylake: devicetree: introduce PchHdaVcType fsp parameter
Make the the FSP Parameter PchHdaVcType a devicetree setting and make
use of it in the devicetrees of all boards that currently set it.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2019-10-02 11:15:00 +00:00
Richard Spiegel 5387144a93 Documentation/mainboard/amd: Add padmelon documentation and images
Create documentation on padmelon, including how to program the SPI. Also
include an index.md pointing to the documentation, as currently there's no
maiboard documentation folder for AMD.

BUG=none.
TEST=none.

Change-Id: I1a684c1acd3fb9441df71e2bc0fffa6131148b98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-01 15:15:30 +00:00
Richard Spiegel 6453c9062b Documentation/soc/amd: Add Family 15h
Create documentation for AMD Family 15h.

BUG=none.
TEST=none.

Change-Id: Iaab4edc431329a691283121494595f3797c566c6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-10-01 15:13:29 +00:00
Hsin-Hsiung Wang 9168ab0077 mediatek/mt8183: Allow modifying vcore voltage
Because vcore is the power of ddrphy in the soc, DRAM DVFS needs to be
calibrated with different vcore voltages to get correct parameters.
A new API is added to allow changing vcore voltage.

BUG=b:80501386
BRANCH=none
TEST=measure vcore voltage with multimeter

Change-Id: Ic43d5efe7e597121775dc853a3e2a08ebc59657d
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33391
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-01 15:11:29 +00:00
Patrick Rudolph 6e079dc120 cpu/intel/common: Move intel_ht_sibling() to common folder
Make intel_ht_sibling() available on all platforms.

Will be used in MP init to only write "Core" MSRs from one thread
on HyperThreading enabled platforms, to prevent race conditions and
resulting #GP if MSRs are written twice or are already locked.

Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-01 15:10:16 +00:00