Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface
in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is
enumerated.
Change-Id: Ic700021d7a09be63ffc2715f31992257e2e893af
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50898
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
update the DPTF parameters received from the thermal team.
BUG=b:181627614
TEST=emerge-ambassador coreboot
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ied6b71d9285662a70446af2e781b630e184c3b19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joe Tessler <jrt@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
There is no PCI host interface for Cnvi BT in Alderlake.
CNVi BT on Alderlake is an USB device.
Change-Id: I3e08c6d6f00e81267dc28c9b37b2dfff5cd75db1
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51352
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the CNVi BT PCI config and add Bt flag.
There is no PCI host interface in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS.
Change-Id: I7e8ca1bb6a57721a72478137612d7a9c391ca0b2
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Remove the CNVi Bt PCI config and add Bt flag.
There is no PCI host interface in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS.
Change-Id: I17c3e2761f91fb397d140d1954b6d4b451c4c603
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
FSP has added the Cnvi BT Core enabling in addition to the existing
CnviMode. This change adds the flag at the soc config side (i.e.
soc_intel_tigerlake_config for devicetree). Also, there is no longer PCI host
interface for BT. Therefore, BT core should not use the pci port status to turn
on/off.
TEST: BT enumeration is checked using 'lsusb -d 8087:0026' from OS to make
sure BT is turned on.
Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
making the symbols common accross targets to avoid duplicates for each soc.
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ic60f46891dfadc7db5ece02756cb449aacdd63c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
From ALSA reviewer suggest to change the name to RTL1015.
Details in below threads:
https://www.spinics.net/lists/alsa-devel/msg123395.html
BUG=b:177971830
TEST=: ALC1015P driver can probe properly.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2762852bdc3164346e3618c373aa4d3336415653
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Missing acpi_dp_write and correct the name from sdb to sdb-gpios for
driver.
BUG=b:177971830
TEST: ALC1015P driver can get sdb-gpio properly.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2728a7dad695d5c97e85c5d86b1effea1595da65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51379
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use VPD of "coreboot_uart_io" to select uart io if
OVERRIDE_UART_FOR_CONSOLE is selected.
Tested=On OCP Delta Lake, console messages correctly output to uart
port which is defined in VPD.
Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Change-Id: I55a85d6f137ef1aba95466e7b094740b685bf9bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Create the collis variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:182227204
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_COLLIS
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ibcf8b59b38d02517cea0a3ee474ff82fc0a2a958
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Add support to pick the right vbt from cbfs according to
SKU-ID.
Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Override SMBIOS type 2 board feature flags. For Delta Lake, board is
replaceable and is a hosting board.
Tested=Execute "dmidecode -t 2" to check info is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I4469360ec51369dbf8179b3cbac0519ead7f0382
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
This patch overrides the get_wifi_sar_cbfs_filename()
to return different sar table according to the sku id.
BUG=b:173465272
TEST=checked bios log and the correct sar table was loaded.
Change-Id: Ia30d760b1a029197d470818c73bfd2c00514652d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use gpio_keys driver to add ACPI node for pen eject event.
Also setting gpio wake pin for wake events.
BUG=b:175519097
BRANCH=firmware-volteer-13672.B
TEST=build and verify on a Copano
Change-Id: Id0a132aa398abde4983af123d00e355ac61839a8
Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51249
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Lindar/Lillipup uses the WIFI_SAR_ID field in FW_CONFIG to pick which
SAR table to load.
BUG=b:178302811
BRANCH=volteer
TEST=build and test no lindar/lillipup
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ibe829062033ba8246b9d9550cdcdc360f5f67dd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Add FW_CONFIG WIFI_SAR_ID fields in devicetree.
BUG=b:178302811
BRANCH=volteer
TEST=build and test on lindar/lillipup
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I7ec37b80ffca6924f1f0952dcfbc43c378a70923
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51386
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fleex will use SSFC to support RTL5682.
BUG=b:178653122
TEST=abuild
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icb06eabe297c5562bd2171b52cc9671c342e6dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Update GPP_A10 and GPP_H17 configuration to meet LTE power sequence
specification.
- FCPO (GPP_A10) should not turned off during warm reset.
BUG=b:177177967
BRANCH=dedede
TEST=Verified LTE power signal waveforms during powering on and off
Change-Id: I469f9c94ebd6bf2b68a0edc74f229158d82d0ef8
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
I was bugged by spurious "Failed to enable LTR" messages for years.
Looking at the the current algorithm, it is flawed in multiple ways:
* It looks like the author didn't know they implemented a
recursive algorithm (pciexp_enable_ltr()) inside another
recursive algorithm (pciexp_scan_bridge()). Thus, at every
tree level, everything is run again for the whole sub-
tree.
* LTR is enabled no matter if `.set_ltr_max_latencies` is
implemented or not. Leaving the endpoints' LTR settings
at 0: They are told to always report zero tolerance.
In theory, depending on the root-complex implementation,
this may result in higher power consumption than without
LTR messages.
* `.set_ltr_max_latencies` is only considered for the direct
parent of a device. Thus, even with it implemented, an
endpoint below a (non-root) bridge may suffer from the 0
settings as described above.
* Due to the double-recursive nature, LTR is enabled starting
with the endpoints, then moving up the tree, while the PCIe
spec tells us to do it in the exact opposite order.
With the current implementation of pciexp_scan_bridge(), it is
hard to hook anything in that runs for each device from top to
bottom. So the proposed solution still adds some redundancy:
First, for every device that uses pciexp_scan_bus(), we enable
LTR if possible (see below). Then, when returning from the bus-
scanning recursion, we enable LTR for every device and configure
the maximum latencies (if supported). The latter runs again on
all bridges, because it's hard to know if pciexp_scan_bus() was
used for them.
When to enable LTR:
* For all devices that implement `.set_ltr_max_latencies`.
* For all devices below a bridge that has it enabled already.
Change-Id: I2c5b8658f1fc8cec15e8b0824464c6fc9bee7e0e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51328
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since no board overrides the weak get_gpe_table function,
gpe_configure_sci wasn't called for any variant, so drop the function.
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3de204cc808449b625e1fa1e79fe653608e4b88a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
This change select the Kconfig to pre-allocate the Intel-recommended bus
and memory resources per-PCIe TBT root port for the adlrvp mainboard.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic56ebab02e50a466662a07d122d8f40eaf16b54b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change select the Kconfig to pre-allocate the Intel-recommended bus
and memory resources per-PCIe TBT root port for the brya0 mainboard.
TEST=snippet from dmesg logs shows the correct resources being allocated:
PCI: 00:07.0 resource base 27fc00000 size 1c000000 align 20 gran 20 limit 29bbfffff flags 60181202 index 24
PCI: 00:07.0 resource base 83000000 size c200000 align 20 gran 20 limit 8f1fffff flags 60080202 index 20
PCI: 00:07.1 resource base 29bc00000 size 1c000000 align 20 gran 20 limit 2b7bfffff flags 60181202 index 24
PCI: 00:07.1 resource base a0000000 size c200000 align 20 gran 20 limit ac1fffff flags 60080202 index 20
PCI: 00:07.2 resource base 2b7c00000 size 1c000000 align 20 gran 20 limit 2d3bfffff flags 60181202 index 24
PCI: 00:07.2 resource base ac200000 size c200000 align 20 gran 20 limit b83fffff flags 60080202 index 20
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6b520ae50f19a730263de7918594718f3b4b1c1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51455
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Intel ADL BIOS specification #627270 recommends reserving the
following resources for each PCIe TBT root port:
- 42 buses
- 192 MiB Non-prefetchable memory
- 448 MiB Prefetchable memory
Add a mainboard Kconfig which will auto-select these recommended values,
in addition to PCIEXP_HOTPLUG.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icdfa2688d69c2db0f98d0523d5aba42eec1824db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51460
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The _DSD is generated at runtime using the Intel common pcie
driver, therefore remove it from the ASL files.
BUG=b:182522802, b:182478306
TEST=boot into latest kernel, no thunderbolt driver errors
seen
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iee25a77bf5cc6636f46a5c32f3eeabe8524e0a04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51454
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The _DSD is generated at runtime using the Intel common USB4
driver, therefore remove it from the ASL files.
BUG=b:182522802, b:182478306
TEST=boot into latest kernel, no thunderbolt driver errors
seen
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I77dc283aeb5f52191255137e941487cf68cb7970
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51453
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Done for consistency with other platforms. This also drops redundant S3
resume logging, as `southbridge_detect_s3_resume` already prints it.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: Id96c5aedad80702ebf343dd0a351fbd4e7b1c6c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The `HPET_ADDRESS` Kconfig option has the same value. Use it instead.
Change-Id: I268e949d4396aa20e38f719b36cc4e6226efe082
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This reverts commit 87a1bd696d.
Reason for revert: skin temperature is overheating due to boost time is too long
BUG=b:175364713
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I31db06f4bcb986398e7bd2ac2858ffbedb257e2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
MT8192 devapc supports remapping domains.
There may be different domain bit for different subsys.
For example, domain bit in INFRA is 4-bit, while in MMSYS,
domain bit is 2-bit. For INFRA master to access MM registers,
the domain bit will change from 4 to 2 and need to be remapped.
In this patch we have remapped:
1. TINYSYS (3-bit to 4-bit)
- domain 3 to domain 3
- others to domain 15
2. MMSYS slave (4-bit to 2-bit)
- domain X to domain X, for X = 0 ~ 3
- others to domain 0
Change-Id: Id10a4c0bdf141cc76a386159896c861d0dc302aa
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The SKU ID for Asurada should come from AP ADC channel 5 and 6.
BUG=None
TEST=make; boots on asurada
Change-Id: I6a00c555f20aca4cd7f8bcee46ee81c17ef6ca3c
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Move the initialization from bootblock to romstage for following reasons:
- Follow MT8183 initialization sequence.
- PMIC and RTC functions are only called after verstage.
- Reduce bootblock size.
- PMIC initialization setting is complex and may need to be changed by
an RW firmware update.
TEST=boot to kernel successfully
Change-Id: I3e4c3f918639590ffc73076450235771d06aae91
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xi Chen <xixi.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Updating from commit id 3b1a734:
2021-03-02 11:51:18 -0700 - (picasso: Update FSP to build 0x26)
to commit id 3a9d7cd:
2021-03-03 15:37:08 -0700 - (picasso: Update Dali SMU firmware)
This brings in 1 new commits.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iff3b4ff667f97d3804bc66477f8a95a60e23b1a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51459
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 4fdfa1c:
2021-03-05 13:10:22 -0600 - (mb/amd/majolica: Update to use proper APCBs built for Majolica)
to commit id fc2d4e2:
2021-03-12 10:31:48 -0700 - (mb/google/guybrush: Add initial APCB)
This brings in 1 new commit.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I3003fdb8ba0bcfbc33452999c35a9a21775ecc10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Let the linker do its job.
This fixes building with !CONFIG_PCIEXP_HOTPLUG on some platforms.
Change-Id: I46560722dcb5f1d902709e40b714ef092515b164
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The current values are actually for 32MiB and result in a brick if used
with a 16MiB chip because of the invalid bios region.
Change-Id: I08337394ce0d6e31e5c03cda2bfb3b9f0282f2c3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51322
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Picasso APUs advertise 23 MCA banks in the lower byte of the
IA32_MCG_CAP MSR, which is more than the 7 core MCA banks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e1c8ed437820b350c78b0517e6521582002ee1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The bank names were copied over from Stoneyridge, but they don't match
for Picasso.
TEST=Checked the Picasso PPR.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia86cf3874f8b16b007bad46535af6dafb776fbdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51476
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without the boot template, u-root doesn't include any boot commands.
Booting other OS is impossible.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: I7d0742d115715eb40e293e2a8711d1ff20d8970a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51331
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This enables the standard library method of adding SPDs to CBFS.
BUG=b:178715165
TEST=Build
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I2ec94fd866409e1dfa5cb65f6960ea07cbe22f2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51022
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the option to build guybrush firmware with support for EM100.
This will assist in bringup of the new board.
BUG=b:180723776
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I2246d2952f341cd8fff8fd486cf989cdb7929411
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51071
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cliff Huang