Commit Graph

52329 Commits

Author SHA1 Message Date
Felix Held 46a972022b mb/amd/birman/port_descriptors_*: use DDI_DP_W_TYPEC type for DDI 2..4
DDI 2..4 are the display outputs multiplexed onto the 3 USB type C ports
as DisplayPort alternate function, so use the DDI_DP_W_TYPEC connector
type for those.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I659d62bfb426e3e47214203490c34e9c200beee2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74299
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12 17:08:00 +00:00
Marshall Dawson 7c6b0e9862 mainboard/google/skyrim: Fix MP2 FW naming
Update the blob type for TypeId0x25_Mp2Fw_MDN_AD03.sbin to
subprogram 0. Delete the extra MP2FW line.

BUG=b:246770914

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I5418b1ed59e1916b971d2eece9f6a2fd0e51b1b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-12 16:29:28 +00:00
Michael Niewöhner f14dbdc519 Revert "device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORT"
This reverts commit 655f7362e1.

Reason for revert: Apparently, the change was not properly reviewed. It
not only contains conflicting name and description of the D3COLD
Kconfig, but also creates a conflict between existing devicetree and
Kconfig options for D3Cold/S3/S0ix.

Change-Id: I56ce8f59f8548fc58bc2b3b07c1314e2eed7061c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12 15:20:37 +00:00
Michael Niewöhner a231e71cf1 Revert "soc/intel/rtd3: Hook up supported states to Kconfig"
This reverts commit dbb97c3243.

Reason for revert: dependency for revert CB:73903

Change-Id: Ibc81483239a13f456d20631725641b7219af4ef8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12 15:20:19 +00:00
Michael Niewöhner 076f86125f Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"
This reverts commit 6bfca1b689.

Reason for revert: dependency for revert CB:73903

Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12 15:19:56 +00:00
Michael Niewöhner 7c722ce179 Revert "soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol"
This reverts commit fd4ad29f18.

Reason for revert: dependency for revert CB:73903

Change-Id: I5ed5e3e267032d62d65aef7fb246a075dccc9cf6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12 15:19:49 +00:00
Patrick Rudolph 76c27c8032 soc/intel/xeon_sp: Drop Kconfig MAX_SOCKET_UPD
The Kconfig is only used in common code to gather the build time
maximum socket number FSP support. The same information is available
in FSP header as MAX_SOCKET, thus use the FSP as truth of source.

Currently MAX_SOCKET is 4.

Change-Id: I10282c79dbf5d612c37b7e45b900af105bb83c36
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74339
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-12 14:51:40 +00:00
Jon Murphy 8118647b2a mb/google/myst: Enable iommu
Enable iommu in devicetree for myst in order to allow kernel to load and
initialize IOMMU.

Bug=b:276805280
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I94e93afe775b070253464a9d187ad6c028d1b811
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-12 14:17:20 +00:00
Jon Murphy 8e02644c90 mb/google/myst: Enable console UART
Enable the console UART for myst devices.

Bug=b:275900837
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I52c1b86c46907216d88f98917968b833af0d5d41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74103
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-12 14:16:44 +00:00
Jon Murphy b27495d0fa mb/google/myst: Add FW_CONFIG
Add initial FW_CONFIG for the myst program.

BUG=b:
TEST=builds

Cq-Depend: chrome-internal:5674351
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If74c3649d4e8d174d9fe00a4b896c2351ee3ab19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-12 14:14:48 +00:00
Jon Murphy 9a2d0e6bc2 mb/google/myst: Enable eSPI SCI events
Enable EC SCI events for eSPI.

BUG=b:275894894
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I8fd858c484f6fcf952bcb4f756ba2e4728091d8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74101
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-12 14:13:35 +00:00
Tony Huang 99330648cc mb/google/nissa/var/yaviks: Generate SPD ID for new memory parts
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
These new memory are added for yavilla.

  DRAM Part Name                 ID to assigna
  H58G66BK7BX067                 4 (0100)
  MT62F2G32D4DS-026 WT:B         4 (0100)
  K3KL9L90CM-MGCT                4 (0100)
  H58G66AK6BX070                 5 (0101)

BUG=b:277148122
BRANCH=firmware-nissa-15217.B
TEST=run part_id_gen to generate SPD id

Change-Id: I3c48b9763f54e2e69f7c2d494fefbabedab2a389
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-12 14:12:15 +00:00
Sumeet Pawnikar 2f7fa55433 Reland "drivers/intel/dptf: Add multiple fan support under dptf"
This reverts commit 4dba71fd25.

Add multiple fan support for dptf policies.

This also fixes the Google Meet resolution drop issue as per
b:246535768 comment#12. When system starts Google Meet video call,
it uses the hardware accelerated encoder as expected. But, as soon as
another system connects to the call, an immediate fallback is observed
from hardware to software encoder. Due to this, Google Meet resolution
dropped from 720p to 180p. This issue is observed on Alder Lake-N SoC
based fanless platforms. This same issue was not seen on fan based
systems. With the fix in dptf driver where fan configures appropriate
setting for only fan participant, not for other device participants,
able to see consistent 720p resolution.

BUG=b:246535768,b:235254828
BRANCH=None
TEST=Built and tested on Alder Lake-P Redrix system for two fans
support and on Alder Lake-N fanless systems. With this code change
Google Meet resolution drop not observed.

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: Id07d279ff962253c22be9d395ed7be0d732aeaa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73249
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12 14:11:45 +00:00
Eric Lai 0c06dbb1a4 mb/google/rex: remove weak from cros gpio
No need for variant to use _weak.

BUG=b:276818954
TEST=new_variant_fulltest.sh rex0

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I7ad904e06e5d83edf4bc11cafd5060ca409bd4ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74294
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-04-12 13:28:17 +00:00
Dtrain Hsu 7e07ab95c7 mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
This patch configures external V1p05/Vnn/VnnSx rails for Uldren
to follow best practices for power savings – untested though.

* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
  S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.

BUG=b:272829190
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74335
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12 13:24:42 +00:00
Karthikeyan Ramasubramanian 1ce9075f8c mb/google/skyrim: Remove mainboard LIDS ACPI object
With EC's lid switch implementation, there is no need to maintain the
lid switch state in mainboard. Hence remove LIDS ACPI object from
mainboard.

BUG=None
TEST=Build Skyrim BIOS image and boot to OS. Read the lid switch state
correctly through /proc/acpi/button/lid/LID0/state.

Change-Id: I0f8dc7216337268c421a475f54ee5b28abf33d08
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-12 12:58:08 +00:00
Karthikeyan Ramasubramanian 8fc20c4961 ec/google/chromeec: Use either EC or MB lid switch state
With CB:16732, EC can provide default lid switch implementation(LID0
ACPI device). Up until that point, mainboard has been providing default
switch implementation. When EC provides lid switch implementation, the
lid switch state is read from EC either through MMAP or LPC interface.
Hence there is no need to keep mainboard's LIDS ACPI object in sync with
EC's lid switch state. Use only EC's lid switch state on boards using
EC's implementation. This paves the way to remove LIDS ACPI object on
those mainboards.

BUG=None
TEST=Build Skyrim BIOS image and boot to OS. Trigger lid open/close
events and ensure that they are detected properly through
/proc/acpi/button/lid/LID0/state.
localhost ~ # cat /proc/acpi/button/lid/LID0/state
state:      open
localhost ~ # cat /proc/acpi/button/lid/LID0/state
state:      closed

Ensure that the system behaves as expected based on powerd
configuration. After signin, system suspends/resumes for lid close/open.
On signin screen, system shuts down/boots for lid close/open.

Change-Id: I013574d7c21761f167ad38aeed27a419677b8000
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-12 12:57:55 +00:00
Sean Rhodes ae4b184ee0 mb/starlabs/starbook/adl: Enable OverCurrent 3 GPIO
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9971209539aa7b74e55673141902b6ad0d698e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73985
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12 12:25:23 +00:00
Sean Rhodes 4d3a0266ce mb/starlabs/starbook/adl: Fix OC pin config
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1c4bdab44f0d73546f52614917dccbe71f0911a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73984
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12 12:25:13 +00:00
Jonathan Zhang aaab6566c0 mb/intel: Add 2 SPR sockets CRB Archer City
Intel Archer City CRB is a dual socket CRB with Intel Sapphire Rapids
Scalable Processor chipset. The chipset also includes Emmitsburg PCH.
It was tested with LinuxBoot payload on both dual and single socket
configurations.
The multisocket support depends on Change-Id:
I4a593252bb7f68494f4ccce215ac9cf1eb19b190

Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71968
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-12 11:43:02 +00:00
Jon Murphy 134566395f mb/google/myst: Add smihandler
Add SMI handler code for Myst platform.

BUG=b:275858191
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I92e5e6aef7ab0b84a96d976e29ebf96b56f6f1a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74100
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-11 20:32:12 +00:00
Jon Murphy a456458db0 mb/google/myst: Enable chromeOS EC
BUG=b:270624655
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Id18a311097d575973087eb92fd446a5c511f570e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-11 20:31:45 +00:00
Jon Murphy 3f34879e28 mb/google/myst: Enable variants for Myst
BUG=b:270618107
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I688e9c2fdf203cecfd5f200dec6cde9dbc0a9aa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-11 20:21:00 +00:00
Kyösti Mälkki 2e9f0d3b6a ACPI: Add helper for MADT LAPICs
This avoids some code duplication related to X2APIC mode.

Change-Id: I592c69e0f52687924fe41189b082c86913999136
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11 19:58:17 +00:00
Kyösti Mälkki 9ac1fb729f ACPI: Add helper for MADT LAPIC NMIs
This avoids some code duplication related to X2APIC mode.

Change-Id: I2cb8676efc1aba1b154fd04c49e53b2530239b4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11 19:57:58 +00:00
Kyösti Mälkki 899c713e3e binaryPI: Use common code for LAPIC NMIs
Change-Id: I1a39f355733d10ecd43a1da541ab2e66ba13db15
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11 19:57:36 +00:00
Michał Żygowski 56621e1e57 soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden
Set the P2SB device as hidden as FSP-S is hiding the PCI configuration
space from coreboot on Alder Lake systems.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-11 16:35:06 +00:00
Michał Żygowski 16c7626077 soc/intel/alderlake: Hook up P2SB PCI ops
P2SB device is being hidden from coreboot by FSP-S. This breaks the
resource allocator which does not report P2SB BAR via intel common
block P2SB driver. Hook up the common block P2SB driver ops to
soc_enable function so that the resources will be reported. The P2SB
device must be set as hidden in the devicetree.

This fixes the silent resource allocation conflicts on machines with
devices having big BARs which accidentally overlapped P2SB BAR.

TEST=Boot MSI PRO Z690-A with multiple PCIe devices/dGPUs with big
BARs and see resource conflicts no longer occur.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I7c59441268676a8aab075abbc036e651b9426057
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-11 16:34:48 +00:00
Sumeet Pawnikar ffc4b8fda4 mb/google/rex: Add DTT thermal settings for thermal control
Add DTT thermal settings for thermal control provided by
thermal team for rex0 board

BRANCH=None
BUG=b:262498724, b:270664854
TEST=Built and verified thermal entries in ACPI SSDT on Rex board

Change-Id: I00dd97b759c8c68edaeeb4d64422b83c5e86981d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-11 16:29:33 +00:00
Paul Menzel 6e4102bc9d soc/amd/mendocino: Lower log level for TDP value to DEBUG
Printing the value of a variable is not informative for a normal user,
so decrease the value from BIOS_INFO to BIOS_DEBUG.

Fixes: b9caac74a3 ("soc/amd/mendocino: Reinterpret smu_power_and_thm_limit")
Change-Id: I22f6293fd47633dfdbdae37b7257f47a5a4bb29c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
2023-04-11 16:29:02 +00:00
Patrick Rudolph d708884d50 soc/intel/xeon_sp/acpi: Fix _OSC method
Fix a couple of bugs in the _OSC method for handling
"PCI Host Bridge Device" on Xeon-SP.

- Drop the Sleep. The code doesn't write to hardware at all, so
  there's no need to sleep here.
- Make sure that the number of DWORD passed in Arg2 is at least 3.
  The existing check was useless as it would not create the
  DWordField, but then use it anyways.
- Add check for CXL 2 device method calls which provide a 5 DWORD
  long buffer to prevent buffer overflows when invoking the
  "PCI Host Bridge Device" method.

Test:
Boot on Archer City and confirm that no ACPI errors are reported
for _OSC.

Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-04-11 16:28:03 +00:00
Michał Żygowski daf834a705 soc/intel/alderlake/iomap: Fix the PCR BAR size on ADL-S
According to ADL PCH BIOS specification (DOC# 630603) ADL-S PCH
uses a fixed SBREG_BAR of 256MiB starting at 0xe0000000.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ied59a6dad8fb065dc3aeb6281bd32074aaa5e3b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-11 16:24:25 +00:00
Mario Scheithauer 1b767725a5 mb/siemens/mc_ehl2: Fix GPIO settings for latest HW revision
With the latest hardware revision, the two GPIOs GPD11 and GPP_C8 are no
longer used.

BUG=none
TEST=Checked output verbose GPIO debug messages

Change-Id: Ia06f93aee4eccb0e4230f0c3ef53922d42701f21
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74201
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-04-11 16:23:54 +00:00
Arthur Heymans e84b095d3a util/sconfig: Remove unused ioapic and irq keywords
Ioapic information in the devicetree was only used to set up mptables
but this generic driver was removed (ca5a793 drivers/generic/ioapic:
Drop poor implementation).

This removes the unused remainders from mainboard devicetrees.
Remove ioapic setup from sconfig.

Change-Id: Ib3fef0bf923ab3f02f3aeed2e55cf662a3dc3a1b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-11 16:23:28 +00:00
Arthur Heymans 8b8400a889 drivers/fsp2_0/mp_service_ppi: Use struct device to fill in buffer
Now the CPU topology is filled in struct device during mp_init.

Change-Id: I7322b43f5b95dda5fbe81e7427f5269c9d6f8755
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-11 16:02:09 +00:00
John Su d9b938b0cf mb/google/skyrim: Enable UPD usb3_port_force_gen1 for Markarth
From request, all type C port limit to to Gen1 5GHz.
So enable UPD usb3_port_force_gen1 for Markarth.

BUG=b:273841155
BRANCH=skyrim
TEST=Build, verify the setting will be applied on Markarth.

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I9314b67a82ad2993c87f0110db5ec927caaa772b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74087
Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-11 15:56:55 +00:00
Tarun Tuli 166387f790 mb/google/brya/variants/hades: Update GPU power sequencing to add Hades support
Add GPU power sequencing changes for the Hades baseboard and variant.
Some signals were added, moved or inverted.
Based on implementation from Agah.

Moved signals:
GPIO_1V8_PWR_EN		GPP_E11
GPIO_NV33_PWR_EN	GPP_E2
GPIO_NV33_PG		GPP_E1

New signals:
GPIO_NV12_PWR_EN	GPP_D0
GPIO_NV12_PG		GPP_D1

Inverted signals:
GPIO_FBVDD_PWR_EN	GPP_A19

ifdef's will be dropped once the Agah variant is retired.

BUG=b:269371363
TEST=builds and verified on Agah that DGPU is still detectable (lspci)

Change-Id: I0b8efe7a34102cf61d4f784103c4a4f9337213f7
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-04-11 14:34:41 +00:00
Bill XIE fa38535a20 mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
mainboard_vbt_filename() used to assume that it is called after a call
to get_blc_pwm_freq_value() with a valid parameter, but currently it
is the first call of get_blc_pwm_freq_value(NULL), and will return 0,
so "data_led.vbt" is always returned, regardless of the actual type of
the panel.

Combined with the previous commit, in this commit
mainboard_vbt_filename() will explicitly read EDID string via
gm45_get_lvds_edid_str() and use this string to call
get_blc_pwm_freq_value().

Resolves: https://ticket.coreboot.org/issues/475

Tested on my x200s with LTD121EQ3B (LED), and x200 with LTD121EWVB
(CCFL).

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74181
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-11 11:47:07 +00:00
Subrata Banik cc4ca5ec94 mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MB
This patch updates the MTLRVP debug flash layout to optimize WP_RO to 4MB.

Changes for chromeos.fmd:

SI_BIOS:
    RW_SECTION_A/B: Increase to 7.5MB.
    RW_LEGACY: Introduce with 1MB.
    RW_MISC: Increased to 1MB.
    RW_UNUSED: 2MB (reserved)
    WP_RO: Reduce to 4MB

Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the
SPI Flash.

BUG=b:277143384
TEST=Able to build and boot intel/mtlrvp with FSP release and debug image.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie635e3cce1c3fd771e6a17e4b3c1bd700f4729bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-11 11:39:14 +00:00
Subrata Banik 589f6b9c04 mb/google/rex: Update Debug Flash Layout to fit WP_RO within 4MB
This patch updates the Rex debug flash layout to optimize WP_RO to 4MB.

Changes for chromeos.fmd:

SI_BIOS:
     RW_SECTION_A/B: Increase to 7.5MB.
     RW_LEGACY: Introduce with 1MB.
     RW_MISC: Increased to 1MB.
     RW_UNUSED: 2MB (reserved)
     WP_RO: Reduce to 4MB

Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the
SPI Flash.

BUG=b:277143384
TEST=Able to build and boot google/rex with FSP release and debug image.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4ab69eb24937d58c8bc5d3c0a6e5cb70b843a1ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-11 11:38:54 +00:00
Subrata Banik c484c1a9f6 mb/intel/mtlrvp: Update Flash Layout to fit WP_RO within 4MB
This patch updates the MTLRVP flash layout to optimize WP_RO to 4MB.

Changes for chromeos.fmd:

SI_BIOS:
     RW_SECTION_A/B: Reduce to 7MB.
     RW_LEGACY: Reduce to 1MB.
     RW_MISC: Increased to 1MB.
     RW_UNUSED: 3MB (reserved)
     WP_RO: Reduce to 4MB

Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the
SPI Flash.

BUG=b:277143384
TEST=Able to build and boot intel/mtlrvp with FSP release and debug image.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibd1ea7a3a2cd21928b8e33473c7bdddfad17c636
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-11 11:38:43 +00:00
Subrata Banik 9629f94c4e mb/google/rex: Update Flash Layout to fit WP_RO within 4MB
This patch updates the Rex flash layout to optimize WP_RO to 4MB.

The idea is to create more space inside FW_RW_A/B to accommodate
multiple blobs to boot google/rex with different Intel MTL SoC stepping.

Changes for chromeos.fmd:

SI_BIOS:
     RW_SECTION_A/B: Reduce to 7MB.
     RW_LEGACY: Reduce to 1MB.
     RW_MISC: Increased to 1MB.
     RW_UNUSED: 3MB (reserved)
     WP_RO: Reduce to 4MB

Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the
SPI Flash.

BUG=b:277143384
TEST=Able to build and boot google/rex with FSP release and debug image.

Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74229
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-11 11:38:23 +00:00
Subrata Banik cda48b297c soc/intel/{adl, cmn}: Send CSE EOP Async CMD early
This patch sends the CSE EOP command asynchronous implementation early
as part of `soc_init_pre_device`.

Without this patch the duration between asynchronous CSE EOP send and
receive commands is not ample whichcauses idle delay while waiting
for EOP response.

The goal of the CSE async implementation is to avoid idle delay while
capturing the response from CSE EOP cmd.

This patch helps to create ample duration between CSE EOP command
being sent and response being captured.

TEST=Able to boot google/marasov EVT sku to ChromeOS and observed
~30ms of boot time savings (across warm and cold reset scenarios).

Without this patch:

  963:returning from FspMultiPhaseSiInit          907,326 (97,293)
  ...
  ...
  115:finished elog init                          967,343 (2,581)
  942:before sending EOP to ME                    967,821 (478)
  … 
  16:finished LZMA decompress (ignore for x86)    1,017,937 (12,135)
  943:after sending EOP to ME                     1,067,799 (49,861)
  …
  …
  1101:jumping to kernel                          1,144,587 (13,734)

  Total Time: 1,144,549

With this patch:
  963:returning from FspMultiPhaseSiInit          918,291 (97,320)
  942:before sending EOP to ME                    918,522 (230)
  ...
  ...
  16:finished LZMA decompress (ignore for x86)    1,029,476 (12,483)
  943:after sending EOP to ME                     1,033,456 (3,980)
  ...
  ...
  1101:jumping to kernel                          1,111,410 (14,007)

  Total Time: 1,111,375

Change-Id: Idaf45ef28747bebc02347f0faa77cc858a4a8ef1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-11 11:37:38 +00:00
Cliff Huang e46dbf771b mb/intel/mtlrvp: Enable PCIe port 6 and RTD3 support for x1 slot
This change enables PCIe x1 slot. In addition, it turns off 3.3v and
12v power and assert PERST# when suspend and turn on the power and
deassert the PERST# when resume for the x1 slot.

NOTE: Kconfig flag and required GPIO pins are already configured.
- /soc/intel/meteorlake/Kconfig
	select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
- gpio.c:
    /* GPP_A18: X1_PCIE_SLOT3_PWR_EN */
    PAD_CFG_GPO(GPP_A18, 1, DEEP),
    /* GPP_A19: X1_DT_PCIE_RST_N */

   /* SRCCLKREQ: GPP_C12: SRCCLKREQ3_GEN4_X1_DT_SLOT3_N */
    PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),

BUG=b:224325352
BRANCH=None
TEST=Insert a SD card or NIC AIC on PCIe x1 slot and the AIC should
be detected and enabled at boot. For S0ix, run
'suspend_stress_test -c 1'. The RP6 should not cause any suspend and
resume issue.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Id2e92acf754569a22ea76a68c91aafce0075a742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73054
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-11 05:32:13 +00:00
Matt DeVillier f2e8865d76 soc/amd/common/blk/pcie: Program LTR max latencies
PCIe bridges need to provide the LTR (latency tolerance reporting)
maximum snoop/non-snoop values so that they are inherited by downstream
PCIe devices which support and enable LTR. Without this, downstream
devices cannot have LTR enabled, which is a requirement for supporting
PCIe L1 substates. Enabling L1ss without LTR has unpredictable behavior,
including some devices refusing to enter L1 low power modes at all.

Program the max snoop/non-snoop latency values for all PCIe bridges
using the same value used by AGESA/FSP, 1.049ms.

BUG=b:265890321
TEST=build/boot google/skyrim (multiple variants, NVMe drives), ensure
LTR is enabled, latency values are correctly set, and that device
power draw at idle is in the expected range (<25 mW).

Change-Id: Icf188e69cf5676be870873c56d175423d16704b4
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74288
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-10 16:41:26 +00:00
Matt DeVillier 0d5b0248eb mb/google/sarien: Use runtime detection for touchscreens
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.

TEST=build/boot Windows/linux on drallion, verify touchscreen functional
in OS, dump ACPI and verify only i2c devices actually present on the
board have entries in the SSDT.

Change-Id: I3b91a628cd4a9edb5d5a7521529f39b75935e1d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-10 15:14:34 +00:00
Matt DeVillier 50143cfb22 mb/google/sarien: Set touchpad/screen IRQs to LEVEL vs EDGE
Ensure the GPIOs themselves are configured as level triggered, as well
as the devicetree entiures. I2C-HID spec requires LEVEL trigger, and the
drivers (both Linux and Windows) work better with LEVEL vs EDGE trigger.

TEST=tested with rest of patch train

Change-Id: I4fba55c938f401876798c2b32c5922523f32180f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-10 15:14:11 +00:00
Matt DeVillier b4bf865359 mb/google/sarien: Implement touchscreen power sequencing
For touchscreens on sarien, drive the enable GPIO high starting in
romstage while holding in reset, then disable the reset GPIO in
ramstage. This will allow coreboot to detect the presence of i2c
touchscreens during ACPI SSDT generation (implemented in a subsequent
commit).

BUG=b:121309055
TEST=tested with rest of patch train

Change-Id: I3ce7bfc0fa4c03c0bb96bebaa3c3d256f886ecc4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-10 15:13:52 +00:00
Matt DeVillier 08da6eff8a mb/google/sarien: Add method to set GPIOs in romstage
Add method variant_romstage_gpio_table() with empty implementation to
be used in a subsequent commit for touchscreen power sequencing.
Call method in romstage to program any GPIOs that may need to be set.

TEST=tested with rest of patch train

Change-Id: I11b72a10a4a105385fbcf1d795c020708a7a90d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-10 15:13:15 +00:00
Matt DeVillier a358f2b4f7 mb/google/brya: Compile gpio.c in SMM when needed
Without gpio.c compiled in, SMMSTORE will fail to initialize and hang.
Add a conditional inclusion so gpio.c is compiled in SMM when SMMSTORE
is selected.

TEST=build/boot google/banshee with SMMSTORE support enabled

Change-Id: If049cba98f13f060807058029306dcad2ada2d49
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-10 15:13:01 +00:00