Commit Graph

41461 Commits

Author SHA1 Message Date
Jakub Czapiga 4ae7ee6e2b lib/rtc: Remove unnecessary year constraint in rtc_calc_weekday
Algorithm used to calculate weekday is now based on Zeller's rule, so it
does not need if statement constraining year to 1971 and later.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I25e2e6a1c9b2fb1ac2576e028b580db0ea474d37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-15 07:39:31 +00:00
Jakub Czapiga a4819b3c31 Makefile: Add unit-tests help and targets list
Add unit-tests targets to help output. Add list-unit-tests target
that lists all available unit-tests.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I464a76cbea1f4afbc3fc772960787952e61b95b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-04-15 07:38:48 +00:00
Jakub Czapiga dadcae63c6 tests: Add lib/dimm_info_util-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I536566ba883bbeb558587a8d71e3d86152fb5e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-15 07:38:05 +00:00
Jonathan Zhang e73bae7b0a Documentation/mb/ocp: Update Delta Lake documentation
Update OCP Delta Lake documentation following OSF (Open System Firmware)
solution reaching DVT exit parity. This alternative host firmware
solution uses FSP/coreboot/Linuxboot stack.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ifd6ab251cd7806cf8cd3f984ad88c091f85035cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-15 07:37:46 +00:00
Tim Crawford a346fd943f mb/system76/oryp5: Enable TAS5825M smart amp
Allows using the internal speakers of the oryp5.

Smart AMP data was collected using a logic analyzer connected to the IC
during system start on proprietary firmware. This data is then used to
generate a C file [1].

[1]: https://github.com/system76/smart-amp

Change-Id: I148f18ff3e754d913bdf907121b103c6de02ffc3
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47962
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15 07:37:22 +00:00
Jeremy Soller e20c47b408 drivers/i2c/tas5825m: Add driver for TI TAS5825M
This adds a driver for the TI TAS5825M smart amplifier [1].

The driver expects the mainboard using it to define tas5825m_setup(),
which uses the tas5825m_* functions to set configuration data. Each
mainboard may have very different configuration data, depending on
its audio hardware.

Tested on System76 addw1, bonw14, oryp5, and oryp6.

[1]: https://www.ti.com/product/TAS5825M

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I896e8f272f18e64bfc90f406e7d4163010800aaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15 07:36:03 +00:00
Tony Huang a1165fdfd4 mb/google/dedede/var/kracko: Add LTE modem support
Add LTE modem to devicetree
Configure GPIO control for LTE modem

BUG=b:178092096
TEST=Built image and verified with command modem status

Change-Id: Id8f483e1132a08500fbe950711cc84197ce40b12
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-15 07:35:42 +00:00
Tao Xia 9f24c4b12a mb/google/dedede/var/sasukette: Enable Wifi SAR for sasukette
BUG=b:185084331
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Ie982741cb7b328623cf27f41c31f819e8cdb7bc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-15 07:35:35 +00:00
Kevin Chiu 2414148220 mb/google/zork: fine tune stamp_boost parameter for dirinboz
The new discovery from Google & AMD, the value currently used
STAPM Time Constant of 1640 is reducing real PPT TSP from the
target 4.8W to 4.68W.

Furthermore, when using the "default" STAPM Time Constant of 1400,
the actual real PPT TSP becomes 4.89W.

Operating at this default settings therefore uses a higher real PPT TSP,
which results in a significant performance improvement.

BUG=b:175364713,b:184902568
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. run balance performance and skin temperature test => pass

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I9cf4d51f42fe250340bcb642db07796c9a480c34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52312
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15 07:31:08 +00:00
Kevin Chiu fde6b65b52 mb/google/zork: fine tune stamp_boost parameter for gumboz
The new discovery from Google & AMD, the value currently used
STAPM Time Constant of 1640 is reducing real PPT TSP from the
target 4.8W to 4.68W.

Furthermore, when using the "default" STAPM Time Constant of 1400,
the actual real PPT TSP becomes 4.89W.

Operating at this default settings therefore uses a higher real PPT TSP,
which results in a significant performance improvement.

BUG=b:184902568
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. run balance performance and skin temperature test => pass

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I102c1c5f8215a6c5f7a4451f5731167c32e27c90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52313
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15 07:30:59 +00:00
Stanley Wu 51f3b32255 mb/google/dedede/var/boten: Add custom Wifi SAR for botenflex
Add wifi sar for botenflex.
Due to fw-config cannot distinguish between boten and botenflex.
Using sku_id to decide to load botenflex custom wifi sar.
Detail reason for using sku_id in b:182433707.

BUG=b:182433707
TEST=build and test on boten/botenflex

Cq-Depend: chrome-internal:3686313
Change-Id: Id3f2529a7ad56ff306df98f77cda556656da52a5
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-14 23:43:12 +00:00
FrankChu 79a72c4c4b mb/google/volteer: Update collis device tree
Update device tree override to match schematics.

BUG=b:182227204
TEST=emerge-volteer coreboot

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ib1698504cc0b377659fa60b4fae25227b5823753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-14 20:31:11 +00:00
FrankChu 6943ada500 mb/google/volteer: Add GPIO to collis support
Add support for gpio driver for collis

BUG=b:182227204
TEST=emerge-volteer coreboot

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ief225093bf93137384b64327a1c66576c9a5193a
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-14 20:30:57 +00:00
Tim Crawford 3647e86862 mb/system76/whl-u: Add System76 Galago Pro 3 Rev C
Tested with TianoCore payload (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- NVMe port
- SATA port
- SD card slot
- Left USB 3 Type-A port
- Right USB 3 Type-A port
- Right USB 3 Type-C port
- Webcam
- Ethernet
- Integrated graphics using Intel GOP driver
- mDP output
- HDMI output
- Internal microphone
- Internal speakers
- 3.5mm audio input
- 3.5mm audio output
- S3 suspend/resume
- Flashing with flashrom
- Booting to Ubuntu Linux 20.10 and Windows 10

Not tested:

- Thunderbolt functionality

Change-Id: I5c992e603dbd57ae1b4ddc3a0f9bfc92d6acc813
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14 19:59:46 +00:00
Felix Held c0538d4613 soc/amd/stoneyridge: use common pm_set_power_failure_state functionality
The functionality to restore the previous power state after power was
lost that could previously be enabled by selecting
MAINBOARD_POWER_RESTORE in the mainboard's Kconfig can now be achieved
by selecting POWER_STATE_PREVIOUS_AFTER_FAILURE in the mainboard's
Kconfig instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I49c4a44ca2c4fa937a823c4eddf1618739c15114
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14 18:46:48 +00:00
Felix Held bbb8c042e4 soc/amd/piasso/fch: use common pm_set_power_failure_state functionality
The functionality to restore the previous power state after power was
lost that could previously be enabled by selecting
MAINBOARD_POWER_RESTORE in the mainboard's Kconfig can now be achieved
by selecting POWER_STATE_PREVIOUS_AFTER_FAILURE in the mainboard's
Kconfig instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab9578ebea89651dc2389bf6ca93ca3f3507eb47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14 18:46:23 +00:00
Felix Held 43cd1c0bbe soc/amd/common/block/pm: rework pm_set_power_failure_state
Picasso and Stoneyridge didn't do a read-modify-write operation on the
lower nibble of PM_RTC_SHADOW_REG, but just wrote the upper nibble as
all zeros. Since the upper nibble might be uninitialized before the
lower nibble gets written, do what Picasso and Stoneyridge did here
instead of what the reference code does. Also add a comment why and how
this register behaves a bit weird.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bda2349e3ae84cba50b187cc773fd8a5b17f4e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14 18:45:39 +00:00
Felix Held 151cc6c14b soc/amd/common/block/pm: remove POWER_STATE_DEFAULT_ON_AFTER_FAILURE
Not selecting POWER_STATE_DEFAULT_ON_AFTER_FAILURE brings Cezanne that
is currently the only SoC using this functionality in line with Picasso
where the default is that the board remains in power off mode after
power was lost and later restored. Boards can change this behavior by
selecting POWER_STATE_OFF_AFTER_FAILURE, POWER_STATE_ON_AFTER_FAILURE or
POWER_STATE_PREVIOUS_AFTER_FAILURE.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic96f40e3c9867cd821e58d752f58b763930f6d0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14 18:45:13 +00:00
Felix Held 7cc502b07a soc/amd/common/block/pm: select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
Without this being selected, mainboards can't select
MAINBOARD_POWER_STATE_PREVIOUS to use the power state restoration code
path in pmlib.c

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I753659fa753e03a66b6c6b2eb97e7ef20c71ca57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14 18:44:50 +00:00
Tim Wawrzynczak 5641590957 mb/google/brya: Enable CSE Lite SKU
The first CSE Lite SKU is available, therefore enable the Kconfig
option to have the CSE reboot the system into its RW FW during a cold
boot.

BUG=b:183826781
TEST=50 cold reboot cycles

Cq-Depend: chrome-internal:3758108
Change-Id: Ib3a1a9f8ac51bdab8858b2764d5bc0f6f07987cc
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-14 15:59:23 +00:00
Michael Niewöhner a0c7f34302 maintainers.go: Work around common mistake in MAINTAINERS
Gerrit is able to add reviewers based on entries in the `MAINTAINERS`
file. For inclusion and exclusion matches either paths or regular
expressions can be used. The syntax is described in the header of the
file.

When matching a path, there are two sensible possibilities:
  - `path/to/file`  matches a file.
  - `path/to/dir/`  matches a folder including its contents recursively.
  - `path/to/dir/*` matches all files in that folder, without recursing
                    into its subfolders.

The trailing slash in the second example is essential. Without it, only
the directory entry itself matches when, for example, the folder gets
deleted, renamed or its permissions get modified. Reviewers in the list
won't get added to changes of any files or directories below that path.

However, from time to time entries get added without this trailing
slash. Thus, implement a workaround in `maintainers.go` to check, if a
path entry is actually a directory. In such case a trailing slash gets
appended, so that the contents will match, too.

Example: `path/to/dir` will become `path/to/dir/`

Tests:
1. output before and after does not differ
2. manual test of resulting regex when running `maintainers.go`

Change-Id: Ic712aacb0c5c50380fa9beeccf5161501f1cd8ea
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52276
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14 12:18:58 +00:00
Michael Niewöhner 158fed9ee7 maintainers.go: correct handling of globs
maintainers.go does not handle globs as described in MAINTAINERS.
Instead of only matching the files inside a directory, it also matches
everything below. Also, a glob used in between (`e.g. path/to/*/dir`)
could lead to matching many more paths unexpectedly.

This is caused by the way paths using globs are converted to regegular
expressions for use with gerrit:

1. The script converts all paths with trailing slash to a path with
   trailing glob. That means, a recursive match on a directory gets
   converted to match only the files in the directory (at least
   according to the documentation - if there wasn't 2).

   Example: `path/to/dir/` becomes `path/to/dir/*`

2. When converting the path to a regex, all globs get converted to
   prefix matching by replacing the glob by `.*`. Instead of only
   matching the files in the directory, everything below matches,
   which is a) not what the documentation states and b) the opposite
   of what 1. did first.

   Example: `path/to/dir/*` becomes `^path/to/dir/.*$`

In sum, this leads to all sorts of issues. Examples:
  - `path/*/dir`    becomes `^path/.*/dir$`
  - `path/to/dir/*` becomes `^path/to/dir/.*$`
  - `path/to/*.c`   becomes `^path/to/.*\.c$`

This change fixes that behaviour by:
- dropping the wrong conversion from 1. above.
- fixing glob matching by replacing `*` by `[^/]`.
- handling paths with trailing `/` as prefix, as documented.

The change was not split because these changes depend on each other and
splitting would break recursive matching between the commits.

Tests:
1. diffed output before and after is equal (!= the same)
2. manual testing of glob matching

Change-Id: I4347a60874e4f07e41bdee43cc312547bea99008
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-14 10:50:18 +00:00
Frans Hendriks 20e04efc33 mb/portwell/m107/Kconfig: Remove CACHE_MRC_SETTINGS
The CACHE_MRC_SETTINGS option is already selected in SoC Kconfig.

BUG = N/A
TEST = Build and boot Portwell M107

Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: I528c582419fb2044f5edfd7a070785489efdf7a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52154
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14 10:38:50 +00:00
Kevin Chang c48cf110dd lillipup: provide additional VBT for lillipup OLED sku
Lillipup add two sku for OLED panel.

Additional VBT is necessary to modify PWM source from VESA eDP AUX
interface

BUG=b:183630802
TEST=emerge-volteer coreboot-private-files-baseboard-volteer
check vbt_oled.bin is under build folder and check in CPU log.

Cq-Depend: chrome-internal:3744227
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I576297b8296def3c37a01ae0223fa332aa9f02b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52150
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14 10:38:36 +00:00
Nico Huber 7cc14ac25d Rename do_printk() to printk()
The indirection seems unnecessary. The macros throw features like
`-Wmisleading-indentation` off, though.

Default build for QEMU/Q35 is unchanged.

Change-Id: Ie4eab935a367b5ad6b38225c4973d41d9f70ef10
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-14 10:38:09 +00:00
Nico Huber 879ccaa7c5 console: Always add printf-format attribute to printk()
The attribute was missing in case the console is disabled.

Change-Id: Iee23f6f4da61cd3637441705a8d3bbd2da7a33ca
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52231
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14 10:37:04 +00:00
Julius Werner 62fa9f3cf9 intel: mma: Use new CBFS API
This patch changes the Intel MMA driver to use the new CBFS API.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Icc11d0c2a9ec1bd7a1d6af362f849dac16375433
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-14 01:03:33 +00:00
Julius Werner 43c9d709c7 intel: fsp2_0: Move last pieces to new CBFS API
This patch ports the last remaining use of cbfs_boot_locate() in the
Intel FSP drivers to the new CBFS API. As a consequence, there is no
longer a reason for fsp_validate_component() to operate on rdevs, and
the function is simplified to take a direct void pointer and size to a
memory-mapping of the FSP blob instead.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If1f0239eefa4542e4d23f6e2e3ff19106f2e3c0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52281
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14 01:03:26 +00:00
Julius Werner b3182fbb00 vboot: ec_sync: Switch to new CBFS API
This patch changes the vboot EC sync code to use the new CBFS API. As a
consequence, we have to map the whole EC image file at once (because the
new API doesn't support partial mapping). This should be fine on the
only platform that uses this code (Google_Volteer/_Dedede family)
because they are x86 devices that support direct mapping from flash, but
the code was originally written to more carefully map the file in
smaller steps to be theoretically able to support Arm devices.

EC sync in romstage for devices without memory-mapped flash would be
hard to combine with CBFS verification because there's not enough SRAM
to ever hold the whole file in memory at once, but we can't validate the
file hash until we have loaded the whole file and for performance (or
TOCTOU-safety, if applicable) reasons we wouldn't want to load anything
more than once. The "good" solution for this would be to introduce a
CBFS streaming API can slowly feed chunks of the file into a callback
but in the end still return a "hash valid/invalid" result to the caller.
If use cases like this become pressing in the future, we may have to
implement such an API.

However, for now this code is the only part of coreboot with constraints
like that, it was only ever used on platforms that do support
memory-mapped flash, and due to the new EC-EFS2 model used on more
recent Chrome OS devices we don't currently anticipate this to ever be
needed again. Therefore this patch goes the easier way of just papering
over the problem and punting the work of implementing a more generic
solution until we actually have a real need for it.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7e263272aef3463f3b2924887d96de9b2607f5e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52280
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14 01:03:22 +00:00
Yu-Ping Wu c074f61d8f soc/mediatek: Include sdram_info in ddr_base_info
Sync dramc_param.h with private repo mtk-dramk (CL:*3751861).

BUG=none
TEST=emerge-asurada coreboot
TEST=Hayato boots with fast calibration
BRANCH=asurada

Change-Id: I79541f66ce68a75147c22b83a456e6268ca1485e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-04-14 00:55:57 +00:00
Yidi Lin 97b9d9ef24 mb/google/cherry: Add MediaTek MT8195 reference board
TEST=boot from SPI-NOR and UART works fine.

Change-Id: I279b3d2da8a30b38686005212f6c019a9a646874
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-14 00:55:47 +00:00
Felix Held df9549efb2 soc/amd/picasso/fch: add missing amdblocks/gpio_banks.h header
The prototype of gpio_add_events() is provided by that header file.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia384c9297ac1e24bf0b1bcce048012a247406f39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52274
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14 00:01:44 +00:00
Felix Held 72b78910fb soc/amd/cezanne/fch: process ACPI PM/GPE and GPIO events
BUG=b:184549804

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4ebbe9667d18a96b1a363d0353c612e214699d12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52273
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14 00:01:22 +00:00
Martin Roth 31f7a726ff soc/amd/cezanne: save chipset state to CBMEM
Guybrush complains that this is missing during the boot, so add it to
cezanne. I verified that the registers in gpio.c are correct.

BUG=b:184549804
TEST=Build and boot

Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3de3764c99fe89b962db88065575463b365ddaf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14 00:00:51 +00:00
Felix Held 0d2c0019e2 soc/amd/picasso/romstage: factor out chipset state saving functionality
Since Cezanne needs the exact same code, move it to the common directory
and add a Kconfig option to add this functionality to the build.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I04c4295071a3df7afcb4dfd5435b11fb0bf6963f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14 00:00:27 +00:00
Michael Niewöhner 651d5214d2 mb/clevo/cml-u: drop LPC generic range for port 80
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have
to be set up as generic range. Drop the entry from clevo/cml-u, which
has been forgotten in commit c5f1dc9.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I05844db4cfe96e6075bd6526ffc242973a2082c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-04-13 19:39:27 +00:00
Jakub Czapiga ec8eef0a6b tests/lib/bootmem-test: Add initialization of lb_mem fields
Add missing initialization of tag and size fields. Include initial size
value in assertion in test_bootmem_write_mem_table().

Found-by: Coverity CID 1452250
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I27678a4eb01a0e6bedd0ba8c4b22a1b01afeaf12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-13 16:03:27 +00:00
Michael Niewöhner 64d31f48d2 lint: MAINTAINERS: check path matches to not only cover the directory
Gerrit is able to add reviewers based on entries in the `MAINTAINERS`
file. For inclusion and exclusion matches either paths or regular
expressions can be used. The syntax is described in the header of the
file.

When matching a path, there are two sensible possibilities:
  - `path/to/file`  matches a file.
  - `path/to/dir/`  matches a folder including its contents recursively.
  - `path/to/dir/*` matches all files in that folder, without recursing
                    into its subfolders.

The trailing slash in the second example is essential. Without it, only
the directory entry itself matches when, for example, the folder gets
deleted, renamed or its permissions get modified. Reviewers in the list
won't get added to changes of any files or directories below that path.

Thus, add a linter script to ensure a path match on a directory always
ends with `/` or `/*` as shown above.

Change-Id: I9873184c0df4a0b4455f803828e2719887e545db
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-13 14:29:43 +00:00
Angel Pons 2b4da16ea4 mb/hp/280_g2/romstage.c: Correct CaVrefConfig setting
With DDR4, CA Vref goes to channel 0, and CH1 Vref goes to channel 1.

Change-Id: I64606824b4f82affb0fcfc78e68ba29859a1cc69
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-13 08:24:29 +00:00
Tim Wawrzynczak 7f7c3882a6 dptf: Move platform-specific information to `struct dptf_platform_info`
DPTF HIDs are different per-platform going forward, so refactor these
into SoC-specific structures which the DPTF driver can query at runtime
for platform-specific information.

Change-Id: I6307f9d28f4274b851323ad69180ff4ae35053da
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-13 08:22:49 +00:00
Yidi Lin 24ea3f3364 soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC
TEST=boot from SPI-NOR and show console message at bootblock stage.

Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-13 06:07:54 +00:00
Nico Huber 2bb361f0f5 nb/intel/x4x: Refactor sync DLL programming (part 2)
Instead of counting consecutive matches (in `j`), check for a second
match directly in the control flow. Also, add some dedicated variables:

* `tap`: Keeps track of the tap value that resulted in a match and
         is eventually programmed into the hardware.

* `tap2`: Is just temporarily used to search for another edge.

Keeping `tap` sync'ed with the hardware has the benefit that we don't
need to read the programmed value back for later fixups.

Change-Id: I3ae541c39efdc695f5ca74bc757b2f009239ec93
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-12 20:42:08 +00:00
Nico Huber a20a02e82a nb/intel/x4x: Refactor sync DLL programming (part 1)
Extract some common code patterns into functions.

Change-Id: I5f8d40bb55d4b4f0639e0287881ae0ecde298590
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-12 20:41:53 +00:00
Nico Huber b6a2ebe5ef nb/intel/x4x: Sort code in program_dll()
Move the last block of the sync DLL programming up. It's independent
of the switch/case statement that it's moved around.

Change-Id: I71bc1ca1c629e4f2f4a13474c7e2c22d1a3b65d9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-12 20:41:43 +00:00
Eric Lai 67d099a7f2 mb/google/mancomb: Temporary fix to set eSPI mux
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ief59bdea392ab3f141ccf7444c608aef99701d2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-12 17:26:52 +00:00
Kangheui Won 082be1073e chromeec: make ssfc optional in fw_config
When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and SSFC is
not set, all fw_config is invalidated. But for some platform this may
not be necessary, we can treat missing SSFC as zero and use other 32
bits of firmware config.

BUG=b:184809649
TEST=boot and check fw_config is not -1 even if ssfc is not set
BRANCH=zork

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I21c7b0d449a694d28ad7b3f14b035e3a5830030a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-12 17:11:40 +00:00
Michael Niewöhner c5f1dc96bf mb/*: drop LPC generic range for port 80
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have
to be set up as generic range. Drop the entries from the devicetrees.

Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-12 16:52:19 +00:00
Felix Held c1ec940eba mb/amd/majolica/port_descriptor: use GPIO number define
TEST=Timeless build results in identical binary.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie39dc99bef4eb3776388d7406239bac6031bfaaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-12 15:46:39 +00:00
Eric Lai 141f33de54 mb/google/mancomb: add DXIO and DDI descriptors
Sync from guybrush.

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ica4e6511a5106a958567565b96d5888b8c829ff2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-12 14:59:00 +00:00
Ritul Guru 7dccf47fdd mb/amd/bilby: Use Picasso VBIOS as default
use PicassoGenericVbios.bin as default instead of raven VBIOS for
Bilby.

Change-Id: I99621173a33a1154f8bb4929d199288265bbe04d
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52209
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-12 14:58:12 +00:00