Commit Graph

19499 Commits

Author SHA1 Message Date
Elyes HAOUAS 4b940bea54 sb/intel/i3100/lpc.c: Use tab for indents
Change-Id: I37d0b1ad84a95342015659d319ac4ce20e5717be
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17584
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-28 01:06:33 +01:00
Martin Roth ab273d3f16 kconfig_lint: More updates for excluded files
- All of the symbols are in the .config, so if .config is include in
the search all of the symbols are always found.
- There are now some Kconfig symbols in the Documentation directory,
so that needs to be excluded.
- 3rdparty has lots of Kconfig symbols that are unrelated to what
is being searched for.

Change-Id: I0ff56d0a0916338a8b94f5210b8e0b3be5194f41
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17588
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-11-28 01:05:40 +01:00
Martin Roth e69c58d7c8 kconfig_lint: exclude payloads from search, add back specific files
Don't search for symbols in the payloads directory, except for specific
files that are actively added back to the search.

Change-Id: I6f28dc7dee040b8061fa5644066f3613367b6d84
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17443
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-11-28 01:05:01 +01:00
Patrick Rudolph e74ad21a91 nb/intel/sandybridge/raminit: Reset internal state on fallback attempts
Some methods like discover_402x assume an clear state.
Should fix fallback attempt raminit failures.

Change-Id: I7a6fe044c17f5e0dbfa0e9b9d2aed0c3b6ae3972
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17471
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-28 01:04:39 +01:00
Elyes HAOUAS f100700a14 sb/broadcom/bcm5785/reset.c: Use tab for indents
Change-Id: If4350da1c9a7af5228be01a063486433860781e0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17583
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-28 01:04:03 +01:00
Elyes HAOUAS 2220f0d7c7 sb/ricoh/rl5c476/rl5c476.c: Use tab for indents
Change-Id: I3967d1ff0623037efa66927843e0c47f408832d7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17582
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-28 01:03:34 +01:00
Patrick Georgi 1b593e5ad7 util/crossgcc: fix using -D
Otherwise errors similar to "touch: cannot touch
'${TARGETDIR}/.GMP.6.1.0.success': No such file
or directory" might occur.

Change-Id: I4f24c93a25b7d567d3ce14a0415d20fd0778c9c8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/17603
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-28 01:01:58 +01:00
Nico Huber 696abfcfd3 nb/intel/x4x: Fix and deflate `dimm_config` in raminit
By shifting the `chan` right instead of left, values were always taken
from the DIMMs of the first channel. The diff-stat also looks like an
improvement.

Change-Id: I605eb4f9b04520c51eea9995a2d4a1f050f02ecc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17587
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-11-26 01:51:32 +01:00
Prabal Saha c7098a61b1 google/parrot: Fix keyboard interrupts, DSDT
Commit 967cd9a [ChromeOS: fix Kconfig dependencies] broke keyboard
interrupts on parrot by making SERIRQ_CONTINUOUS_MODE conditional on
CONFIG_CHROMEOS, which it should not be; fix by moving back under main
board specific options config.

Additionally, Windows [8/8.1/10] fails to enumerate the keyboard when
its ACPI entry is located under the SIO device since it is missing an
_HID entry, so add the appropriate value per ACPI spec 5 ch. 9.7

Change-Id: Ia69e9b326001d2026b15b4ec03c94f7d03c8a700
Signed-off-by: Prabal Saha <coolstarorganization@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17017
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-25 20:50:00 +01:00
Jeremy Compostella bf618cb94e libpayload: increase MAX_ARGC_COUNT
MAX_ARGC_COUNT limits the payload to ten parameters which is not
enough when used with a proprietary first stage bootloader providing
hardware description using around 20 parameters.

This patch makes the libpayload able to get up to 32 parameters.

Change-Id: I49925040d951dffb9c11425334674d8d498821f2
Signed-off-by: Jeremy Compostella <jeremy.compostella@gmail.com>
Reviewed-on: https://review.coreboot.org/17467
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-25 13:39:01 +01:00
Kyösti Mälkki f6fe2f1286 AGESA binaryPI: Fix cache-as-ram for x86_64
AMD_ENABLE_STACK was not called on x86_64 path for AGESA, while
it was for binaryPI.

Comments on BIST and cpu_init_detected were reversed, so fix those
too.

Change-Id: I0ddfaf51feb386a56d488c29d60171b05ff6fbc4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17551
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2016-11-25 10:32:07 +01:00
Kyösti Mälkki 619a245def x86 BIST: Fix missing include
Change-Id: I3d1a456f17073c99c9502da26e09cfde65380746
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17586
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24 21:39:41 +01:00
Werner Zeh 507c9c5976 mc_tcu3: Swap LVDS even and odd lanes for a certain hardware
Due to some LVDS cable constraints even and odd lanes needs
to be swapped on certain hardware. The hardware ID will be used to
distinguish between these two cases. The swapping itself will be done by
PTN3460, which is configurable for that.

Change-Id: I339b2321a8ed1bc3bbf10aa8e50eb598b14b15fa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/17576
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-11-24 19:24:03 +01:00
Werner Zeh ba7525df18 vendorcode/siemens: Add HWID to hwilib
Add the location of HWID field so that hwilib supports this
value as well.

Change-Id: If6d4695f861232231ac8f9c247c0a10410dac1c5
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/17575
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-11-24 19:23:50 +01:00
Arthur Heymans d83f9fc80e drivers/net/Kconfig: Hide REALTEK_8168_RESET in menuconfig
Resetting a Realtek 8168 NIC only makes sense on targets that have
such a device.

Change-Id: I8ac9e8da1d8ecaacb19b4610a9b75f107915d691
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17577
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24 19:09:38 +01:00
Arthur Heymans 59bf309a49 mb/ga-945gcm-s2l: Enable EC I/O decode range.
Change-Id: I021aae6130c475cb370b891ffaec6f1ad267540b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17580
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24 16:11:43 +01:00
Matt DeVillier 81ae67a634 Add Haswell Chromeboxes/Chromebase using variant board scheme
Combine existing board google/panther with new ChromeOS devices
mccloud, monroe, tricky, and zako, using their common reference board
(beltino) as a base.

Chromium sources used:
firmware-mccloud-5827.B 65bfee7 [haswell: No need pre-graphics delay...]
firmware-monroe-4921.B 1ac749d [Monroe: Disable KB/MS in ITE8772.]
firmware-tricky-5829.B 2db5322 [haswell: No need pre-graphics delay...]
firmware-zako-5219.B eacedef [haswell: No need pre-graphics delay...]

Existing google/panther board will be removed in a subsequent commit.

Variant setup modeled after google/reef

Change-Id: I5d7e0c2551e8b0707841032460c35615cefb2886
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17329
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-24 05:23:36 +01:00
Matt DeVillier b952b0d356 Remove board google/panther
Once #17329 is committed, no reason to have google/panther exist
as a separate board anymore.

Change-Id: I9a11273c39423d5ff33a7d1f91c8d8cffef97ec1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17538
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-11-24 05:23:13 +01:00
Naresh G Solanki 80ff038b28 driver/pc80/tpm: Runtime generate ACPI table for TPM driver
Runtime write acpi table for TPM driver.

Change-Id: I70896e5874c24f17fca0c48b138ad4917b273f5b
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17425
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-24 05:01:51 +01:00
Naresh G Solanki ab77cd4785 arch/x86/acpigen: Write DSM method with multiple UUID's
Enable generic way of writing DSM method which can write acpi table for
multiple UUID's.

Change-Id: Ic1fbdc0647e8fdc50ffa407887feb19a63cb48e4
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17424
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-24 05:01:37 +01:00
Kyösti Mälkki c36fa6433e x86 BIST: Declare function with inline in header file
Change-Id: Ieb5f1668a715ceadd5fe5ba0d121c865f1886038
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17572
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24 00:53:56 +01:00
Martin Roth ba1730b181 soc/mediatek/mt8173/spi.c: Change assert to if statement
Asserts are only fatal if CONFIG_FATAL_ASSERTS is enabled in Kconfig.
By default this is disabled, so the assert is generally just a printf.

Die if someone decides to pass in an invalid bus number for some reason.

Addresses coverity issue 1349858 - Out-of-bounds read

Signed-off-by: Martin Roth <martinroth@google.com>
Change-Id: I9d79bc336cbbfde31f655cfd271f101e7a90ab1b
Reviewed-on: https://review.coreboot.org/17484
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24 00:12:32 +01:00
Martin Roth c8c5ae101a nb/intel/i82810: Make sure DIMM size isn't negative
If smbus_read_byte returned an error when reading the DIMM size,
this value would be used as an offset into an array.

Check for the error, and set the DIMM size to 0 if there's
a problem.

Addresses coverity issue 1229658 - Negative array index read

Signed-off-by: Martin Roth <martinroth@google.com>
Change-Id: I6461a0fae819dd9261adbb411c4bba07520d076d
Reviewed-on: https://review.coreboot.org/17485
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24 00:11:12 +01:00
Martin Roth ff94e00362 soc/samsung/exynos5420/uart.c: Init new serial struct variables
The lb_serial structure had some new entries added, which were not being
filled in.

Fill in the values so they're not undefined.

Addresses coverity error 1354778 - Uninitialized scalar variable

Change-Id: Ia7ce07f6e4e058c91c2e063f3225497271ef93ff
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17482
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24 00:07:00 +01:00
Martin Roth a2267b8490 cpu/allwinner/a10/uart_console.c: Init new serial struct variables
The lb_serial structure had some new entries added, which were not being
filled in.

Fill in the values so they're not undefined.

Addresses coverity error 1354778 - Uninitialized scalar variable

Change-Id: I57f024c35f79397d0e9fd0c800b1b0f4075caac1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17483
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24 00:06:47 +01:00
Elyes HAOUAS a7bf068e82 northbridge/intel/i5000: Convert 'for(;;)' to 'die'
Change-Id: I1ceea759a40d740503bde725ad6d72fab4aa7971
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17006
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-23 23:57:46 +01:00
Kyösti Mälkki 9d9a552ac5 AGESA binaryPI: Fix PCI ID namespace
The defines of device IDs reflects the vendor namespace
the ID has been allocated from.

Change-Id: Id98f45d5984752a9e8c0484d4cb94e93e55b12f6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17510
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-23 23:02:57 +01:00
Naresh G Solanki 006c1e8778 soc/intel/skylake: Define early smbus functions
Define early smbus functions that can be used by mainboard to fetch spd.

Change-Id: Id170b2b8e6fb3ebb147f37bf433a27d1162dc11c
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17433
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-23 22:54:14 +01:00
Naresh G Solanki cd7068703e include/device/early_smbus.h: Declare smbus write function
Add declaration for smbus write. Early smbus access also needs smbus
write function specially to read spd for DDR4 wherein page has to be
switched by smbus write.

Change-Id: I246cbdf0b52923f01dd036f63df17bf9af043c9f
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-23 22:52:58 +01:00
Kevin Chiu 6fca307ced google/pyro: Update DPTF settings
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points.
   CPU  passive point:57, critical point:90
   TSR1 passive point:55, critial  point:70
   TSR2 passive point:65, critial  point:80

2. Update DPTF TRT Sample Period.
   CPU: 5s
   TSR0: 50s
   TSR1: 55s
   TSR2: 120s

BUG=none
BRANCH=master
TEST=emerge-pyro coreboot
Change-Id: Ib1b4b31a49d9396b1c5c9dd8d0b9b9998d01744f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17552
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-23 22:49:51 +01:00
David Hendricks 8883e0f126 veyron_*: Remove obsolete Chromeboxes
This removes brain, danger, emile, and romy from the tree.

This was cherry-picked from the chromeos-2016.02 branch (CL:345574),
but conflicts showed up in many files that were to be deleted anyway
possibly due to some widespread refactoring that was done between
then and now.

BUG=chromium:612660
BRANCH=none
TEST=none

Change-Id: Ie37140a9a4bb9d820a3fcbad6674b2fa737e1249
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1ebe5038a82162f6345e319de7578f26ccd68b73
Original-Change-Id: I11f7e0870916871d8f146a6871370ace76ddec49
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/412424
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17569
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-11-23 15:52:19 +01:00
Kyösti Mälkki 8bf3f7aef3 via/k8t890: Compose a list of PCI IDs
Change-Id: Ic474e17b70d64b63356a0ba7dd1649e5a6ff3a30
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17549
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2016-11-22 18:30:16 +01:00
Łukasz Dobrowolski 1de93a2947 src/vendorcode/amd/agesa: Fix casting
When IDSOPT_TRACING_ENABLED is TRUE build fails with
"cast from pointer to integer of different size"
Use "UINTN" as is done in Family 16h.

Change-Id: I362e67fc83aa609155f959535f33be9c150c7636
Signed-off-by: Łukasz Dobrowolski <lukasz@dobrowolski.io>
Reviewed-on: https://review.coreboot.org/17406
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-22 17:51:57 +01:00
Furquan Shaikh d0c00052d3 soc/intel: Use correct terminology for SPI flash operations
FPR is an attribute of the SPI flash component and not of the SPI bus
itself. Rename functions, file names and Kconfig option to make sure
this is conveyed correctly.

BUG=None
BRANCH=None
TEST=Compiles successfully.

Change-Id: I9f06f1a8ee28b8c56db64ddd6a19dd9179c54f50
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17560
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22 17:39:07 +01:00
Furquan Shaikh d2fb6ae813 spi: Get rid of flash_programmer_probe in spi_slave structure
flash_programmer_probe is a property of the spi flash driver and does
not belong in the spi_slave structure. Thus, make
spi_flash_programmer_probe a callback from the spi_flash_probe
function. Logic still remains the same as before (order matters):
1. Try spi_flash_programmer_probe without force option
2. Try generic flash probing
3. Try spi_flash_programmer_probe with force option

If none of the above steps work, fail probing. Flash controller is
expected to honor force option to decide whether to perform specialized
probing or to defer to generic probing.

BUG=None
BRANCH=None
TEST=Compiles successfully

Change-Id: I4163593eea034fa044ec2216e56d0ea3fbc86c7d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17465
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22 17:37:57 +01:00
Furquan Shaikh dc34fb60b4 spi: Get rid of max_transfer_size parameter in spi_slave structure
max_transfer_size is a property of the SPI controller and not of the spi
slave. Also, this is used only on one SoC currently. There is no need to
handle this at the spi flash layer.

This change moves the handling of max_transfer_size to SoC SPI driver
and gets rid of the max_transfer_size parameter.

BUG=None
BRANCH=None
TEST=Compiles successfully.

Change-Id: I19a1d0a83395a58c2bc1614b24518a3220945a60
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17463
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2016-11-22 17:33:33 +01:00
Furquan Shaikh c28984d9ea spi: Clean up SPI flash driver interface
RW flag was added to spi_slave structure to get around a requirement on
some AMD flash controllers that need to group together all spi volatile
operations (write/erase). This rw flag is not a property or attribute of
the SPI slave or controller. Thus, instead of saving it in spi_slave
structure, clean up the SPI flash driver interface. This allows
chipsets/mainboards (that require volatile operations to be grouped) to
indicate beginning and end of such grouped operations.

New user APIs are added to allow users to perform probe, read, write,
erase, volatile group begin and end operations. Callbacks defined in
spi_flash structure are expected to be used only by the SPI flash
driver. Any chipset that requires grouping of volatile operations can
select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and
define callbacks for chipset_volatile_group_{begin,end}.

spi_claim_bus/spi_release_bus calls have been removed from the SPI flash
chip drivers which end up calling do_spi_flash_cmd since it already has
required calls for claiming and releasing SPI bus before performing a
read/write operation.

BUG=None
BRANCH=None
TEST=Compiles successfully.

Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17462
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22 17:32:09 +01:00
Renze Nicolai 282c832279 mainboard/ms7721: Add MSI MS-7721 (FM2-A57MA-E35)
Adds support for the MSI MS-7721 (FM2-A75MA-E35) motherboard.

Tested by building coreboot with:
 - VGA bios (needed for onboard video)
 - XHCI firmware
 - SeaBIOS payload

CPU: AMD A8-6500 APU
RAM: 2x 2GB Samsung M378B5673EH1

Confirmed booting using:
 - USB stick with Arch Linux (kernel 4.7.5)
 - Gentoo live CD from SATA dvd drive
 - Gentoo installation from SATA harddisk (kernel 4.4.26)

Change-Id: I757e011de01ca9f340fd524b10e7fa3f291d53e3
Signed-off-by: Renze Nicolai <renze@rnplus.nl>
Reviewed-on: https://review.coreboot.org/17495
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-22 05:19:06 +01:00
Renze Nicolai a688b7cb7b mainboard/ms7721: Copy files from "asus/f2a85-m" to "msi/ms7721".
This patch adds a copy of the Asus F2A85-M code with only minimal changes.
(to ensure that the code compiles)

A second commit will be published to remove the copied code parts that
don't apply to the MS-7221 and to make everything else actually work
on the MS-7221 board.

Change-Id: I1426c0876c7bfeb264231c0d338301133c721484
Signed-off-by: Renze Nicolai <renze@rnplus.nl>
Reviewed-on: https://review.coreboot.org/17494
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-22 05:18:34 +01:00
Kyösti Mälkki 809b5881a9 nb/intel/sandybridge/raminit: Do not log inside busy-wait loop
Time spent in printk() is highly unpredictable, depending of the
enabled consoles. If only CBMEM console is enabled, debugstring
is repeated tens of times, consuming preram_cbmem_console storage.

Change-Id: I2b0d9bd11c294d988a0eb84b90e77d5cc7f1f848
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17516
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22 05:02:45 +01:00
Kyösti Mälkki ebc21d125f intel/sch: Switch to MMCONF_SUPPORT_DEFAULT
Untested, only affected board is iwave/iwRainbowG6.

Change-Id: Ie3c40ede85c9f89b54804dd2a411645be93911bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17528
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22 04:17:03 +01:00
Kyösti Mälkki bac0fad408 Remove explicit select MMCONF_SUPPORT
Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT.

Platforms that remain to have explicit MMCONF_SUPPORT are
ones that should be converted.

Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17527
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22 04:15:11 +01:00
Kyösti Mälkki f748eb7ab7 intel FSP sandy/ivy: Move select MMCONF_SUPPORT
Note: Platforms have no MMCONF_SUPPORT_DEFAULT.

Change-Id: I8a02ea78957fca23b1cf161a00d5e3edda73d683
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17543
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22 04:14:49 +01:00
Arthur Heymans c79ced0a68 mb/gigabyte/ga-g41m-es2l: Add MAX_CPU = 4 in Kconfig
This motherboard support Intel core 2 quads.

Before this change SeaBIOS was not usable, due to it crashing before it
got to load anything.

Change-Id: Ifdaaceace04f9ba0753aab2d3b05c0519367f91f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17537
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-22 02:00:52 +01:00
Arthur Heymans 5d0a93d5e7 mb/ga-g41m-es2l: Correctly configure PCI IRQ in ACPI
Obtained from vendor bios DSDT, under "Device (HUB0),
Name (_ADR, 0x001E0000)".

The schematics also indicate that the INTA-D are hardwired to these
PIRQ lines.

Change-Id: I8e1c6cb986a2b345a5e1fddd454c7fb12fb8256a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17099
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-21 23:58:15 +01:00
Martin Roth 53bd26f531 drivers/intel/fsp2_0: Check for NULL before using pointer
The cbmem routines pass back NULL on error.  Check for this before using
the pointer.

Addresses coverity issue 1365731 - Dereference null return value

Change-Id: I92995366ffb15afd0950b9a8bbb6fe16252b2c38
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17480
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-21 23:45:06 +01:00
Martin Roth ad6c885ce4 console/vtxprintf.c: cast precision to size_t for string length
If no maximum string length is specified, we're intentionally passing a
value of -1 to get the string length so that it's not limited.  This
makes checking tools unhappy, so actively cast it to size_t before
passing it into strlen to show that it's not an accident.

Addresses coverity issue 1129133 - Argument cannot be negative

Change-Id: I40f8f2101e170a5c96fcd39c217aa414f4316473
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17479
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-21 23:44:18 +01:00
Martin Roth 128c104c4d nb/intel: Fix some spelling mistakes in comments and strings
Change-Id: I4a8297397d878e38516c8df19dd311c7ef19ec06
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17478
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-21 23:43:54 +01:00
Brandon Breitenstein c6ec8dd1cb fsp2_0: implement stage cache for silicon init
Stage cache will save ~20ms on S3 resume for apollolake platforms.
Implementing the cache in ramstage to save silicon init and reload
it on resume. This patch adds passing S3 status to silicon init in
order to verify that the wake is from S3 and not for some other
reason. This patch also includes changes needed for quark and
skylake platforms that require fsp 2.0.

BUG=chrome-os-partner:56941
BRANCH=none
TEST=built for reef and tested boot and S3 resume path saving 20ms

Change-Id: I99dc93c1d7a7d5cf8d8de1aa253a326ec67f05f6
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/17460
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-21 23:43:28 +01:00
Marshall Dawson 5c325491ca util/inteltool: Fix bay trail ahci device
Use a unique bus/device/function if a bay trail LPC bridge was found.

TEST=Run on MinnowBoard MAX Turbot and customer's LynxPoint-LP.

Change-Id: Ib4b50aaf9817ac94f46c28925081540676226d84
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17464
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-21 23:38:40 +01:00