Commit Graph

27796 Commits

Author SHA1 Message Date
Tristan Corrick 9a085745f1 sb/intel/lynxpoint: Add PCI IDs for more SKUs
The PCI IDs were taken from the Intel Lynx Point datasheet [1].

[1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub
    (PCH) Datasheet, revision 003, document number 328904.

Change-Id: Ie4a264e9325d185334c3d7f7d2ed3c394ac33059
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01 20:27:26 +00:00
David Wu eb38fa7e95 mb/google/fizz/variants/karma: Rename kalista to karma
Change the variant name from kalista to karma.
According to the CL:1298319, the baseboard name is kalista
and the board name is karma.

BUG=none
BRANCH=master
TEST=emerge-kalista coreboot chromeos-bootimage

Change-Id: Idea295cc14249721a6dc0fc4e2ef6470d43e16eb
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29314
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01 13:26:06 +00:00
Elyes HAOUAS 9e4fa330ef sb/intel/common/pciehp.h: Add missing license header
Change-Id: Ia669b25683c138d96be00db90d01cf406db4c2eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29404
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01 11:26:33 +00:00
Elyes HAOUAS c4e4193715 src: Add missing include <stdint.h>
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01 11:25:07 +00:00
Martin Roth 1956a00953 soc/amd/stoneyridge: Fix get_cpu_count()
In commit 41baf0c3ff (soc/amd/stoneyridge: Remove dev_find_slot where
possible), the register being read was changed accidentally from
HT_DEV (Device 18h, Func 0) to NB_DEV (Device 18h, Func 5)

This doesn't return the correct value, and causes Grunt to reboot.

BUG=b:118721473
TEST=Boot grunt

Change-Id: I7b73358a074dd27639aafead7c8b39f0fad5685f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-10-31 22:00:03 +00:00
Martin Roth 3424f38ae6 soc/amd/stoneyridge: Get rid of domain_read_resources
The function domain_read_resources() didn't have any code to actually
reserve any resources - it was just creating an empty resource entry.

I looked at fixing it to actually reserve the space, but the values in
the registers at the point when this runs aren't the final values that
we want to reserve anyway, they're temp values with a range much larger
than we want to reserve.

I next looked at moving the amd_initcpuio() function earlier so that we
could get the correct values for the registers, but even that doesn't
give us what we really want.

Ultimately removing this whole function seems to be the right thing.

BUG=None
TEST=Verify that the only resource that changes is the empty resource:
PCI: 00:18.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 1 index 1080

Change-Id: I83bd3ea8db141416632c12fc883386070363f2f1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-31 21:56:09 +00:00
Duncan Laurie 29f2b258c8 ec/google/wilco: Unmute audio on init
The speakers start up muted, and the EC must be told by the BIOS
to unmute it.  This helps prevent popping noises on boot/resume.

Change-Id: I693f1d01e46e19362ef8fd0d5b3f4930967b5a12
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-31 18:31:15 +00:00
Duncan Laurie f5d688a5a2 ec/google/wilco: Add ACPI SuperIO devices
Add ACPI devices for the basic SuperIO functionality provided by the EC
for PS/2 keyboard, PS/2 mouse (trackpad emulation), and legacy UART.

The specific defines to enable these devices should be declared by the
mainboard before including this ASL, the same as the Chrome EC behavior.

Change-Id: I910940ebf26b8758ab12d695e1eba9c668c640c6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-31 18:31:04 +00:00
Duncan Laurie e52840a9ed ec/google/wilco: Add ACPI EC event handlers
Add methods to handle ACPI EC events at runtime.  Currently only
some common events are handled like lid switch and battery info,
and the event status is printed for debug on other events.

Change-Id: Ic0bd070940c8a2dfa6a251f3464301418bdb69c1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-31 18:30:51 +00:00
Duncan Laurie 4af38d440d ec/google/wilco: Add ACPI battery and AC objects
Add the expected objects (_BST, _BIF, _BIX) for reading battery
information and status from the embedded controller, and the
expected objects for reporting AC power status.

The battery was tested by booting with a battery attached and checking
that it is present in /sys/class/power_supply/BAT0 and that the values
are consistent and within expected ranges.

The AC device was tested by checking the AC status in sysfs when AC
is inserted or removed while the system is running.

Change-Id: Ie996891c383c9e990736690aef9795512ad6d35a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-31 18:30:38 +00:00
Duncan Laurie a802be2910 ec/google/wilco: Add ACPI EC infrastructure
Add the base ACPI support for the Wilco embedded controller, using
ASL 2.0 syntax throughout.

This includes the EC device and its resources, as well as the layout
for the EC RAM and the functions needed to read and write to the EC RAM.

The EC RAM address space is typically read/write, and so the ACPI EC
device expects that a defined Field can be read and/or written.  With
this EC the read and write address spaces are different.  For example,
a read from address zero will return data that is unrelated to what a
write to address zero expects.

This makes using a typical OperationRegion to describe the EC RAM
address space somewhat impracticle, since field definitions would
overlap.  Instead, methods are provided for reading and writing to an
EC RAM offset, and the EC RAM layout is defined as a Package that
describes offset+mask for read or write fields within the EC RAM.

Change-Id: If8cfdf2633db1ccad4306fe877180ba197ee7414
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-31 18:30:29 +00:00
Duncan Laurie ea98b40efe ec/google/wilco: Add a bootblock function for early init
Add a function for use in bootblock stage that performs early init
of the EC, in particular setting it up for UART passthrough so a
legacy serial port can be used by the host.

This needs to be called by the mainboard that intends to use it
in bootblock in order for the UART to be available in later stages.

Some of the PNP style programming may look odd, but it is following
the EC specification which is not entirely standard.  This code has
been tested on a board with this EC and it is functional.

Change-Id: I9d6935a9fdf0d7290a94bf2ee565ef2a7c00ecc7
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29121
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-31 18:30:20 +00:00
Duncan Laurie 3fbe1949b1 ec/google/wilco: Save and restore PS/2 data for S3
Send a command to the EC on the way into S3 suspend state telling
it to save the PS/2 data, and on resume send it a command for
restoring the PS/2 data that was previously saved.

Change-Id: Ic4b5d6d2656dbb1c476b9211b0d60c71b0cd7b32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29120
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-31 18:30:12 +00:00
Duncan Laurie d978174d1d ec/google/wilco: Add SMM handlers
Add EC handlers for specific SMM actions:

- on entry to sleep state tell the EC to save state and to prepare for
the host to enter sleep
- on ACPI enable/disable send command to the EC
- add a function to print SMI reasons when eSPI SMI is received

These need to be called by the mainboard handlers which will be done
when a board is added that uses this EC.

Change-Id: Ibabdc1462e0a8df405f9520244b83684e2ccf2f5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29119
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-31 18:30:04 +00:00
Duncan Laurie 421a962cc6 ec/google/wilco: Report BIOS progress to the EC
The EC expects to receive updates about the BIOS boot progress.  This is
used for the EC logging to track system boot completeness.  If the EC is
not informed about BIOS progress it will turn the system off 30 seconds
after the boot starts.

Change-Id: I693c3930117db2b69a119aee0380d6f303c4881c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29118
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-31 18:29:43 +00:00
Duncan Laurie b29e2d58f2 ec/google/wilco: Add devicetree chip infrastructure
Add a chip_operations structure for Wilco EC and hook it into the device
tree so it can be initialized at boot.

Reserve the device resources specified in Kconfig, which will also
create the device IO windows if they have not been created in bootblock.
If the IO windows already exist (becauase they were specified in the
mainboard devicetree.cb) then this will find the existing entry instead.

During device init stage prepare the keyboard for use, which is required
for it to be functional in firmware and OS with this EC.  Also send a
command to the EC telling it to pass the power button through to the
host for processing.

Change-Id: I0adb01cf394f939f4a28aeb47fe4d0bcda5957d9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29117
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-31 18:29:36 +00:00
Duncan Laurie 2f954921b8 ec/google/wilco: Add power related mailbox commands
Add EC mailbox commands that are related to the power and state of the
system.  These commands include:

- read the power status registers from the EC
- read & clear the power status registers
- helper function to read the current lid state
- tell the EC why the host is about to power off
- tell the EC that the host is about to enter a sleep state

Change-Id: Iaa7051b4006e3c1687933e0384d962516220621f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29116
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-31 18:29:26 +00:00
Duncan Laurie b0bf280be4 ec/google/wilco: Add mailbox commands
Add basic supported mailbox commands for this embedded contrlller,
and define some command functions to retrieve and print information
about the EC.

Change-Id: Ibcef7d58e1852fdb2e52b97acd4b51a26dd8cd77
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-31 18:29:19 +00:00
Duncan Laurie 5f6f1dab7d ec/google/wilco: Add mailbox helper functions
Add helper functions that make it more convenient to send and receive
the most common types of commands to the Wilco embedded controller.

Change-Id: I9cee1a3b2f9d507f6ecdfae9f4a34ba59056cb91
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29114
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-31 18:29:09 +00:00
Duncan Laurie 21dde8b25f ec/google/wilco: Add Wilco EC mailbox interface
The Google "Wilco" Embedded Controller is a new embedded controller that
will be used in some future devices.  The mailbox interface is simliar
to the existing Chromium EC protocol version 3, but not close enough
that it was convenient to re-use the full Chrome EC driver.

This commit adds the basic mailbox interface for ramstage which will be
used by future commits to send varous mailbox commands during the boot
process.  The IO base addresses for the mailbox interface are defined in
Kconfig so they can be changed by the mainboard if needed.

Change-Id: I8520dadfa982c9d14357cf2aa644e255cef425c2
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-31 18:29:00 +00:00
Loop_Wu 370123e1a3 Veyron: add Hynix H9CCNNNBKTMLBR-NTD ddr with RAMID '00Z1'
Confirm with RK, H9CCNNNBKTMLBR-NTD uses this sdram config.
  sdram-lpddr3-hynix-4GB.inc

BUG=b:117967129
BRANCH=master
TEST=None

Change-Id: I98afc33fd2cb61343be0dcdc007add75bee9c2af
Signed-off-by: Loop_Wu <Loop_Wu@asus.com>
Reviewed-on: https://review.coreboot.org/29366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-31 16:00:06 +00:00
Nico Huber 718c6faff4 reset: Finalize move to new API
Move soft_reset() to `southbridge/amd/common/` it's only used for
amdfam10 now.

Drop hard_reset() for good.

Change-Id: Ifdc5791160653c5578007f6c1b96015efe2b3e1e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-31 15:29:42 +00:00
Werner Zeh 30cf14ff3f security/tpm: Add function to measure a region device
Add a new function which can hash a given region device and extend a PCR
in the TPM with the result. The needed SHA algorithms are included from
3rdparty/vboot and thus not duplicated in the coreboot tree.

For now VB2_LIB is not usable in postcar stage. Follow-up commits will
add the ability to use the lib in postcar as well. Once this feature is
ready, the library will be included in postcar stage to make this
function available in every stage.

Change-Id: I126cc3500fd039d63743db78002a04d201ab18aa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/29234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-31 14:14:16 +00:00
Patrick Georgi 5220aeab6e security/vboot: build vboot_fw20.a per stage
When used more widely across the tree, we don't want to have
to worry if all its users are on the same architecture
(eg. aarch32 vs aarch64), so just build their own library for
each stage.

Change-Id: Ib6807ff73c2713f3b23f43055325b2c40ff1a17d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-31 12:15:29 +00:00
John Zhao b3c27f0a24 soc/intel/apollolake: Revert the w/a nWR_24 setting
GLK FSP 2.0.6.0 has properly determined MR1 value during InitializeJedec.
Revert the w/a code "odt_config |= nWR_24" in coreboot.

BUG=b:118422998
CQ-DEPEND=CL:*703187
TEST=Verified booting to kernel.

Change-Id: I6dd3c14b2048259a5518e1f72ff1061b9c5c7dfe
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-31 05:38:42 +00:00
John Su 2257a35862 mb/google/poppy/variants/nami: Perform PL2 setting for syndra
According to syndra thermal table, PL2 need to check cpu id.
Set up syndra PL2 value.
1. KBL_U PL2 is 25w.
2. KBL_R PL2 is 29w.

Refer to b:116836990#comment10.

BUG=b:116836990
TEST=The thermal team verify OK

Change-Id: I766a886121a089683565608252b4c176c70e88a3
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
2018-10-31 03:50:57 +00:00
Shelley Chen 7129cbf2f1 soc/intel/icelake: Open ports 0x60,0x64 for keyboard controller
BUG=b:112110028
BRANCH=none
TEST=boot into recovery
     in ec console:
     kblog on
     (type on keyboard)
     kblog
     make sure buffer is not empty

Change-Id: I6525c2a46eef835dc64682466364a5b8fbb35226
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-10-31 02:18:54 +00:00
Elyes HAOUAS b0817b0fe5 src: Move shared amd64 and IA32 MSRs to <cpu/x86/msr.h>
Change-Id: Ic9022a98878a2fcc85868a64aa9c2ca3eb2e2c4e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29177
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30 20:20:00 +00:00
Elyes HAOUAS 8a643703b8 {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros
Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29243
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30 20:18:53 +00:00
Martin Roth 50f2e4ccec soc/amd/stoneyridge: Set IOMMU support to follow device setting
Instead of forcing the IOMMU to be enabled, change it to only be enabled
if the device is enabled in devicetree.

BUG=b:118612241
TEST=Verify that IOMMU is disabled.

Change-Id: I6cfd6c81f47de23c54a49ec7cf87b219215ced5e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-10-30 20:12:00 +00:00
Martin Roth d80884ea5a mb/google/kahlee: Disable IOMMU
Unfortunately Stoney has an issue where enabling the IOMMU causes
a 10%-50% decrease in the integrated graphics performance.  It is
also disabled by default on other stoney platforms.

BUG=b:118612241
TEST=Verify that IOMMU is disabled.

Change-Id: Ia396c7227cb21461ec8afbdf746721d4fb28083d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29342
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30 20:11:51 +00:00
Richard Spiegel 41baf0c3ff soc/amd/stoneyridge: Remove dev_find_slot where possible
The procedure dev_find_slot has 3 main uses. To find configuration
(devicetree), to verify if a particular device is enabled at build \
time, and to get the address for PCI access while in bootblock/romstage.
The third use can be hidden by using macros defined in pci_devs.h,
making it very clear what PCI device is being accessed. replace the
temporary pointers to device used with PCI access with SOC_XXX_DEV where
XXX is the device being accessed, and remove the setting of the temporary
pointers.

BUG=b:117917136
TEST=Build grunt.

Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-30 16:57:53 +00:00
Mario Scheithauer 58bf3e7632 siemens/mc_apl3: Add new mainboard variant mc_apl3
This mainboard is based on mc_apl1. In a first step, it concerns a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl3 mainboard will follow in separate commits.

Change-Id: I963ec63bccf71296c3fdabfcf9f3009c2febc791
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-10-30 12:16:30 +00:00
Patrick Rudolph e63a5f1e7f drivers/spi: Winbond specific write-protection enable
Extend the SPI interface to enable write-protection.

Tested on Cavium EVB CN81xx using W25Q128.

Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-30 12:15:57 +00:00
Jonathan Neuschäfer 61322d7ad2 security/tpm: Fix references to tpm_setup function
Change-Id: Ia97ddcd5471f8e5db50f57b67a766f08a08180b1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/29349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-30 12:12:50 +00:00
Elyes HAOUAS dfbe6bd5c3 src: Add missing include <stdint.h>
Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29312
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30 09:41:08 +00:00
Paul Menzel b06f8ddfe8 Documentation/riscv: Improve `index.md`
1.  Add dot/period to the end of sentences
2.  Remove blank line at the end of the file
3.  Break lines after 75 characters
4.  Use RISC-V spelling
5.  Add comma for clarity

Change-Id: Icbe803dfbe92ca7850204a1a9f7175befe9c8bcf
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/28654
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30 02:10:44 +00:00
Philipp Hug 1ed082bc8b riscv: simplify timer interrupt handling
Just disable the timer interrupt and notify supervisor.
To receive another timer interrupt just set timecmp and
enable machine mode timer interrupt again.

TEST=Run linux on sifive unleashed

Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/29340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-30 02:09:05 +00:00
Philipp Hug d4ab5bbc82 src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode
Pointer to opcode increases by unit uint16_t not byte.

Change-Id: I2986ca5402ad86d80e0eb955478bfbdc5d50e1f5
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/29339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-10-30 02:07:58 +00:00
Philipp Hug bb7f41d85a sifive/fu540: correct cbmem support
Return correct memory location for cbmem instead of incorrectly returning memory size.

Change-Id: If7f490a46edebb04c2280bf317d1adacef08f30d
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/29197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xiang Wang <wxjstz@126.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-30 02:07:12 +00:00
Ronald G. Minnich 3d8e53f85a Add selfboot to the romstage
Now that bounce buffers are gone, and we can elide the selfload checking
code at build time, it is safe to add selfboot to the romstage.

Make it so.

This required a few other tweaks to rules.h and selfboot.c
to make it buildon ARM.

Change-Id: Ib6540921ad7cd7d58bfeab881d3978325b303cc2
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/29338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-30 00:37:04 +00:00
Marshall Dawson 46fc684783 x86/mp_init: Add configurable stack size for SMM relocate
A stack overrun has been observed on AMD64 CPUs during the SMM module
relocation process.  Change the assumed required size from equaling the
save structure's size to a Kconfig symbol.

A value of 0x400 doubles the size used by AMD64 systems and maintains
the size used by EM64T.

BUG=b:118420852
TEST=S3 on Grunt and verify 0x2f000-0x30000 uncorrupted

Change-Id: Ib1d590ee4afb06ca649afd6ad253cdfd969ae777
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-29 18:01:43 +00:00
Shelley Chen bf00401e8a mb/google/poppy/variants/nami: Add field to identify single channel DDR
Variants of Nami need to accommodate single channel DDR.  Will use
GPP_D10 on nami for identification.  GPP_D10 will return 1 when device
is using single channel DDR and 0 when using dual channel DDR.

BUG=b:117194353
BRANCH=None
TEST=dmidecode | grep Channel and make sure that the correct number of
     channels gets returned.

Change-Id: If86ab2c5404c4e818ce496ea935227ab5e51730a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-29 16:49:43 +00:00
Frans Hendriks 6cc937e687 src/drivers/pc80/tpm/tis.c: Dont use port value when invalid.
port is allocated in ACPI, without checking for value.
Don't use port value when zero.

BUG=N/A
TEST=Portwell PQ-M107

Change-Id: Ia44281b82d003b29bffbf985b774ddd661b65c4e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/29331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-29 14:27:16 +00:00
Peter Lemenkov 9b83f760cd mb/lenovo/t430: Set USB always on when calling SMI sleep
Looks like we must do it in the same way as in l520, t420, t420s,
t430s, t520, t530, x201, x220, x230 models. No idea why t430 should be
handled differently.

Change-Id: Ic4851022267caca267b667b4e3c327838e0a0b66
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29031
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-29 11:26:36 +00:00
Paul Menzel 8950706169 mb/lenovo/t400: Use acpi_s3_resume_allowed()
Apply commit 12d681b2 (intel/i945 gm45: Use acpi_s3_resume_allowed())
also to the Lenovo T400.

See also commit 42ae0bae with Change-Id
I4e1e0ccf2abbe175c0e5ddcbb6ee7bf6afb1ae88 (mb/lenovo/x200: Use
acpi_s3_resume_allowed())

Change-Id: I9d4ac711375977a979a8b3e5606e2197847e88de
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-29 11:26:02 +00:00
Patrick Rudolph 82b1e019a5 Documentation: Improve payload fit
* Convert '' to `
* Add example how to use mkimage

Change-Id: Id83db3db51582cb0d6ded7f3152b5549fba1f2e7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-29 11:21:47 +00:00
Jonathan Neuschäfer 84bf089f6a Documentation/mainboard: Add emulation/spike-riscv.md
Move the usage instructions from their ad-hoc place in Kconfig.name to
the Documentation directory, and expand them a bit.

Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-10-29 11:19:34 +00:00
Nico Huber c5f4a8c8f0 tegra210_lp0: make sure to build with compiler.h included
Like in ce1064e (tegra124_lp0: make sure to build with compiler.h
included), fix builds where `compiler.h` is needed.

Change-Id: If4b60a9db4520b58e48339a7e2726f2545cb4102
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-29 08:40:37 +00:00
Patrick Georgi c6382cd4bf soc/intel/*: Make FSP header path user configurable
Required to compensate for Chrome OS' tree differences

Change-Id: I01fe80b55c69ff57da1c96a76bd1d9b5a2d4a9a8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-27 23:58:15 +00:00