The current power sequencing for the SSD does not work in a non-serial
enabled BIOS image. It appears that the FSP scans the PCIe RPs before
the SSD has time to prepare itself for PCIe, so the FSP disables the RP
and so depthcharge cannot find a boot disk.
Changing the power sequence timing to enable power in bootblock and
deassert reset in ramstage follows the SSD's power sequence and
allows it to be discovered by the FSP so the RP does not get disabled.
BUG=b:199714453
TEST=build, boot into SSD, and run reboot stress test.
Change-Id: I5e7943a6cc88bc02bcbd97a1086b2d8044d7b1c3
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Load GSI FW in ramstage and make it part of RW
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I3d9caa0921fcf9ad67f1071cdf769a99fb6d1a30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Loading QUP FW as per herobrine and piglin configuration
for I2C, SPI and UART.
As part of the code clean up, update the header files of the
QUP drivers with the correct path.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: Ic218c6a91ffc4484830446d707d1f3403e2dc46b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
BUG=b:191776301
TEST=dewatt build no longer fails when a check for non-existent files
in LIB_SPD_DEPS is added (following commit).
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Iee0c5e8b71f7cc7c016a38a60569daff99a55027
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Remove the override in guybrush devicetree that configured in-band eSPI
alerts. This will result in guybrush using dedicated open-drain eSPI
alerts. Guybrush boards must be reworked to connect the eSPI alert line,
otherwise they will not boot with this change
BUG=b:198596430
TEST=Boot on reworked guybrush
BRANCH=None
Change-Id: I185eec773336fb662d9fe7f4c11991813e4d7cd6
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57778
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change replaces the device tree walks with device pointers by
adding alias for igpu (integrated graphics) device in the tree.
Change-Id: I6d159f6dc674f4a0b38ebb553c5141105405a883
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change replaces the device tree walks with device pointers by
adding alias for following devices:
1. FPMCU
2. WWAN
Additionally, this change drops the __weak attribute for variant_has_*
functions as there is no need for different implementations for the
variants.
Change-Id: I8af5e27f226270e6b40a50640c87de99a5a703f7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
On some dedede variants, USB port 2.3/3.3 might be connected to either
LTE device or Type-A external port depending upon FW_CONFIG. Commit
856b579 ("mb/google/dedede/var/kracko: Update LTE USB port
configuration") enabled Type-A external port by default in override
tree and updated the config dynamically for LTE USB device if
FW_CONFIG indicated support for it. This was required because sconfig
lacked the support for multiple override devices. Commit
b9c22e0 ("util/sconfig: Compare probe conditions for override device
match") fixed this behavior in sconfig and now we can add multiple
override devices using different FW_CONFIG probe statements in
override tree. Hence, this change moves the LTE USB device to override
tree for metaknight, kracko and drawcia variants.
In addition to that, drawcia needs to be update reset_gpio depending
upon board_id. Thus, alias `lte_usb2` is used in drawcia override tree
to fix the reset_gpio for older boards i.e. board_id <= 9.
Change-Id: Ie5b205594680d9c2b8543c5c99325d95620cafd2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
On sasukette, codec device might be either 10EC5682 or RTL5682
depending upon the provisioned FW_CONFIG value for
AUDIO_CODEC_SOURCE. The HID for the device was updated in ramstage.c
because sconfig lacked the support for multiple override
devices. Commit b9c22e0 ("util/sconfig: Compare probe conditions for
override device match") fixed this behavior in sconfig and now we can
add multiple override devices using different FW_CONFIG probe
statements in override tree. Hence, this change moves the codec device
to override tree and drops the special handling in ramstage.c
This change also probes for UNPROVISIONED value of FW_CONFIG for
"10EC5682" device since some devices might have shipped with
UNPROVISIONED value and using "10EC5682" device.
Change-Id: I909a29c3df0cbb7ac3c07ca7663a49ad47007232
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change replaces the device tree walks with device pointers by
using alias names for the following devices:
1. PMC MUX connector
2. SPI TPM
3. I2C TPM
Change-Id: I38f87d3a90a7253f2a29aba7db9a9f9744985494
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change replaces the device tree walks with device pointers by
adding alias for dptf_policy generic device in the tree.
Change-Id: I8fd5476a9cea84ab8b2678167b3e0504eecacf6c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
USB3 MB doesn't have re-timer. Thus we have to configurate the AUX pin.
For now, we use USB3 DB to determine the USB3 MB.
BUG=b:197907500
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ide45c77e0a6f736a02d5dc9ad05aa1ef9e754fa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
To save the S3 power, USB3_HUB_RST_L is externally pulled up to a
weak resistor so we have to reset the hub via GPIO84 as early
as possible. Otherwise the USB3 hub may be not usable.
BUG=b:199822702
TEST=measure voltage of USB3_HUB_RST_L as 1.8V
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie87d631e83ede819ee9f9951dfc6517beae50247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57663
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update thermal setting from thermal team.
BUG=b:200134784
TEST=build and verified by thermal team.
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: If74c3bc19cf4abd64d646b842cbb6a61b910e933
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
NVMe needs extra time to run boot process, enable power and deassert
reset for NVMe earlier in the boot flow that primus can successfully
boot into OS with non-serial coreboot.
BUG=b:199967106
TEST=USE="project_primus" emerge-brya coreboot and verify it builds
without error.
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I9c66efe96515347502d059556052c764c1be5d09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Apart from the u8, u16 and u32 types, the bool type is used in this file
so include types.h instead of stdint.h to have bool defined too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I95f037deb0fe11b717586df655065bfbb33b0d23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
These statements fit on a single line. Reflow them to ease future works.
Change-Id: Ie18e9a00f67b999fdcedcab3c28b68e34bc93da4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Follow FIBOCOM_L850-GL Hardware User Manual_V1.0.8.
BUG=b:180166408,b:187691798
TEST=measure WWAN power off by scope is meeting the spec.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I6b2725cd61d5b54bc7fd70a9daffd29e7b43690b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When the century byte was reserved, the debug_level was accidentally
converted from an enum to a hidden value. Change it back to an enum.
Fixes: f05bd8830d ("mb/system76/*: cmos.layout: Reserve century byte")
Change-Id: Id88a7aed7b2fc793fd003db5b45f3f201b1a7630
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
The `CaVrefConfig` FSP-M UPD describes how the on-die Vref generators
are connected to the DRAM. With the exception of an early Skylake RVP
board (which doesn't have coreboot support), mainboards using DDR3 or
LPDDR3 memory should set `CaVrefConfig` to 0, whereas mainboards with
DDR4 should set `CaVrefConfig` to 2. MRC uses this information during
memory training, so it is important to use the correct value to avoid
any issues, such as increased power usage, system instability or even
boot failures.
However, several Skylake DDR4 mainboards don't set `CaVrefConfig` to 2.
Although they can boot successfully, it's not optimal. For boards that
set `DIMM_SPD_SIZE` to 512 (DDR4 SPD size), set `CaVrefConfig` to 2.
Change-Id: Idab77daff311584b3e3061e9bf107c2fc1b7bdf1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
vboot_reference is introducing a new field (ctx) to store the current
boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged
in both vboot flow and elog_add_boot_reason in coreboot.
In current steps of deciding bootmode, a function vb2ex_ec_trusted
is required. This function checks gpio EC_IN_RW pin and will return
'trusted' only if EC is not in RW. Therefore, we need to implement
similar utilities in coreboot.
We will deprecate vb2ex_ec_trusted and use the flag,
VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag
in coreboot, verstage_main.
Also add a help function get_ec_is_trusted which needed to be
implemented per mainboard.
BUG=b:177196147, b:181931817
BRANCH=none
TEST=Test on trogdor if manual recovery works
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This now skips all of the pieces done by PSP_verstage.
BUG=None
TEST=Boot Guybrush with & without PSP_verstage
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5a6b8e2284e232c30c9f36ea7c6ab044e2644f7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Since the PCIE training for the USB WWAN card is no longer being run,
we can initialize the GPIOs the same for all WWAN cards.
BUG=b:193036827
TEST=Boot and reboot with fibocom FM350-GL & L850GL modules
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idc9a7cb883fc8dd6bbc6077b8ea99182f17f888b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57317
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Check to see if the PCIe slot needs to be activated for the WWAN card.
If it doesn't, leave it unused so it will be powered off and not do
the PCIe training.
BUG=b:193036827
TEST=Boot & Reboot guybrush with both PCIe & USB WWAN cards.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I79c32e4814672c03ee0821786d5be1c77fd1b410
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO field of fw_config.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:200009010
TEST=ALC5682-VD/ALC5682-VS audio codec can work
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I09c7830fff6b318cf1a1f4a44ee0a819691f7c58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57673
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MIPI camera support for OVTI2740
BUG=b:196937374 b:194926283
TEST=Build and boot on Kano
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I248c64b9460c898f9faa5f7ac8cf339a9c814013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch has changes to support multiple camera modules, base on the value set in the SSFC_CONFIG.
BUG=b:198235323
TEST=tested the changes with redrix 5MP(ov5675/hi556) camera.
Change-Id: I71c8355617171ec7d08862759b87d4bf12ce2924
Signed-off-by: Arec Kao <arec.kao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57272
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCIe WWAN module used on brya0 requires control over 4 signals to
successfully power it on. It is desirable to do this before passing
control to the payload, because the modem requires a ~10 seconds
initialization phase before it can be used.
The corrected sequence looks like:
1) Drive device into full reset and enable power in bootblock
2) Deassert FCPO in romstage, after power rails stabilize
3) Deassert WLAN_RST#, then WLAN_PERST# in ramstage
BUG=b:187691798
Change-Id: I10f15a4dcfd86216c334fb24b4693ea250d35ee4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This GPIO is used to force the USB retimers on Type-C ports to stay in a
powered state and can be used e.g., during a firmware update to the
retimer to force power on even when no device may be connected to the
port. However, its power rail is controlled elsewhere and coreboot is
not applying a FW update, so this GPIO should be driven low instead.
BUG=b:193402306
TEST=compile
Change-Id: I976a0b8252b31aacef476d5ee4bcf6b1ef2e79de
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add mipi panel support for wormdingler
- Add the following panel for wormdingler:
INX P110ZZD-DF0
BOE TV110C9M-LL0
- Use panel_id to distinguish which mipi panel to use.
- Setup panel orientation
BUG=b:195898400,b:198548221
BRANCH=none
TEST=emerge-strongbad coreboot
Change-Id: I8cd28e024ecbfdcd473bc39efb529eb4aca1b5d0
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
2. Hynix H54G46CYRBX267
BUG=b:199032134
TEST=emerge-dedede coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: If8b75f9ed4d789d6c9c4365c517358df8d6e55c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Configure I2C high / low time in the device tree to ensure I2C
CLK runs accurately between 380 kHz and 400 kHz.
Measured I2C frequency just as below after tuning:
touchpad:390kHz
codec:395.8kHz
BUG=b:199481261
BRANCH=dedede
TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz
Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Ifadc3d19eb57fe6f67504be154c30df7bc0fee71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
All variants originally had been changed to start with an arrow with
two spaces following it to line up with the platform name. A number
of recent platforms were added only using a single space. This change
updates them all to have two spaces so they line up again.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iab9e6207fff5a7d2f6d76e5ca33eeaca721a224f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
