Commit Graph

34414 Commits

Author SHA1 Message Date
Angel Pons d615230cce treewide: Replace BOARD_EMULATION_QEMU_X86
It is equivalent to the CPU_QEMU_X86 symbol.

Change-Id: Ic16233e3d80bab62cc97fd075bdcca1780a6a2b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-03 10:16:09 +00:00
Angel Pons 632e241468 mb/emulation/Kconfig: Redefine BOARD_EMULATION_QEMU_X86
Use CPU_QEMU_X86 as it is selected by both Qemu x86 mainboards.

Change-Id: I8d6bfbddeeb8f2c66c5ea7728a9919e7cda86e7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-03 10:15:35 +00:00
Angel Pons 7671bce33b mb/*/Kconfig: Factor out MAINBOARD_VENDOR
Only some mainboard vendors have a prompt for this option. Let's be fair
and give this ability to everyone.

Change-Id: I03eec7c13d18b42e3c56fb1a43dc665d5dbd1145
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-03 10:15:22 +00:00
Angel Pons 3e576739c9 mb/Kconfig: Align ROM size options
Change-Id: I0160e72a8961f1aa34982f6348825708e7be9c40
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-03 10:13:31 +00:00
Marcello Sylvester Bauer dc1596c8c8 util/ifdtool: add --output flag
Add an optional commandline flag to define the filename of the resulting
output file. If this flag is not defined, it will behave like before by
using the old filename with a ".new" suffix.

With this additional flag it is not necessary to move the output file at
build-time, and the stdout print "Writing new image to <filename>" makes
more sense in the build context.

Change-Id: I824e94e93749f55c3576e4ee2f7804d855fefed2
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-03 10:12:52 +00:00
Matt DeVillier 3a7a3390f5 soc/broadwell: hook up smmstore
Adapted from implementation in sb/intel/common.

Test: build/boot variants of google/{jecht, auron}
with Tianocore and SMMSTORE enabled

Change-Id: I4d2aaa80dad229a6c7b947d0edf8fb1174050ad0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-03 10:12:02 +00:00
Matt DeVillier aa3b5e29f2 soc/braswell: hook up smmstore
Adapted from implementation in sb/intel/common.

Test: build/boot variants of google/cyan with Tianocore
and SMMSTORE enabled

Change-Id: Ife4681983d0eecbc01c539b477664f3dd8bb9368
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-03 10:11:55 +00:00
Matt DeVillier bd6bdc5c1d soc/baytrail: hook up smmstore
Adapted from implementation in sb/intel/common.

Test: build/boot variants of google/rambi with Tianocore
and SMMSTORE enabled

Change-Id: Id8adeda982feba1cbcf5e04cf0bef0a6710ad4f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-03 10:11:42 +00:00
Angel Pons 73704533d6 LGA1155 mainboards: Remove gfx.did and gfx.ndid
They are downright useless and result in ACPI errors. So, burn them.
Also, do a minor update to autoport's README about these values.

Change-Id: Idb5832cfd2e3043b8d70e13cbbe8bd94ad613120
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-03 10:11:02 +00:00
Ronak Kanabar 1c2313d339 soc/intel/tigerlake: Add Jasper lake GPIO support
Add gpio definition for Jasper Lake gpio controller.

Also created a separate file for JSL and TGL gpio keeping common asl file.
gpio_soc_defs.h must pass correct information/macro values to asl file
for code to work.

GPIO controller includes 4 gpio community and 10 groups. Patch adds
definition for all gpio within community and groups

Updated IRQ mapping for all gpios

TEST=Check if jslrvp and tglrvp code is compiling

Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-03-03 10:09:26 +00:00
Angel Pons c052ba0ac1 payloads/ext/Makefile.inc: Fix SeaBIOS race condition
For a very long time, SeaBIOS sometimes failed to build when using
multiple threads. This known problem has been haunting everyone for a
very long time. Until now.

Unlike most other payloads, building SeaBIOS results in two files: the
SeaBIOS payload itself and SeaVGABIOS. Each file has its own target, and
there's a third target called "seabios", which has the same recipe as
the SeaBIOS file, which calls `payloads/external/SeaBIOS/Makefile` with
a bunch of arguments. In addition, SeaVGABIOS depends on "seabios".

When executing serially, if the file of either SeaBIOS or SeaVGABIOS is
needed, the SeaBIOS Makefile will be run. This will generate both files,
so it is not necessary to run the Makefile more than once.

However, when using multiple threads, it can happen that one thread
wants to make the SeaBIOS file, while another one wants to make the
SeaVGABIOS file, which depends on "seabios". This implies that both
threads will execute the SeaBIOS Makefile at about the same time, only
to collide when performing git operations. Since git uses a lock file
when updating the index, one of the threads will fail to acquire the
lock with an error, which will ultimately cause the build to fail.

Whenever this happened, manually aborting with Ctrl-C made the build
process fail again because of the same error. The only way to get past
this problem, other than using one thread, was to let the unfinished
jobs complete. The thread that acquired the lock on the SeaBIOS git
repository would finish building SeaBIOS, so that target would not need
to be remade. When restarting the build, only the target that failed is
rebuilt, so it does not collide with any other thread.

To address this issue, make the SeaVGABIOS file target depend directly
on the SeaBIOS file instead, and remove the duplicate "seabios" target.

Change-Id: I251190d3bb27052ff474f3cd1a45022dab6fac31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-03 07:47:31 +00:00
Arthur Heymans 8e9801380b Kconfig: Have GDB_STUB depend on DRIVERS_UART
There is no reason to hide the GDB_STUB option when CONSOLE_SERIAL is
not set.

Change-Id: Icbf9a1ac0e617939cafa3d66774bbd467dc01cbc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-03 07:45:23 +00:00
Keith Hui 2f3c37bd62 i82371eb: Roll 82093aa init into isa_init()
This allows reuse of dev and reg32 already available,
and converting the block from #if to simple if.

Change-Id: I7a56f5a170986bbdf3c0c87eb5ead838ad55c659
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-03 07:43:08 +00:00
Keith Hui 2b9004de60 i82371eb: Drop support for older PIIX chips
All boards using this code use i82371eb (that shares PCI ID with i82371ab).
Dropping the code lightens compressed ramstage by a few dozen bytes.

Change-Id: Iab1e83b8f5fff44a33619c7925e5448169a2a87c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38598
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-03 07:42:48 +00:00
Arthur Heymans 3fa3bf97e5 cpu/intel/slot_1: Cache romstage XIP execution
Change-Id: I19fc31a0fe71c5d0c6845a8680e267a0bf5f1a8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37164
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Keith Hui <buurin@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-03 07:41:40 +00:00
Meera Ravindranath 872fced41d mb/google/dedede: Add memory initialization support for dedede
Update memory parameters based on memory type supported by dedede
1. Update dq/dqs mappings
2. Update spd data for Micron Memory
3. Add SPD data binary files for supported memory types
4. Update other FSPM UPDs as part of memory initialization

BUG=none
BRANCH=none
TEST=Build dedede, flash and boot to kernel.

Change-Id: I7248861efd1ecd5a0df0e17d39a44c168cab200e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39136
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-03 07:41:12 +00:00
Keith Hui ce62238998 sb/intel/i82371eb: Support reconfiguring GPO22/23
XOE# and XDIR# can be used as GPOs 23/22 if X-Bus functionality is not
required. Turns out asus/p2b-ls is using them to control termination
for the onboard SCSI buses. Add support to allow this reconfiguration.

Change-Id: I2dab6fafbd67a98ed1cac1ffcf9352be4a87c3e9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-03 07:36:53 +00:00
Keith Hui 7af59f709a sb/intel/i82371eb: Enable upper NVRAM bank
Change-Id: I9ad127ca4394e27fc055ddf03012a195cb03bd94
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-03 07:35:13 +00:00
Meera Ravindranath eaba79cc66 src/soc/tigerlake: Add memory configuration support for Jasper Lake
BUG=none
BRANCH=none
TEST=Build and verify boot of WaddleDoo.

Change-Id: I8de502d3f05d52b9dae34e3b013c6d5b1896fa85
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-03-03 04:07:39 +00:00
Wonkyu Kim 528ae9e811 soc/tigerlake: Correct FSP log interface
Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART.
DEBUG_INTERFACE_UART: Legacy UART
DEBUG_INTERFACE_SERIAL_IO: PCH UART

BUG=None
BRANCH=None
TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39167
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02 23:43:12 +00:00
Felix Singer 23f870ad3a soc/intel/denverton/uart.c: Clean up code
Since there is only one device ID used for UART,
an array is not needed. Therefore, just save the
device ID to the device variable.

Change-Id: Icd325e1102a85cc175f6025519a47a1b64ee5b46
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-02 19:13:39 +00:00
Felix Singer dbc90df35d soc/intel/denverton: Move PCI IDs to pci_ids.h
This patch moves the PCI ID definitions to pci_ids.h file
and replaces every occurrence with the new names.

The resulting binary doesn't differ from the one
without this patch.

Used documents:
- Intel 337018

Change-Id: Ib7d2aae78c8877f3c9287d03b20a5620db293445
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-03-02 19:13:10 +00:00
Marshall Dawson c4a8c48b2f util/amdfwtool: Clarify APOB NV requirements
Relocate the first size check.  This was automatically continuing
and not looking for the caller incorrectly passing a destination.

New information indicates that the APOB_NV should always be present
in the system.  Augment the missing size check to inferring whether
a missing size is valid, as in the case of older products, or truly
missing when it's needed.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I51f5333de4392dec1478bd84563c053a508b9e9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-03-02 16:35:51 +00:00
Marshall Dawson 4062b6a3b1 soc/amd/picasso: Add PCI ID for Dali xHCI
soc//picasso is intended to be forward-compatible with the Dali APU, a
Family 17h Models 20h-2Fh product.  Add the one new device ID it has.
See PPR document #55772 (still NDA only) for more information.

Change-Id: I7e9b90bb00ae6f4a121f10b1467d2ca398ac860c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-03-02 16:33:07 +00:00
Paul Menzel c105d9ab3f x86/acpi_s3: Remove trailing dots from debug message
The dot is not needed, as it is no sentence and followed by a line
break.

Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30806
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02 15:08:52 +00:00
Elyes HAOUAS 10615996cc lint/lint-extended-007-checkpatch: Fix obsolete paths
Change-Id: I7a6ca083e79d285b8c596631f21ccdfe2777e20e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-02 15:05:38 +00:00
Elyes HAOUAS b61a4da5ec lint/check_lint_tests: Fix obsolete paths
Change-Id: Ieac6e5ba0d425f873c3d4125d828224313017b69
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-02 15:05:32 +00:00
Alex Rebert 70282aece0 lz4: Fix out-of-bounds reads
Fix two out-of-bounds reads in lz4 decompression:

1) LZ4_decompress_generic could read one byte past the input buffer when
decoding variable length literals due to a missing bounds check. This
issue was resolved in libpayload, commonlib and cbfstool

2) ulz4fn could read up to 4 bytes past the input buffer when reading a
lz4_block_header due to a missing bounds check. This issue was resolved
in libpayload and commonlib.

Change-Id: I5afdf7e1d43ecdb06c7b288be46813c1017569fc
Signed-off-by: Alex Rebert <alexandre.rebert@gmail.com>
Found-by: Mayhem
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-02 15:03:03 +00:00
Alex Rebert e5e24107f9 libpayload: cbfs: fix infinite loop in cbfs_get_{handle,attr}
cbfs_get_handle() and cbfs_get_attr() are both looping over elements to
find a particular one. Each element header contains the element's
length, which is used to compute the next element's offset. Invalid or
corrupted CBFS files could lead to infinite loops where the offset would
remain constant across iterations, due to 0-length elements or integer
overflows in the computation of the next offset.

This patch makes both functions more robust by adding a check that
ensure offsets are strictly monotonic. Instead of infinite looping, the
functions are now printing an ERROR and returning a NULL value.

Change-Id: I440e82fa969b8c2aacc5800e7e26450c3b97c74a
Signed-off-by: Alex Rebert <alexandre.rebert@gmail.com>
Found-by: Mayhem
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-02 15:00:24 +00:00
Seunghwan Kim 56a0c2579d mb/google/kohaku: Add LPDDR 16G 2133 support
BUG=b:149775711
BRANCH=firmware-hatch-12672.B
TEST=emerge-hatch coreboot

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I856d7b361e70b657966cd4036c79f2fedfabb766
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39126
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02 11:53:06 +00:00
Angel Pons cfe1016883 mb/**/dsdt.asl: Remove outdated sleepstates.asl comment
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.

This follows commit 408d1dac9e.

Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-02 11:51:23 +00:00
Angel Pons 59e7a43f9a mb/**/dsdt.asl: Remove "Some generic macros" comment, again
It provides no useful information, so it might as well vanish.

This follows commit 0142d441c6.

Change-Id: Iad41d8d39c6712cebfa5245f37bc69061b5ac552
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-02 11:51:06 +00:00
Angel Pons cb06cfeca6 soc/intel/apollolake: Fix flashconsole, again
This time, it failed to build if measured boot was not enabled. Fix this
problem, and make sure flashconsole will not break like that again.

Change-Id: I5f5ffd14a3225804524cb0c1518e3d99737e0a93
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-02 11:49:50 +00:00
Patrick Rudolph 1ee3dbc63b nb/intel/sandybridge: Fix VBOOT
The VBOOT code can be compiled but it asserts with:
ASSERTION ERROR: file 'src/security/vboot/common.c', line 40

Start VBOOT in bootblock to fix the assertion.

Tested on Lenovo X220:
The assertion is gone, the platform boots again.

Change-Id: I48365e911b4f43aecba3b1f950178b7ceed5b2e9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-02 11:49:03 +00:00
Patrick Rudolph c8b0f31ca1 acpi: Bump FADT to revision 6
Some of the revision 4 FADT fields were already updated to ACPI
spec revision 6, but not all of them. In addition the advertised
FADT revision was 3.

Implement all fields as defined in version 6 and bump the advertised
FADT revision to 6.

Change-Id: I10c1e2517df41159ab9b04f763d3805ecba50ffa
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-02 11:48:11 +00:00
Paul Menzel d778b3bc90 drivers/i2c/at24rf08c: Format according to coding style
1.  Move opening bracket to line above
2.  Remove space after `printk` statements

Change-Id: Ia12a4ed6ab2fb2c9848a2688b41fcfa70ab001b0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-02 11:46:29 +00:00
Paul Menzel 2a6140ea85 drivers/i2c/at24rf08c: Correctly format short multi-line comments
Change-Id: I84e09706aceae69671ce429d77e7874128468307
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-02 11:46:24 +00:00
Jonathan Zhang 9ab4dc32b4 vendorcode/intel/fsp/fsp2_0: Add FSP header files for Skylake-SP
Add header files for FSP of Skylake Scalable Processor.

These header files are from an Intel SKX-SP FSP engineering build.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: johnny_lin@wiwynn.com
Change-Id: If47f102c2c7979da1196f8c6b315d5be558e786c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
2020-03-02 11:44:47 +00:00
Tommie a1d7db8215 mb/google/octopus: support new Elan touch panel for Foob
This is new elan touch screen IC, which includes touch panel and USI pen.

BUG=b:149800883
BRANCH=octopus
TEST=build bios and verify touch screen works fine

Signed-off-by: Tommie Lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: Ibec3d08cc740e398a10a5c845181318724afc70a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
2020-03-02 11:43:05 +00:00
Rajat Jain c0380a24e8 mb/google/hatch/var/jinlon: Disable EPS on some SKUs
Disable EPS on the SKUs that do not have it.

Change-Id: I7305097beea3484634933ab856fd084933868a10
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2020-03-02 11:42:26 +00:00
Rajat Jain 68cd0d0b2c mb/google/hatch/var/jinlon: Enable gfx/generic driver
Enable the GFX device for Jinlon.

Change-Id: I6ba90bf464e315ec364b6f35e7670924a2aba25a
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2020-03-02 11:42:16 +00:00
Rajat Jain 7ef06b0234 drivers/gfx/generic: Add support for gpio based EPS
Add support to control EPS via a PCH gpio

Change-Id: I6f570fd43e1649fb23255b0890e01086e34f844a
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2020-03-02 11:42:06 +00:00
Rajat Jain 310623b2dd arch/x86/acpigen: Add new helper routines for XOR and get_rx_gpio
Add new helper function in the acpigen library, that use the underlying
soc routines.

Change-Id: I8d65699d3c806007a50adcb51c5d84567ce451b7
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2020-03-02 11:40:23 +00:00
Patrick Rudolph 4d9dd22bd1 Documentation: Add Heads to payloads
Add a small description about Heads.

Change-Id: I2e768a640751fee1b1b5df4401205e24cde0607c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-02 11:39:16 +00:00
Patrick Rudolph 0751d7bded Documentation: Add tutorial for me_cleaner on Lenovo devices
Add a tutorial how to use ME cleaner, and give some basic steps to
strip the ME. Update the Lenovo Sandy Bridge documentation that no
issues could be observed on X220 and give an example flash layout.

Tested on Lenovo X220 with stripped ME and found no issues:
commit: cbc5b99ac9

* Displayport
* VGA
* USB
* Bluetooth
* Wifi
* Wifi-kill switch
* libgfxinit
* SATA
* Audio
* SD-card
* Ethernet
* Keyboard
* Fn-Keys
* Display brightness
* ACPI S3 resume
* Battery events
* CPU temperature reporting
* FAN managment
* Stress test stable
  * Youtube videos over Wifi
  * stress -c 2 -m 1 -d 1
  * glxgears

Change-Id: I0b1d04f00b5dbb38cf04333f2b345749b740a375
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39129
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02 11:39:05 +00:00
Sridhar Siricilla 24a974a8cb soc/intel/{common, skl, cnl, apl}: Move print_me_fw_version() to CSE lib
Move print_me_fw_version(), remove print_me_version/dump_me_version from
cnl/skl/apl and make changes to call print_me_version() which is defined
in the CSE lib.

TEST=Verified on hatch, soraka and bobba.

Change-Id: I7567fac100b14dc207b7fc6060e7a064fb05caf6
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-03-02 11:38:18 +00:00
Sridhar Siricilla c2a2d2ba26 soc/intel/common: Remove HOST_RESET_ONLY reset type support
Remove HOST_RESET_ONLY reset type of GLOBAL_RESET HECI command as it
is not supported.

Change-Id: I17171e1e5fe79710142369499d3d904a5ba98636
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-02 11:37:56 +00:00
Usha P aaf28d2507 soc/intel/apollolake: Display platform information
This patch includes the change required to display Apollo Lake platform
information which reports CPU, MCH, PCH and IGD information in romstage.

BUG=None
TEST=
1. Boot to OS on Bobba board.
2. Verified below info from CPU Console log in romstage
CPU: Intel(R) Celeron(R) N4000 CPU @ 1.10GHz
CPU: ID 706a1, Geminilake B0, ucode: 00000031
CPU: AES supported, TXT NOT supported, VT supported
MCH: device id 31f0 (rev 03) is Geminilake
PCH: device id 3197 (rev 03) is Geminilake
IGD: device id 3185 (rev 03) is Geminilake EU12

Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38824
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02 11:37:13 +00:00
Patrick Rudolph 792fd51b14 mb/emulation/qemu-aarch64: Add ARM trusted firmware support
Linux expects a working PSCI and hangs if not found.
Add BL31 into CBFS as '-M virt,secure=on -bios ' commands line arguments cause
qemu's internal PSCI emulation to shutdown.
BL31 is placed in qemu's SECURERAM memory region and won't conflict with
resources in DRAM.

Tested on qemu-system-aarch64:
Fixes a hang and allows to boot into Linux 5.4.14 userspace.

Change-Id: I809742522240185431621cc4fd8b9c7deaf2bb54
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-02 10:36:37 +00:00
Patrick Rudolph 977b8e83cb mb/emulation/qemu-aarch64: Add MMU support
Enable MMU in bootblock. Makes qemu look more similar to real hardware.
There's no real need to activate the MMU.

Tested on qemu-system-aarch64: 5 page entries are used out of 32.

Change-Id: Ifaed9d3cc11520f180a732d51adce634621b5844
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38534
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02 10:33:38 +00:00