The ADAU7002 is a family of Stereo PDM-to-I2S/TDM conversion ICs from
Analog Devices. On some boards they are a used to convert a PDM audio
data stream from a DMIC to an I2S signal.
Add a driver for populating ACPI table entries for this part.
BUG=b:72121803
TEST=With grunt audio kernel patches, "aplay -l" shows playback devices:
**** List of PLAYBACK Hardware Devices ****
card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 []
Subdevices: 1/1
Subdevice #0: subdevice #0
Change-Id: I2b64c8e1cbc0a68984482a7d496f8c4498cb6cbe
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23659
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Martin Roth <martinroth@google.com>
When running 'make distclean' on coreboot, the build cleans the tools
as well. Since secimage didn't have a distclean target, it gave an error
that the distclean target didn't exist. This didn't actually affect
anything more than the secimage clean, but it was impossible to tell
that from the warning:
% make distclean
make[1]: *** No rule to make target 'distclean'. Stop.
Change-Id: I4b4bcc1ab48e767218d31e455d23527acedf4953
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
For system without secondary battery, current DSDT will report warning
during build time. Add a conditional check to make sure only battery
index 0 can return success.
TEST=Build pass.
Change-Id: Iae12c5d1aa749948ef4025c8b5e60c97e1b747a5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23661
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As per FSP 2.0 specification and FSP SOC integration guide, its not expected
that SMBIOS Memory Information GUID will be same for all platform. Hence
fsp_find_smbios_memory_info() function inside common/driver code is not
generic one.
Removing this function and making use of fsp_find_extension_hob_by_guid()
to find SMBIOS Memory Info GUID from platform code as needed.
Change-Id: Ifd5abcd3e0733cedf61fa3dda7230cf3da6b14ce
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add option to have customized DLL setting for EMMC interface to make
EMMC able to run at HS400 speed.
BUG=None
Change-Id: I38bc022d8c05dd1fbd03dc26aa6f33cd249e8248
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for KBL RVP8 board
* Add KBL RVP8 support in Konfig.
* Add KBL RVP8 config option in make menuconfig.
* Add descriptor and ME binary paths for RVP8 in Kconfig.
* Add RVP8 board name Kconfig.name.
* Add devicetree.cb for RVP8 in the variants path.
* Add gpio.h for RVP8 in variants/include/variant path.
TEST= Build and boot RVP8.
Change-Id: I6ba177c223f6aa3285c0fe5eba0cd55b2a50c4ed
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/23383
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch ensures to have Type 17 SMBIOS table for CannonLake Platform.
TEST=Enable to get correct SMBIOS DIMM type information as per
SMBIOS spec 3.1
Change-Id: I611f9f3fc0e07f026610b7a61bc3599523e4f262
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Pmax is calcuated from MAX(Psku1, Psku2), where Psku1, Psku2 are
estimated Pmax power of U42 and U22 skus. For U42 sku, the Pmax is PL4
(71W) + ROPmax (49W) = 120W; for U22 SKU, the Pmax is PL4 (43W) +
ROPmax (49W) = 92W. So Pmax is set to MAX(120W, 92W) = 120W.
BUG=b:71594855
BRANCH=None
TEST=Make sure correct pmax value is being passed into fsp
Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23633
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
CMOS layout is not used and can be removed. A change to Kconfig is needed in
order not to break the build.
BUG=b:64207749
TEST=Build gardenia.
Change-Id: I24a71490777b101b069175460f3715ec3ff78240
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We share the same shared memory fields for both batteries. When
the host wants to switch battery to read out, it will:
- Set BTID (EC_ACPI_MEM_BATTERY_INDEX) to the required index
- Wait for BITX (EC_MEMMAP_BATT_INDEX) to have the required value
- Then fetch the data
BRANCH=none
BUG=b:65697620
TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are
present, data is valid.
Change-Id: Ib06176e6ab4c45a899259f0917e6292121865ed6
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/23598
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Improve the file with:
* C99 inializations for structures
* reorder include files for aesthetics
* remove extraneous whitespace
* remove a stale comment
* make variable naming consistent
* make function arguments consistent
This change clears up all remaining checkpatch issues with the wrapper
with the exception of errors created with AMD definitions, e.g.
ERROR: need consistent spacing around '*' (ctx:WxV)
#32: FILE: src/soc/amd/common/block/pi/agesawrapper.c:32:
void __attribute__((weak)) SetFchMidParams(FCH_INTERFACE *params) {}
BUG=b:62240746
TEST=Build and boot Kahlee
Change-Id: I40985e0cf50df6aa4d830937e7f6b6e7908f72fe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a function to allow an external region to be located in TSEG.
Select the option to use memory outside of cbmem. Increase the size
reserved in TSEG.
Change-Id: Ic1073af04475d862753136c9e14e2b2dde31fe66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Leverage the stage_cache mechanism to store a non-specific type
of data. This is not interesting when the location for the cache
is in cbmem. However it will be more useful when an external
location is used, e.g. when the cache is in TSEG, locked from user
modification.
Change-Id: Iaf0b25ebe14c176bbd24fc8942f902f627ca8e6f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch ensures soc/sata.c correctly translates pci config offset 0x92
Bit 0-2 [SATA Port x Present (SPDx)]
0 = Port x is enabled.
1 = Port x is disabled.
Change-Id: Ide093dafe33b947ba7845cc0b74a975471353e39
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
SATA PCH configuration space registers bit mapping is different
for various SOCs hence common API between SPT-PCH and CNL-PCH causing
issue.
Add new Kconfig option to address this delta between different PCH.
Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23589
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to
match the latest schematic changes).
Since WiFi was the only device using WAKE# pin, DSX_EN_WAKE_PIN is
removed from deep_sx_config as well.
BUG=b:72697650
TEST=Verified:
1. Wake-on-wifi works.
2. Device is able to enter G3 without WAKE# pin causing unwanted wakes
from deep S5.
Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23594
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In TPM 2.0 case, if the factory initialization is interrupted after
defining, say, the kernel tpm nvram space but before writing to this
space, the following will happen upon reboot when the factory
initialization will be re-attempted. Writing to this space will be
skipped, and coreboot will finish the factory initialization with
this space remained unwritten. At a later stage, when the rollback
logic will attempt to check the version in the kernel space, it will
fail (TPM2.0 returns an error when reading from unwritten spaces),
and the system will go into recovery with no way out (since the
kernel space will never be written).
This change fixes that by always writing to the kernel, MRC hash and
firmware spaces during factory initialization, even if the space
already existed by that time.
BUG=b:71884828
TEST=delete, define, but not write to the kernel space; trigger
factory initialization; coreboot should fill the kernel
space and continue booting.
Change-Id: I48d8bb4f9fc0e5276e6ec81247b3b6768ec9fa3b
Signed-off-by: Andrey Pronin <apronin@google.com>
Reviewed-on: https://review.coreboot.org/23456
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This patch stores the correct capabilities for EMMC media which in turn
sets the correct timing data for HS400 mode.
Without this code change, EMMC CMD13 is failing at the end of HS400 mode
switching.
BUG=none
BRANCH=none
TEST=Build and boot Soraka
Change-Id: I3f00c9eace7cc136d86a1e07f040fbfc09e0e02e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23541
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch changes the sequence of post_cpus_init() function of mp_init
to very last of the stages, i.e., ON_EXIT of BS_WRITE_TABLES for normal
boot path, and to ON_ENTRY of BS_OS_RESUME for S3 Resume path.
Also, the fast_spi_cache_bios_region() call inside post_cpus_init()
function is left out, since caching the SPI Bios region is not required
now at this stage.
BUG=none
BRANCH=none
TEST=Build and boot in Soraka (KBL), executed stability tests on multiple
systems.
Change-Id: I97c4a4096a3529a21bae6f2cf5aac654523a5b22
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/23540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
'Optimizing' MMCONF_BASE_ADDRESS for the native codepath prevents the
use of fallback/normal with both the native raminit and the mrc.bin.
Using the same MMCONF_BASE_ADDRESS as the mrc.bin codepath means that
128MB less is available to devices using the native raminit. Most
devices reserve 2048M for non memory resources below 4G, which in most
cases is more than adequate. Devices with only 1024M (and that don't
already use the mrc.bin) are:
* lenovo/x220
* lenovo/x230
* lenovo/x131e
* lenovo/x1_carbon_gen1
Those could fail to allocate PCI resources, but on at least x220 with
a somewhat default configuration (USB3 expresscard, Wireless PCIe
card) it still boots fine, so one should not expect many problems from
this change.
Change-Id: I1d0648fe36c88bd9279ac19e5c710055327599fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With the new extra detachable UI elements, we're running out of space in
Scarlet's RO CBFS. Thankfully, the GBB is still massively
overdimensioned, so we can steal another half MB from there.
This patch changes the FMAP for some boards that have already had
production firmware releases. However, all the new changes are to the RO
parts of the FMAP, so there shouldn't be a way this could cause a
problem for updates.
Change-Id: Iec182de3e894e56fec2a64b034c0ca65d78a5522
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
One of responsibilities of the `secimage` tool is signing the image
using the HMAC-SHA256 algorithm. The test being added verifies that
secimage's internal call yields same result as the according openssl
tool does.
Change-Id: I8de4328f435af56901a861e3d5e733657c3c7f78
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This driver uses an fmap region for the MRC cache instead of a CBFS
file which makes it easier to manage if one wants to write protect
it.
Change-Id: Iaa6b9f87c752088d70882fd05cb792e61a091391
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The registers were taken from the wrong addess since the spibar offset
was not added to it.
This also fixes the endianness.
Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23478
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I2C bus rise/fall times were measured as follows. Signals were generated
with:
- bus 0: manual i2c driver in depthcharge
- bus 2,3: i2cdetect -r <bus_number>
and then measured manually with an oscilloscope.
BUG=b:72442912
Change-Id: I291e144249271ec34a93417398e54e68b8e21e23
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
PARALLEL_CPU_INIT pertains to initialize_cpus() in
src/cpu/x86/lapic/lapic_cpu_init.c
which haswell does not use as it uses PARALLEL_MP init.
Change-Id: I46b6f72e8e372b8c8564243ece7aed3a9371c621
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CMOS layout is not used and can be removed. A change to Kconfig is needed in
order not to break the build.
BUG=b:64207749
TEST=Build kahlee.
Change-Id: Ib5d18e80a56111d96c730420db865194c71de1b3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
After adding NHLT and max98373 amp support, cnlrvp fails to boot
with error: out of memory (free_mem_ptr >= free_mem_end_ptr).
Increase HEAP_SIZE from 0x4000 to 0x8000.
BUG=None
TEST= emerge-cnlrvp coreboot nhlt-blobs chromeos-bootimage coreboot-private-files-cnlrvp
and verify cnlrvp boots to kernel.
Change-Id: Icb0f3c626b784d73e417e5722b3b4da29ab5acce
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add `cmos.default` to get rid of four seconds in romstage. Choose 8 MB
for size for video RAM.
Order the entries like in `cmos.layout`.
Change-Id: If2dcc266f6f061807401b62647124ce96e9a3802
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/23468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Enable HotPlug for the PCIe root port that the WiFi device
is on so the OS can re-train the link without needing a reboot
if it goes down unexpectedly at runtime.
BUG=b:72417777
TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in
linux that it is identified as a HotPlug capable root port.
Change-Id: Id2b7fc92c8c9128f0e28102eb5991bda7fbf6799
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23512
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a variable to fill out the FSP UPD variable for PCIe HotPlug,
which allows a mainboard to enable HotPlug on individual root ports.
BUG=b:72417777
TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in linux
that it is identified as a HotPlug capable root port.
Change-Id: I6b1f525e41909a3f81984806c4ef20239032c8d6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23511
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide a method for initializing i2c buses that are not marked as
early_init in the device tree. These i2c buses can be enabled in a
mainboard's ramstage, for example.
BUG=b:69407112
TEST=Boot depthcharge w/ CLI enabled on grunt.
devbeep
=> plays beep
BRANCH=None
Change-Id: I6e49b0de9116138ba102377d283e22d7b50d7dca
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
According to doc #543977 Power Architecture Guide, PsysPmax is the
maximum platform power. It maps to the full-scale of Psys signal.
This patch adds a "psys_pmax" member in chip information which allows
boards to set up maximum platform power.
BUG=b:71594855
BRANCH=None
TEST=Set "psys_pmax" in device tree & "USE=fw_debug emerge-fizz
chromeos-mrc coreboot chromeos-bootimage" & ensure correct
PsysPmax value is passed to FSP-S through UPD. Verfied on
KBL-R and KBL-U SKUs.
Change-Id: I44f2e2917a8eb9ce3bb69d9c15899d4c7c5b2883
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Pass in fizz-specific adapter-based PsysPl3 and Pl4 values to avoid
brownouts. According to Intel doc #560604, page 74, the max time
window is 64ms (code=6) and the min duty cycle we can set is 4%.
BUG=b:71594855
BRANCH=None
TEST=Boot to OS and check MSRs using iotools for expected values
Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Daniel Kurtz