<rules.h> and <commonlib/bsd/compiler.h> are always automatically
included in all compilation units by the build system
Change-Id: I9528c47f4b7cd22c5a56d6a59b3bfe53197cc4d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently coreboot and EC had different logic to interpret TCSS port
number which would break retimer update functionality since coreboot
would pass wrong port information to EC.
This change clones the implementation on Alder Lake which converts
the phyiscal port mapping to EC's abstract port mapping.
BUG=b:207057940
BRANCH=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: If4451598dbb83528ae6d88dbc1b65c206f24fe1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
TGL-LP only has 12 root ports, not 20. Correct the port map.
Change-Id: I3f5c69a2e7e3a2b8292c81beeac4ea6c7279d4b4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The factory versions (minor version 22) of cr50 FW have an issue with
producing short interrupt pulses, which can be missed by the ADL PCH
if autonomous GPIO power management is enabled, therefore instead of
continually adding the setting to all the variants, move it to the
baseboard instead.
Change-Id: I337f1e9e8f958c02bb73e6701a06c0b88a4757d7
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The existing common AMD SoC code supports some of AMD Family 17h Model
A0h SoC's PCI devices that however have different PCI IDs. Add the new
PCI ID defines to the PCI ID lists of the common PCI drivers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I50960e502c63a2ffcfed35178c5e7c9729ef061e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The PCI IDs of the ACP (audio co-processor), the non-GPU HDA audio, the
SMBus and the LPC devices haven't changed from the previous generations
of Zen-based APUs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I41e0a57671b9ef2938b7798d5826de43bea8fe12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add an elog type 0xb6 for Chrome OS diagnostics related events and
log the message while booting the diagnostic tool:
__func__: Logged diagnostic boot
BRANCH=none
BUG=b:185551931, b:177196147
TEST=emerge-volteer coreboot vboot_reference
Change-Id: Icb675fc431d4c45e4f432b2d12cac6dcfb2d5e3a
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
uintptr_t is defined in stdint.h which gets included by types.h. I use
types.h instead of stdint.h, since that's also what the Picasso code
does.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id3d0811d831b5acc9343398f4d28c73467c0a429
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Apollo Lake
and ensures disable_heci1() is guarded against this config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7ac0cad97fcd42b2c6386693319d863352356864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move the `configure_pmc_descriptor()` function to SoC scope instead of
having two identical copies in mainboard scope. Add a Kconfig option to
allow mainboards to decide whether to implement this workaround.
Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Copy the `is_descriptor_writeable()` function from the `intel/adlrvp`
mainboard and use it in the `configure_pmc_descriptor()` function. With
this change, this function is now identical for both mainboards.
Change-Id: I2ff39682ed98c6b8bc60cc2218f36f4934b9903c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
Adjust the cosmetics of the `configure_pmc_descriptor()` function to
match the code for the `intel/adlrvp` mainboard. The only difference
is that adlrvp checks if the descriptor is writable.
Tested with BUILD_TIMELESS=1, Google Brya0 remains identical.
Change-Id: I9c524d5c422c765db200a15f484c2b8827ebd40b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
Restructure the code in the `configure_pmc_descriptor()` so that it
matches the code for the `intel/adlrvp` mainboard. This change does
not reindent the contents of the original if-block intentionally as
this will be taken care of in a reproducible follow-up.
Change-Id: I8c9d9087cb2d0668f6a4afbb566d830bb9febd89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
More Brya variants like Brya0 and Taeko have migrated to use
Alder Lake QS SoC which enables eNEM feature by default. Hence,
select eNEM for CAR by default for these variants.
BUG=b:168820083
TEST=Able to build and boot brya0 variant using eNEM mode.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I63be166c8e428f052999fe29c8ebe1238e1a12ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch migrates common code API into SoC specific implementation
to drop CPU privilege level as the MSR is not consistent across
platforms.
For example: On APL/GLK, it's MSR 0x120 and CNL onwards it's MSR 0x151.
Also, include `soc/msr.h` in cpu.h to fix the compilation issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0b6f39509cc5457089cc15f28956833c36b567ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60898
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On x86_64 the struct isn't packed, causing the fw_cfg parser to return
invalid memory entries (possible others as well) through fw_cfg.
Fix that by packing all structs.
Change-Id: Id1bab99f06be99674efe219dda443fb7d44be560
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Instead of maintaining another set of byteswapping functions in
cbfstool, this change removes swab.h and replaces it with
bsd/sysincludes.h from commonlib. Callers have been updated to use
be32toh/be64toh/htobe32/htobe64 instead of ntohl/ntohll/htonl/htonll
respectively.
Change-Id: I54195865ab4042fcf83609fcf67ef8f33994d68e
Signed-off-by: Alex James <theracermaster@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch adds a config to let mainboard users choose the correct
state of HECI1(CSE) device prior to handing off to payload.
`DISABLE_HECI1_AT_PRE_BOOT` config to make HECI1 function disable
at pre-boot.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Elyes HAOUAS