Commit Graph

41404 Commits

Author SHA1 Message Date
Angel Pons 736a1028fb drivers/intel/fsp1_1: Drop dead MMA code
The only FSP 1.1 platform with MMA support is Skylake. As it now uses
Kaby Lake FSP 2.0, this code is no longer useful. Drop it.

Change-Id: I819c3152bdea0fdad629793d96136ef134429fbd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-06 06:46:41 +00:00
Kevin Chiu f0fd3e2269 mb/google/zork: update DRAM table for morphius
Add Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb
index was generated by gen_part_id

BUG=b:184024142
BRANCH=zork
TEST=emerge-zork coreboot

Change-Id: I890a2da38c8cd1963e9ee7c5df9410b2b2538e9f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-04-06 06:46:27 +00:00
Kevin Chiu e1da21f687 util: Add DDR4 generic SPD for Micron MT40A1G16RC-062E-B 16Gb
Add SPD support for Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb

BUG=b:184024142
TEST=none

Change-Id: I438310fb74d96953bc83374df3109e4c56192a5f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-04-06 06:46:18 +00:00
Frank Wu e440c6b238 mb/google/zork/var/vilboz: Update WiFi SAR for Vilboz/Vilboz360 LTE
Loading wifi_sar-vilboz-2.hex for vilboz LTE sku.
Loading wifi_sar-vilboz-3.hex for vilboz360 LTE sku.

BUG=b:183902165, b:176211194, b:183913210
BRANCH=firmware-zork-13434.B
TEST=Build coreboot and load the wifi sar table by fw_config

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I37a40456970e3f1dc8b2eed26aa23e3d75748222
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-06 03:24:13 +00:00
Julius Werner 8205ce6b34 fsp2_0: Replace fspld->get_destination() callback with CBFS allocator
The Intel FSP 2.0 driver contains a custom construct that basically
serves the same purpose as the new CBFS allocator concept: a callback
function to customize placement of a loaded CBFS file whose size is
initially unknown. This patch removes the existing implementation and
replaces it with a CBFS allocator.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0b7b446a0d2af87ec337fb80ad54f2d404e69668
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 22:59:09 +00:00
Julius Werner 4676ec52c2 cbfs: Make `mdata` argument to cbfs_allocator_t const
Right before CB:49334 was submitted, I changed the signature of
cbfs_allocator_t function pointers to include another argument passing
in the already loaded CBFS metadata (to allow for the rare edge case of
allocators needing to read CBFS attributes). This interface is not meant
to be able to modify the passed-in metadata, so to clarify that and
prevent potential errors, we should declare the argument const.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7e3756490b9ad7ded91268c61797cef36c4118ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 22:59:02 +00:00
Felix Held d9c02cdc98 vc/amd/fsp/picasso/platform_descriptors: fix typos in enum element names
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5cad6a6a585320b33bfab7b3950888241f7c179c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-05 19:49:02 +00:00
Karthikeyan Ramasubramanian 72c1deaa74 mb/google/guybrush/var/guybrush: Add Codec and Speaker configration
Enable I2C2 in devicetree and fill ACPI information for Codec and
Speaker amplifiers. Pass correct IRQ GPIO for headset jack.

BUG=None
BRANCH=None
TEST=Ensure that the Codec and Speaker Amplifiers are detected in
i2cdetect.

Change-Id: I1ae52a8bbaa0181c906cd14a94de22e0250ed4c1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52046
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 19:47:24 +00:00
Karthikeyan Ramasubramanian d84ce40f7d mb/google/guybrush: Add Bluetooth configuration
Configure the BT disable GPIO to logic low in order to enable Bluetooth.
Add USB ACPI configuration for BT device.

BUG=b:182201890
TEST=Build and boot to OS.

Change-Id: I647c301e2db6d4a7c5c8cb31cbc47a44cba5e734
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 19:47:15 +00:00
Raul E Rangel 92e66cc4e3 soc/amd/cezanne: Add soc/msr.h
This is a copy of picasso.

BUG=b:184151560
TEST=Compared with the cezanne PPR.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia4bc40daa971c126c2596837155312d411b91a06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-05 19:25:26 +00:00
Ivy Jian 7a347afa95 mb/google/guybrush: Enable camera power GPIO
Configure camera power GPIO to high

BUG=b:182207799
TEST=Build and boot to OS then checked camera device existence with lsusb

Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-05 18:30:46 +00:00
Martin Roth 632419852a mb/google/guybrush: Update GPIO configuration
Initialize all eSPI signals including PCIE_RST0_L early for EC
communication.
- Set PCIE_RST0_L to a GPIO and set it high to release the bus.  This is
a temporary workaround until PCIE_RST_L comes up on its own.
- Make sure all GPIO muxes initialized early are re-initialized.

BUG=b:183340503
TEST=Boot Guybrush

Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51675
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 18:24:44 +00:00
Martin Roth d07f724f9c soc/amd/common: Add some ESPI register definitions
Use definitions instead of magic numbers
clean up some whitespace while I'm here.

BUG=b:183207262
TEST=Build

Change-Id: Ieae53b12e5303641fb3f180c47468aaa6906e9af
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-05 17:34:18 +00:00
Martin Roth fa9eb951d4 util/bincfg: Clean up Makefile
- Enable warnings
- Enable warnings as errors
- Remove debug flag -g
- Add targets for all, distclean, and help
- Add dependency of the bincfg file for output targets
- Add all phony targets to .PHONY

BUG=None
TEST=Build all targets

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ic0302f663cbc931325334d0cce93d3b0bf937cc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50654
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 17:21:04 +00:00
Eric Lai 7bbcdc2f20 mb/google/mancomb: Add ACPI support for Chrome EC
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ibce15d2e4340515353a33c593d065df50a15286a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05 16:41:14 +00:00
Eric Lai e93e693173 mb/google/mancomb: Enable eSPI VW SCI events
Mancomb does not have a dedicated SCI pin so it uses VW.

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id315ab448209d9c93494f7689361e45f8a6ed001
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05 16:41:02 +00:00
Eric Lai 6b928356ca mb/google/mancomb: Enable Chrome EC SKUID and BOARDID
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I70283c8d93b5cbabdaf5a8ab947d5f8444940dff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05 16:40:48 +00:00
Eric Lai 1954c1f92e mb/google/mancomb: Add smihandler
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I52411917d9e7e8f8d9ac5d1c9b426a58ba09f5ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05 16:40:37 +00:00
Eric Lai 87e27e1d0e mb/google/mancomb: Enable Chrome EC
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id1617be67bfc5d2f142358ae8a70c3e575a94c6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05 16:40:08 +00:00
Raul E Rangel b95f848766 soc/amd: Make espi_clear_decodes private
espi_setup already clears most of the controller registers. So this
change consolidates the clear logic into one spot.

This shouldn't result in a behavior change on Picasso. Picasso already
has the eSPI decodes clear on boot, so this change is a nop.

BUG=b:183524609
TEST=Boot guybrush to the OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 16:39:11 +00:00
Raul E Rangel 61ac1bc530 soc/amd: Make espi_configure_decodes private
This is only ever called after espi_setup.

55861 - AMD System Peripheral Bus Overview also says that io ranges
should be configured before enabling the BUS_MASTER bit.

BUG=b:183524609
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 16:38:23 +00:00
Seunghwan Kim c988d0516c mb/google/dedede/var/sasuke: Update DPTF parameters
Remove TSR2, use DPTF parameters from internal thermal team.

BUG=b:183749595
BRANCH=dedede
TEST=emerge-dedede coreboot

Change-Id: I3182b96bf36c8d07299fe435a29e6b8c0b8a6927
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-05 15:37:42 +00:00
Seunghwan Kim 6ffaf5a691 mb/google/dedede/var/sasuke: Configure I2C times for touchpad/audio
Configure I2C rise/fall time in device tree to ensure I2C CLK runs
accurately at I2C_SPEED_FAST (< 400 kHz).

Measured I2C frequency just as below after tuning:
I2C0(touchpad): 385 kHz
I2C4(audio): 380 kHz

BUG=b:180335053
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400kHz

Change-Id: Ic92ee0379456e80260a8026bc38ee41325dad6d2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-05 15:32:09 +00:00
Raul E Rangel 66c52ffb2b soc/amd/common/espi: Clear DNCMD_COMPLETE on completion
Tidy up the interrupt status. This will leave SLAVE0_INT_STS = 0.

BUG=b:183524609
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I950cfb81521e35758c120a482670cfdb924201d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52056
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 15:02:10 +00:00
Raul E Rangel b92383a8a5 soc/amd/common/espi: Reset eSPI registers to known state
This sets the eSPI registers to the reset values specified in the PPR.

On Cezanne, the PSP modifies these registers such that the eSPI
peripheral cannot send DEFER packets. This causes random bus errors.

These reset values are identical to what is currently used on Zork.

I didn't clear out ESPI_DECODE because it's currently being done by
cb:51749.

BUG=b:183524609
TEST=Boot guybrush to the OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 15:02:00 +00:00
Raul E Rangel 1d0e4930ba soc/amd/common/espi: Add missing eSPI register definitions
These are defined in the public Picasso PPR - 55570-B1 Rev 3.15.

BUG=b:183524609
TEST=Build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e601f767327e0a24a086146623af039388b2e7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 15:01:50 +00:00
Aaron Durbin a435c3e2ea mb/google/dedede: add lalala variant
The Lalala variant is a design that differs only
in replacing Cr50 with a discrete TPM part.

BUG=b:184151664

Change-Id: I2f7abb9637cd5a13ac896396781b19feb156c948
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
2021-04-05 14:31:15 +00:00
Aaron Durbin 7164ad74bf mb/google/dedede: add discrete TPM 2.0 configuration
There are forthcoming designs that will be utilizing
a discrete TPM 2.0 solution. Split the existing dedede
configuration options so future mainboard variants can
easily select the appropriate Kconfig option using the
newly introduced options:
- BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
- BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
The existing variants all select the former option,
BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 since all those
designs currently utilize Cr50.

BUG=b:184151664

Change-Id: I2bdb1ca4fd78cc0628256d49678ea042c55f6fba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52030
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 14:31:08 +00:00
Furquan Shaikh f7f715dff3 mb/google/brya: Enable south XHCI ports 1 and 2
FSP v2081 has a bug where it uses the information about south XHCI
ports to enable TCSS XHCI ports. This change works around this bug by
enabling south XHCI ports 1 and 2 in brya baseboard devicetree. brya0
already enables south XHCI port 1 in overridetree.cb, however, it is
still enabled in baseboard/devicetree in case more variants are added
to brya before FSP is fixed.

BUG=b:184324979
TEST=Verified that TCSS XHCI ports 1 and 2 are now enabled.

Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-05 14:15:31 +00:00
Angel Pons 5304ce108e nb/intel/sandybridge: Drop `pci_mmio_size`
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.

Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:16:43 +00:00
Angel Pons f2e8660fa2 sandybridge boards: Drop default `pci_mmio_size`
2 GiB is the default already.

Change-Id: I294460949659c97d4e19ad4e9d14f8c3566cca3f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52071
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:16:36 +00:00
Angel Pons e24f97c081 nb/intel/ironlake: Drop `pci_mmio_size`
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.

Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:16:22 +00:00
Angel Pons 83e319d6f5 device/dram/ddr3: Drop unused MRS helpers
These aren't used anywhere anymore.

Change-Id: I4cf2fc0d07a772886e90fba4f66591a7b0a40e6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05 13:03:58 +00:00
Angel Pons ae5e636b96 nb/intel/sandybridge: Rename `pdwm_mode` enum
The `pdwm` part was supposed to be an abbreviation of `power down`, but
it is neither self-explanatory nor properly-spelled. Rename the enum.

Change-Id: I7b83c71d4534b62e18ced04eebe6a65089e1d874
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05 13:03:24 +00:00
Angel Pons 623d75e828 spd.h: Remove unused definitions
These definitions are unused and not particularly useful. Drop them.

Change-Id: I40a824888701870b6713c1a16ab671c19b3770ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51900
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:02:59 +00:00
Angel Pons e97a66d371 nb/intel/i945/raminit.c: Replace `DIMM0`
Use the actual value as it is more informative.

Change-Id: Id3bd8ccdf79d1e3fdf97cda049f81271bb017ef7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05 13:02:41 +00:00
Angel Pons a60b42a26a nb/intel/i945: Refactor `dump_spd_registers` function
Use the mainboard-provided SPD map and skip unused addresses.

Change-Id: I2b5b71cff290343c1000d5613209049fa9724e3d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05 13:02:27 +00:00
Angel Pons 6c6e049282 device/dram/ddr4.h: Align with DDR3 and DDR2
Drop unnecessary typedefs and rename DDR4-specific definitions to avoid
name clashes, as done for DDR3 in earlier commits. This allows including
and using both DDR3 and DDR4 headers in the same compilation unit.

Change-Id: I17f1cd88f83251ec23e9783a617f4d2ed41b07f0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51898
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:02:00 +00:00
Angel Pons acd30e9017 include/spd_ddr2.h: Remove unused and redundant file
DDR2-related definitions exist in `device/dram/ddr2` already.

Change-Id: I509f728138327d8a0a88e4503235f05bf14aed20
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51897
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:01:51 +00:00
Angel Pons 18571389d5 device/dram/ddr3: Rename DDR3 SPD memory types
To avoid name clashes with definitions for other DRAM generations,
rename the enum type and values to contain `ddr3` or `DDR3`.

Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:01:37 +00:00
Angel Pons afb3d7e7ec device/dram/ddr3: Get rid of useless typedefs
These typedefs are not necessary. Remove them, and rename some elements
to avoid any confusion with other DRAM generations, such as DDR4.

Change-Id: Ibe40f33372358262c540e371f7866b06a4ac842a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51895
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:01:29 +00:00
Raul E Rangel 4774012515 soc/amd/common/espi: Add ESPI_ prefix to SLAVE0_INT_EN
This matches the other register definitions.

BUG=b:183524609
TEST=Build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0ed92add633f294f92c6a0dde32851d01b10db3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 00:44:43 +00:00
Martin Roth f3314c20de soc/amd/cezanne: Clear eSPI ranges before configuring eSPI
The Cezanne PSP configures the eSPI with the assumption that it's a
majolica, setting up both the serial port and the majolica EC IO decode
ranges.  Since guybrush is NOT a majolica, this doesn't work very well
there.  Clearing the decode ranges allows the guybrush platform to set
the decode ranges needed for its EC.

BUG=b:183524609
TEST=Set up eSPI on Guybrush

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I77cfb948cb9ae6d1cf001bd9e66cede8d93f50b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 00:44:19 +00:00
Martin Roth 011bf13715 soc/amd/common: Add func to clear eSPI IO & memory decode ranges
Previously, the eSPI code would only add to existing decode ranges, and
there wasn't any way to clear ranges.  This clears all the ranges so
the eSPI configuration can start fresh.

BUG=b:183207262, b:183974365
TEST=Verify on Guybrush

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic4e67c40d34915505bdd5b431a064d2c7b6bbc70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 00:43:55 +00:00
Angel Pons da335abfe7 soc/ti/am335x/mmc.c: Fix memset length argument
The sizeof() operator was being applied to a pointer-to-struct type.
Correct this, so that the entire struct space gets cleared.

Change-Id: Ieab3aaa2d07a928f27004b94132377d5dae935c0
Found-by: Coverity CID 1451732
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52054
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Sam Lewis <sam.vr.lewis@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-04 09:58:26 +00:00
Michael Niewöhner 0887fc4dbc docs/mb/supermicro: add SUM tool for flashing with disabled ME
Change-Id: I08543c0908a6cb4ef9fb46d0eb3a7aa481fb95d9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49887
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-03 20:25:44 +00:00
Julius Werner 0972871a23 coreboot_tables: Print strapping IDs when adding them to coreboot table
These used to be printed before CB:46605. Having them in the logs can be
a huge timesaver when debugging logs sent to you by other people
(especially from systems that don't boot all the way). Let's add them
back.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifdbfdd29d25a0937c27113ace776f7aec231a57d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-02 21:23:13 +00:00
John Su 45e103ca87 mb/google/zork/vilboz: Fix audio test failure on LTE SKU
Use board id to switch acp_i2s_use_external_48mhz_osc enable.

BUG=b:181720406
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I085c39accd82bf72e4ebbc0394382ed4a7d4e901
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-04-02 20:52:57 +00:00
Tim Wawrzynczak a10cc8a98b mb/intel/adlrvp: Update VBT filenames
These files were just renamed to put `adlrvp` in between `vbt`
and the memory technology type.

Change-Id: Icefbac462d0ec9c660541e9cf44686d6dcf82dfd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52032
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-02 20:47:28 +00:00
Karthikeyan Ramasubramanian 1e36dc078e mb/google/guybrush: Enable early EC Software Sync
BUG=None
TEST=Build and boot to OS in Guybrush. Ensure that the EC Software Sync
is complete.

Change-Id: Id8655b6f805e14ce3cb71777c1cc175f45841fcc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-02 16:25:11 +00:00