At this point, the zork platform will only use psp_verstage, so remove
the VBOOT_STARTS_IN_BOOTBLOCK option and set code for VBOOT_STARTS-
BEFORE_BOOTBLOCK to always be used.
TEST=Build & Boot Morphius
BRANCH=Zork
BUG=b:172848137
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I30d90fe82c37966a860b52c07a3550dcecf8d19d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a function that initializes GPIOs based on the sleep type that
the system is coming back from. This allows initialization of the
fingerprint GPIOs which need to be handled differently between wake
from S3 and boot from S5.
On initial boot, the state of the FP sensor could be either
enabled or disabled. Because of this, on boot, we power off
the sensor for >200ms, to reset its state, then power it back on.
In suspend/resume, the fingerprint sensor should remain powered
the entire time.
If fingerprint is disabled on the trembyle-based board, set the pins
to no-connect. Dalboz doesn't have fingerprint and the GPIOS are
configured differently due to the FT5 chip having fewer GPIOS than
FP5, so nothing needs to be initialized there.
There were also a couple of trivial comment clean ups regarding the
FPMCU GPIOS.
BUG=b:171837716
TEST=Boot & Check GPIO states.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I16a2e621145782e0a908bb3e49478586c09a0e0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: I75a92616f11054993ff5a5bfefce5c3f4638c07c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Create the shuboz variant of the zork reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:172021093
BRANCH=none
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I3f62625f8cbde1c9adf8ab335edeb9e811e32679
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47152
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust USB2 phy si setting fine tune on DVT for Ezkinil.
BRANCH=zork
BUG=b:156315391
TEST=Measuring scope timing and test usb detection
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: Id537b6e9a17f47481b6aedcea0c6a8474d993b6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since the mainboard Kconfig is sourced before the SoC one, it would
still be possible to override this setting at mainboard level, even
though that shouldn't be needed. The maximum CPU count for Picasso is 8,
since the chips have only up to 4 cores with up to two threads each.
Change-Id: I53449b8fa73c5d13e6ea77bee6eed8896b7d3ec3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47205
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ELAN touch support and update Goodix settings.
BUG=b:157265632
BRANCH=zork
TEST=emerge coreboot and check both touch screen are workable.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icfc2421061e8b3163d7d5108673351bc17df20ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
We all knew this was coming, 32 bits is never enough. Doing this early
so that it doesn't affect too much code yet. Take care of every usage of
fw_config throughout the codebase so the conversion is all done at once.
BUG=b:169668368
TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG
and verify the console print contained that bit.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove code to turn on backlight during ACPI mode because backlight has
been properly enabled in ACPI.
BUG=b:158087989
BRANCH=Zork
TEST=tested backlight during reboot and suspend
Signed-off-by: Josie Nordrum <JosieNordrum@google.com>
Change-Id: I3bf06042aa19e4559127d611d401f0ba0516b3a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since google_chromeec_cbi_get_board_version and google_chromeec_cbi_get_fw_config both call cbi_get_unit32 and return 0 as success, non-zero as failure. Let's add more readability for the false condition.
BUG=None
TEST=check with empty CBI value
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia49ac1ee35302f8f6afe8c0eb8e13afdf36c5b2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46566
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enhance USB 2.0 C0/C1 A0/A1 SI by increasing the level of
"HS DC Voltage Level" and " Disconnect Threshold Adjustment" registers.
COMPDISTUNE0: 0x3->0x7
TXVREFTUNE0: 0x6->0xf
BUG=b:166398726
BRANCH=zork
TEST=1. emerge-zork coreboot
2. check U2 register is set correctly.
3. U2 SI all pass
Change-Id: I69d942605c6d43ece0d71f67df3a5e00b998219b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46545
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
VDD Slope: 62852 -> 62641
SOC Slope: 28022 -> 28333
BUG=b:170531252
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass AMD SDLE/Stardust test
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Id831907aa47be27fef2e33bb884a1118ffec14a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The disconnect voltage needs to be adjusted up because the HS DC voltage
level is 0xF.
BUG=b:170879690
TEST=Servo_v4 USB hub functions
BRANCH=zork
Change-Id: If8662015a45c57e457b4593e55af888084842f58
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Enhance USB 2.0 SI by increasing the level of "HS DC Voltage Level"
and "Disconnect Threshold Adjustment".
COMPDISTUNE0: 0x3->0x7
TXVREFTUNE0: 0x6->0xf
BUG=b:162614573
BRANCH=zork
TEST=1. emerge-zork coreboot
2. check U2 registers are set correctly
3. test with servo v4 type-c, it's working expectedly.
4. U2 SI pass
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I278cc0aaddbc9fce595bf57ca69ee8abfc9f5659
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46537
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
BUG=b:168265881
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: Id6c4f1a92d7f2ad293df7b63694e9665b85f8018
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46472
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit c4a5acdabc.
Reason for revert: Dalboz is missing pull-up on cmd line, so 400khz is not possible.
TEST=Boot Dalboz
BUG=b:159823235, b:169940175
BRANCH=zork
Change-Id: I89653bfeefa522c17ee2d736215bc22aa445871c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Berknip has SSD/eMMC SKU, we should turn off eMMC if storage is NVMe SSD.
BUG=b:170592992
BRANCH=zork
TEST=1. emerge-zork coreboot
2. Check eMMC is enabled or disabled based on the eMMC bit in
FW_CONFIG.
Change-Id: I7aeabc98fc16bc2837c8dcdc40c3c6a80898cdc9
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=Boot dirinboz, run integrity test, b:169940185
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I6bac8284b67070ff2c5838257f4ae2ead0e69c22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45934
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=WIP
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1191d73a2a3f72f99de187a946162460acbb287a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45935
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=WIP
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I2fcbe35103020c3444902c077b4985f87f970671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45936
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=Boot on Vilboz with emmc
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I9a1e47dbee3fcc7317857d40c5418be30d755d61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45933
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=Boot Berknip w/ eMMC to OS.
BRANCH=zork
Change-Id: I5d55f55b8208b4dc3fbdc9d1ec6333f9e211e3fd
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45931
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current Ram_Id: 0011 MT40A1G16KNR-075-E never be built before.
Remove it and change use micron-MT40A1G16KD-062E-E for ram_id:0011.
BRANCH=zork
BUG=b:159316110
TEST=run gen_part_id then check the generated files.
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: I28fc39f17e06ecd39f6567613e6ff5919becb2fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45810
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=Boot Ezkinil w/ eMMC to OS.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ida0bbf9bd772ab7d384d5d097fa3b02b846a3efa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45852
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=Boot on morphius with and without patch, confirm ~7ms improvement
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I7f6efd3d5839f154f2487a07654be8e35634bbbc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45932
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To remove the xhci0_force_gen1 and use usb3_port_force_gen1 instead.
The xhci0_force_gen1 is used for force all port on xhci0 to USB3 GEN1.
Now variant can use the usb3_port_force_gen1 to customize which port
it needs to limit.
BUG=b:167651308
BRANCH=zork
TEST=Build, verify the USB3 speed in gen1
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: If5f0c1f22d8c98c4461f09d074bf082c340b14d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
In morphius, the USB3 typeA port needs to set to gen1, and for ezkinil
all the USB3 ports should force to gen1. So set the corresponding
setting to usb3_port_force_gen1 to force USB3 to Gen1.
BUG=b:167651308
BRANCH=zork
TEST=Build, verify the USB3 speed in gen1
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I10419b91fe86fe3e06de36ddfe0d1769c1031f8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add support for trackpoint wakeup from S3 by adding device events to
mainboard and defining for morphius.
BUG=b:160345665
BRANCH=zork
TEST=tested trackpoint wake from S3 on morphius DVT
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: I982f0f4b60fbaeb389774531e1dee83da77cb8a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Adjust Touchscreen delay off values to let suspend off timing match
power down specificatiion.
BRANCH=zork
BUG=b:163434386
TEST=Measuring scope timing
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: I58866122f441cc3c427e659b8a5fdb6643987882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Configure EMMC_RESET_L (GPIO68) to drive high by default. As per JEDEC
specification for eMMC, RST_n_FUNCTION defaults to temporarily disable
reset using RST_n signal (which is connected to EMMC_RESET_L on
zork). Chrome OS platforms do not configure RST_n_FUNCTION thus making
the reset signal unused. The spec also says that there are no internal
pulls on the card and hence the RST_n signal should be driven
appropriately to prevent the input circuits from flowing unnecessary
leakage current.
Thus, even though the line remains unused, since it is connected in
hardware, this change drives EMMC_RESET_L to high.
BUG=b:169222156
BRANCH=zork
TEST=emerge-zork coreboot
eMMC DUT reboot/suspend x100 iterations pass
Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This fix needs to go into ACPI in the long-term, but this
should suffice in the short-term.
BUG=b:158087989
TEST=Boot berknip, verify backlight is enabled. Test suspend
& resume sequence, backlight is still enabled.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6ecc3c9e397c9756a78e480d3f639c507879a0ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45854
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SMU code was assuming that GPIO 85 was used for a fan, which caused
interesting backlight flickering. That has now been fixed, so remove
the code that reconfigured it to a GPIO on resume.
BUG=b:155667589
TEST=Verify the screen does not flicker on resume from S3
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6d4f9d98e9df52fefab9b20d0ab0f0b67512d356
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
They should be tuned per board to get the best signal and boot time.
This fixes the HS400 preset, so it's correctly set to A. It also changes
the SDR50 and DDR50 presets to B. We can't boot correctly when DDR50 is
set to A.
I chose 1 as the init kHz value since that's what depthcharge uses to
calculate the init clock.
BUG=b:159823235
TEST=Boot Ezkinil and dump SDHCI preset registers.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie2f3497b65d771820ab1a803fec73265547f8906
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
update the telemetry setting for second SDLE testing(for APU power adjusting).
Those values are used to power calibration the APU power and achieving
the best performance.
BUG=b:160698427
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4cf5b8f090befd6a3c4990f44f2f200bc66aa1f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44804
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These parts have not been used in any vilboz devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=vilboz
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611994
TEST=none
Change-Id: I99614acaf45db0556120c883577494d9f753ea12
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45679
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data
sheets.
BUG=b:165611994
TEST=Compared generated SPD with data sheets and checked in SPD
Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
