Commit Graph

26296 Commits

Author SHA1 Message Date
Arthur Heymans e7cacb1a84 mb/intel/dg43gt: Enable the GBE
This was blindly copied from logs created under vendor BIOS in non-descriptor
mode which apparently set LAND in BUC.

Change-Id: I94c917600421ee742ece7f6f71309da80261da28
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-13 12:25:24 +00:00
Julius Werner 487f7f24a5 arm64: mmu: Spot check security state for TTB mapping
Since commit 372d0ff1d1 (arch/arm64: mmu: Spot check TTB memory
attributes), we already check the memory attributes that the TTB region
is mapped with to avoid configuration mistakes that cause weird issues
(because the MMU walks the page tables with different memory attributes
than they were written with). Unfortunately, we only checked
cachability, but the security state attribute is just as important for
this (because it is part of the cache tag, meaning that a cache entry
created by accessing the non-secure mapping won't be used when trying to
read the same address through a secure mapping... and since AArch64 page
table walks are cache snooping and we rely on that behavior, this can
lead to the MMU not seeing the new page table entries we just wrote).

This patch adds the check for security state and cleans up that code a
little.

Change-Id: I70cda4f76f201b03d69a9ece063a3830b15ac04b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/28017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-13 12:24:56 +00:00
Richard Spiegel 72b2022b31 cpu/x86/smm/smm_module_loader.c: Avoid static analysis error "unused value"
In procedure smm_load_module, variables fxsave_size and fxsave_area are set
to 0 and NULL, but if CONFIG_SSE is enabled, they are overwritten. Change
the code setting the value to an "else" of the "if" testing CONFIG_SSE, thus
avoiding static analysis error.

BUG=b:112253891
TEST=Build and boot grunt.

Change-Id: I3042b037017a082378b53ee419c769c535632038
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-13 12:24:34 +00:00
Matt Delco 9fb8e22ffa soc/intel/skylake: use unique _uid
There's two cases of 1 being used.  This changes the
eighth instance to use 8.

Change-Id: I7057a4345dadcc6f8fb43093844d27007444f481
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-13 12:23:51 +00:00
Matt Delco d7d376b726 ec/google/chromeec: de-dup a _UID
There's two instances od _UID 1 for PNP0C02.  This change moves the
more system-specific instance of the two to a higher number. I
believe these are the 4 I'm seeing.

soc/intel/skylake/acpi/systemagent.asl
Device (PDRC)
	Name (_HID, EISAID ("PNP0C02"))
	Name (_UID, 1)

soc/intel/skylake/acpi/lpc.asl
Device (LDRC)
	Name (_HID, EISAID ("PNP0C02"))
	Name (_UID, 2)

ec/google/chromeec/acpi/superio.asl
Device (ECMM) {
	Name (_HID, EISAID ("PNP0C02"))
	Name (_UID, 1)

ec/google/chromeec/acpi/superio.asl
Device (ECUI) {
	Name (_HID, EISAID ("PNP0C02"))
	Name (_UID, 3)

Change-Id: I2b0f1064726a1fa3940ccfb2a4627c79a26684e4
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-13 12:23:37 +00:00
Martin Roth c210d0e31a .checkpatch.conf: Ignore a few more warnings
- PRINTK_WITHOUT_KERN_LEVEL is a new warning that coreboot's printks
don't follow.
- UNDOCUMENTED_DT_STRING is ignored because we don't have any
documentation for .dt files.
- SPDX_LICENSE_TAG is another new warning.  We can evaluate adding the
spdx license tags to our files, but at this point they aren't there, so
disable it for now.

Change-Id: I4b7fcfc0339b358a48e77188d85b47c022c7eb49
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-13 12:23:24 +00:00
Tristan Shieh 1efe2578c0 mediatek: Map SRAM as secure and cached memory
This patch changes the mapping of SRAM from non-secure to secure.
Without this patch, mmu_config_range() can not work when MMU is
enabled. The new config is still in non-secure cache since TTB section
is allocated in SRAM which is mapped as non-secure.

BUG=b:80501386
TEST=Boots correctly on Kukui and Elm

Change-Id: Ia5b8716cfcca64d1d716a177225ea2f7ac2920a6
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-13 12:22:52 +00:00
Nick Vaccaro 4cb8ac234b mb/google/poppy/variants/nocturne: remove icc_max overrides
Remove icc_max overrides to allow SoC code to set proper
icc_max based on CPU SKU.

BUG=b:78122599
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash to
nocturne, boot to kernel and verify device doesn't hang after
a few minutes.

Change-Id: I37c44e2428b802d754f2b12b8a57601d257e6582
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27996
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13 12:22:27 +00:00
Nick Vaccaro 2dd7b6b2f9 mb/google/poppy/variant/nocturne: update PL2 based on CPU sku
This patch adds a function to overwrite PL2 setting based on CPU
sku. From doc #594883, PL2 is 18W for AML-Y.

BUG=b:110890675
BRANCH=None
TEST=emerge-nocturne coreboot chromeos-bootimage & test with AML-Y
     and KBL-Y skus.

Change-Id: Idfdc0c2434fdef56a7c25df05e640837a5096973
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27997
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13 12:22:17 +00:00
Gaggery Tsai 7130ca0ce0 mb/google/poppy/variant/atlas: Update PL2 based on CPU sku
This patch adds a function to overwrite PL2 setting based on CPU
sku. From doc #594883, PL2 is 18W for AML-Y.

BUG=b:110890675
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage & test with AML-Y
     and KBL-Y skus.

Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27765
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13 12:22:05 +00:00
Chris Zhou 736b124136 intel/apollolake: Fix typo in dptf.asl
Fix define typo in dptf.asl

BUG=none
TEST=emerge-octopus coreboot PASS

Change-Id: I1c3bd55d1507e6fffe638bba38c99a9851b8a96a
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-08-13 12:21:20 +00:00
John Su 31c2ccacf6 mb/google/octopus/variants/fleex: Set up DPTF table
Follow thermal table (b:112274477 comment#1) for first tunning.

BUG=b:112274477
TEST=Match the result from DPTF UI.

Change-Id: I63b2e50a4f6fc5453e6564e277600498ac0e6244
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-08-13 12:21:01 +00:00
Denis 'GNUtoo' Carikli 217ecd112b utils: spkmodem: suggest to use parec instead of parecord
Using recent versions of parecord produces the following:
Failed to open audio file.

According to the manual:
  -r | --record
         Capture audio data and write it to the specified file or to STDOUT if none is specified. If the
         tool is called under the name parec this is the default.

so we suggest parec instead.

Change-Id: I8b821df67b10e9d6533c4cbe19c646c84d436c27
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/23863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
2018-08-13 12:19:33 +00:00
Denis 'GNUtoo' Carikli 0005aabe2f utils: spkmodem: Add Makefile and gitignore
Change-Id: Ie3a6a777f5b667e881a4462bdd44a34dbace5520
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/23862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13 12:19:12 +00:00
Tristan Shieh 9315a045cb mediatek/mt8183: Add DRAM resource in ramstage
Add DRAM resource in ramstage to load payload.

BUG=b:80501386
TEST=Load bl31 and depthcharge correctly on Kukui with more patches
     applied.

Change-Id: Ie793b403bbbdb3c231dfa2caef29dcbb596b1a61
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27971
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13 12:17:45 +00:00
Raul E Rangel 128b0cf66e security/vboot/Makefile: Use shell cat instead of make file command
The make `file` command is apparently a v4.2 feature only. Replace it
with a shell cat.

BUG=none
TEST=verified fwid.region was created correctly

Change-Id: I5e32a521ad3e6759853f0cde2e4c4db6e564d3be
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-13 12:17:25 +00:00
Philipp Deppenwiese 9ed805cc76 soc/broadcom/cygnus: Increase romstage SRAM size in memlayout
* Needed for additional code in later patches.
* SOC is obsolete anyway.

Change-Id: I5bbdf19cc886103e9e7a6b75219d6881cfe9c757
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/23764
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13 12:16:32 +00:00
John Zhao 0f3574e9b6 mb/google/octopus: Enable SAR config for Intel 9560 module
Enable the GEO SAR feature for Octopus. Program wifi_sar VPD key.
coreboot reads the VPD and creates the ACPI table as per the WGDS spec.

BUG=b:112288077
TEST=Program VPD key, extract acpi table ssdt and valiate WGDS entry.

Change-Id: I40a6fd9e0ec8b440996bf3389322fd89bcca15a4
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-13 12:16:15 +00:00
Furquan Shaikh fbd6f3995c mb/google/octopus: Do not configure IOStandby for WLAN_PE_RST
PERST signal is asserted/deasserted by ACPI routines during
suspend/resume. Configuring IOStandby for WLAN_PE_RST can result in
failure to resume from suspend state with wake-over-WLAN. This change
removes the IOStandby configuration for WLAN_PE_RST.

BUG=b:112371978

Change-Id: Ic7c0b2aa144233f8bbb4e5169d96347a1290abe1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12 17:58:57 +00:00
Furquan Shaikh 654289993b mb/google/octopus: Configure WiFi wake as NC when using CNVi
When CNVi is being used, external wake using GPIO_119 is not
required. This change configures GPIO_119 as PAD_NC if CNVi is taken
out of reset.

BUG=b:112371978

Change-Id: Ifee90f428ed43c4d7c612c170476aff43b4a33ce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12 17:58:49 +00:00
Furquan Shaikh 9cd65cd4b5 soc/intel/apollolake: Get rid of cnvi.asl
There is no need to add a special cnvi.asl file for the CNVi
device. This can be handled by drivers/intel/wifi just like a PCIe
WiFi device. This change gets rid of the cnvi.asl file and its usage
in southbridge.asl file.

BUG=b:112371978

Change-Id: I0b798cdd430768730b7ada61ca4cb1f63c2a4229
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12 17:58:37 +00:00
Furquan Shaikh c3cbbe6a78 mb/google/octopus: Use correct chip for CNVi device
This change uses drivers/intel/wifi chip for CNVi device to ensure
that:
1. Correct device name shows up in ACPI node
2. It is possible to pass any parameters from devicetree to wifi
driver for SSDT generation.

BUG=b:112371978

Change-Id: Ia49820dd4f9cf2e0a9ef14931fbddd8a723208c0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12 17:58:25 +00:00
Furquan Shaikh 19ab8139e8 drivers/intel/wifi: Get rid of unused wrdd.asl
This change gets rid of unused wrdd.asl in intel wifi driver. This
file became redundant when all boards moved to using SSDT for wifi
device.

Change-Id: I8b5b3816d77c90e75052c58a3120ab62185873a7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27963
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-12 17:58:16 +00:00
Furquan Shaikh 11d0c32e69 drivers/intel/wifi: Skip adding SSDT entry if device is disabled
This change checks to ensure that device is enabled before adding
entry into SSDT.

BUG=b:112371978

Change-Id: Ibe4811bef8cf0978b7a82d66a32f96247b9c823d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-12 17:57:59 +00:00
Furquan Shaikh 617fcf3934 mb/google/octopus: Dynamically disable CNVi/PCIe device
This change checks to see if CNVi module is out of reset:
1. If yes, then PCIe device for WiFi is disabled.
2. If no, then CNVi device is disabled.

BUG=b:112371978

Change-Id: I6e6cf2e646c897df017913056db87ac0cffa1a8e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-08-12 17:57:51 +00:00
Furquan Shaikh 6cf9402ebb soc/intel/apollolake: Add CNVi device to list of PCI devs
This change adds CNVi device to list of PCI devs.

BUG=b:112371978

Change-Id: I6def98db3846c2244812a9a2ce84340bd2149b48
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-12 17:57:43 +00:00
Furquan Shaikh 4b95fa277a mb/google/octopus: Disable unused I2C2 in devicetree
I2C2 is unused on all octopus variants. This change disables it in
devicetree.

BUG=b:112458032

Change-Id: I55abef864c06a448011f9570d3e6c0aa8bfdc5bc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28016
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-12 17:57:31 +00:00
Furquan Shaikh ff23d21e33 mb/google/octopus/var/fleex: Update GPIO config for fleex bid >= 1
This change updates GPIO configuration for fleex boards with id >= 1
This follows the same model as phaser:
a. Dynamically update touchscreen power enable GPIO in devicetree.
b. Provide default and bid0 tables for GPIO configuration in ramstage.
c. Configure WLAN enable GPIO differently in bootblock based on
boardid.
d. Disable unused I2C devices in devicetree.

BUG=b:112458032
TEST=No errors observed on boot-up on fleex.

Change-Id: Ib4c449168b08e2393e2395d6b49469be5599c2ce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-12 17:57:19 +00:00
Tristan Corrick 17ce00d288 mb/asus/maximus_iv_gene-z: Add VBT
The file `data.vbt` matches the VBT in the latest version of the vendor
firmware (version 3603). Tested with Linux 4.9 and everything works as
expected.

Change-Id: I8e3b1d274ac0df63989d966f477013e780611fa1
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/28050
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-12 17:08:49 +00:00
Xiang Wang c1433f77f3 util/lint: Remove register name identified as a misspelled word
RISC-V has a register named 'sepc' but checkpatch identifies it as a
misspelling of 'spec'. Remove it from the list.

Change-Id: I7b092d6f04e28fba36095c607bc59346fb5c605d
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-11 15:14:43 +00:00
Kamil Wcislo bf5ccfd05f drivers/pc80/tpm: add support for SLB9665 TPM2.0 module
SLB9665 are not initialized correctly. It looks like SLB9665 and SLB9660
return the same DEV ID. Initialize these devices according to TPM Kconfig
selections.

Tested on apu2 with following change:
https://review.coreboot.org/#/c/coreboot/+/28000/

Change-Id: Ic20b9a65ef6a4ee392a9352f7c9bf01b2496f482
Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-11 04:40:18 +00:00
Philipp Deppenwiese 545ed7ab3b drivers/i2c: Add i2c TPM support for different stages
Change-Id: Ib0839933f8b59f0c87cdda4e5374828bd6f1099f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/23759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-08-10 23:25:52 +00:00
Patrick Rudolph 52acef175e soc/cavium/cn81xx: Fix minor things
* Move cbmem.c to cn81xx folder
* Store CBMEM below 4 GiB
* Make sure CBMEM doesn't overlap with ATF scratchpad
* Fix ATF scratchpad not marked as reserved due to wrong calculation
* The scratchpad is the last 1 MiB at the end of DRAM.

Tested on Cavium CN81xx EVB:
The ATF scratchpad is now marked reserved and the configuration tables
are located below 4 GiB. Linux still boots.

Change-Id: Ibbc8b586f04bd6867c045f5546b32a77c057ac74
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27955
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10 23:24:56 +00:00
Patrick Rudolph eead87961f [HACK]cavium/cn81xx/soc: Don't advertise CAR area as usable
It's broken.

Change-Id: I3ec8fff99e21cbdf4ad3f4562ff9bbc1cd3c135b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-10 23:23:53 +00:00
Patrick Rudolph 3fca4ed45e lib/fit: support booting initrd placed above 4GiB
Store initrd offset as 64bit integer.

Tested on Cavium CN81XX EVB: The initrd could be loaded when placed
above 4GiB. Previously it failed to find the initrd.

Change-Id: I5d1ae860ae4a4465546bc0ef89937d611d1e56ab
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-10 23:23:17 +00:00
Aaron Durbin 6539edef41 mb/google/octopus: add support for new shared memory config
Allow for shared dram configuration by introducing a new table
that collapses the common settings after removing the part
numbers. When employing this scheme the part number comes
from CBI.

BUG=b:112203105
TEST=Placed part number in cbi. Faked out memory sku id. And enabled
     DRAM part num always in cbi. Everything checked out.

Change-Id: I5229695ce3eb686421b89ac55d8df4b9fcec705c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-10 23:00:46 +00:00
Elyes HAOUAS 3d45000c9c src: Fix typo
Change-Id: I689c5663ef59861f79b68220abd146144f7618de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-10 21:25:53 +00:00
Elyes HAOUAS 1895838e7a src/drivers: Fix typo
Change-Id: I9144937b72a98517cbd41c093cff7bad543b4140
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27916
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10 21:25:30 +00:00
Angel Pons 5cdd9aab34 mb/gigabyte/ga-{h61m-s2pv,b75m-d3h,b75m-d3v}: Clean up CMOS files
Options that were deemed unneceesary on other code reviews have
been removed from the layout files. In addition, the checksummed
range has been extended to cover sata_mode and gfx_uma_size.

Change-Id: Id9e904f447809231806a786e39ed638f21e1bc5a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-10 16:44:36 +00:00
Angel Pons 940bb4ea42 mb/gigabyte/ga-{h61m-s2pv,b75m-d3h,b75m-d3v}: Clean up mainboard code
I ported ga-h61m-s2pv based on the two Gigabyte b75m boards.
Based on another mainboard's code review comments, this patch
improves the code quality of these three similar boards.

ga-h61m-s2pv is tested and confirmed to be working, but I cannot
say the same regarding the other two mainboards as I do not have them.

Change-Id: Ib7747cceb5ba56f791677204cdc4c54c129c70c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-10 16:44:17 +00:00
Patrick Rudolph dfc30130e9 fit: Handle decompression errors properly
Set payload to NULL in case of decompression errors.
Fixes the attempt to boot a kernel that couldn't be decompressed.

Change-Id: I3a602b0e90923a0b5a3683c4a0adf9e4733d5a2a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10 15:14:16 +00:00
David Hendricks fb03dd6043 linuxboot: remove curley brace expansion from u-root commands
Curley brace expansion is a bash-ism, so we can't use it for the
u-root command list.

This unfortunately also breaks the current Kconfig option since the
list needs to be separated by space instead of commas.

Change-Id: I429a52c1673e29b7180ee6f53deaa7a551a1a9b3
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/27967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-10 09:05:04 +00:00
Maulik fc19ab5f34 src/soc/intel: Add new device IDs to support coffeelake
1. Add new device IDs for SATA, GT and Northbridge to pci_ids.h
2. Add entry to identify CFL U GT and CPU to respective files
3. Add entry to identify CFL U to report_platform.c

BUG=none
BRANCH=none
TEST=Boot to CFL U RVP board with this patch and check if coreboot is
able to enumerate various devices and display correct component names properly
in serial logs.

Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed
Signed-off-by: Maulik <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-08-10 06:31:01 +00:00
Julius Werner e819c85760 arm64: Turn architectural register accessors into inline functions
Accesses to architectural registers should be really fast -- they're
just registers, after all. In fact, the arm64 architecture uses them for
some timing-senstive uses like the architectural timer. A read should be:
one instruction, no data dependencies, done.

However, our current coreboot framework wraps each of these accesses
into a separate function. Suddenly you have to spill registers on a
stack, make a function call, move your stack pointer, etc. When running
without MMU this adds a significant enough delay to cause timing
problems when bitbanging a UART on SDM845.

This patch replaces all those existing functions with static inline
definitions in the header so they will get reduced to a single
instruction as they should be. Also use some macros to condense the code
a little since they're all so regular, which should make it easier to
add more in the future. This patch also expands all the data types to
uint64_t since that's what the actual assembly instruction accesses,
even if the register itself only has 32 bits (the others will be ignored
by the processor and set to 0 on read). Arm regularly expands registers
as they add new bit fields to them with newer iterations of the
architecture anyway, so this just prepares us for the inevitable.

Change-Id: I2c41cc3ce49ee26bf12cd34e3d0509d8e61ffc63
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10 04:16:46 +00:00
Julius Werner 0c5f61a01c arm64: Drop checks for current exception level, hardcode EL3 assumption
When we first created the arm64 port, we weren't quite sure whether
coreboot would always run in EL3 on all platforms. The AArch64 A.R.M.
technically considers this exception level optional, but in practice all
SoCs seem to support it. We have since accumulated a lot of code that
already hardcodes an implicit or explicit assumption of executing in EL3
somewhere, so coreboot wouldn't work on a system that tries to enter it
in EL1/2 right now anyway.

However, some of our low level support libraries (in particular those
for accessing architectural registers) still have provisions for
running at different exception levels built-in, and often use switch
statements over the current exception level to decide which register to
access. This includes an unnecessarily large amount of code for what
should be single-instruction operations and precludes further
optimization via inlining.

This patch removes any remaining code that dynamically depends on the
current exception level and makes the assumption that coreboot executes
at EL3 official. If this ever needs to change for a future platform, it
would probably be cleaner to set the expected exception level in a
Kconfig rather than always probing it at runtime.

Change-Id: I1a9fb9b4227bd15a013080d1c7eabd48515fdb67
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10 04:16:25 +00:00
Julius Werner 73be9dd82c arm64: Remove set_cntfrq() function
CNTFRQ_EL0 is a normal AArch64 architectural register like hundreds of
others that are all accessed through the raw_(read|write)_${register}()
family of functions. There's no reason why this register in particular
should have an inconsistent accessor, so replace all instances of
set_cntfrq() with raw_write_cntfrq_el0() and get rid of it.

Change-Id: I599519ba71c287d4085f9ad28d7349ef0b1eea9b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27947
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10 04:16:06 +00:00
Julius Werner af7f9eeddf marvell: Remove 'mvmap2315' SoC
I'm pretty sure this SoC doesn't actually exist.

Change-Id: I53e268ee1795e524a2a4562d67a2b9f28af966d1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27965
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10 04:15:47 +00:00
Julius Werner 3b1987b6be google: Remove board 'rotor'
Rotor is dead, long live [PROJECT NAME REDACTED]!

Change-Id: Ia9308944257255e077a44c1df262c7f49c69890c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27964
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10 04:15:32 +00:00
Aaron Durbin 042b53ad65 mb/google/octopus: add support for fetching DRAM part number from CBI
Add 3 new Kconfig options:
DRAM_PART_NUM_IN_CBI
DRAM_PART_NUM_ALWAYS_IN_CBI
DRAM_PART_IN_CBI_BOARD_ID_MIN

These control whether to 1. attempt to use CBI at all 2. always use cbi
and 3. conditionally use cbi based on board id. The intent is that the
MIN variant would be used for the tranisition period then cut over to
ALWAYS after full transition. Since multiple OEMs have different
schedules these options are there to bridge the gap. yorp. bip, and
octopus build targets would never flip DRAM_PART_NUM_IN_CBI, but in case
someone does the MIN values are 255 to always take the old path.

BUG=b:112203105
TEST=Set correct part number on phaser during testing.

Change-Id: If9a0102806d78e89330b42aa6947d503a8a2deac
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-09 16:56:57 +00:00
Richard Spiegel bb7424f30c arch/x86/tables.c: Avoid static analysis error for unused value
Within procedure arch_write_tables, the pointer "rom_table_end" is updated
every time a table is created. However, after creating last table, pointer
rom_table_end is not used, though it is updated. Add a "(void)rom_table_end;"
at the end to avoid the static analysis error.

BUG=b:112253891
TEST=Build and boot grunt.

Change-Id: I8a34026795c7f0d1bb86c5f5c0469d40aa53994a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09 16:06:06 +00:00