Add a common southbridge gpio code to reduce existing
duplicated code.
By adding it to ram-stage, GPIOs can be changed any time,
without the need of direct register access.
The files are based on bd82x6x and lynxpoint gpio.c.
Change-Id: Iaf0c2f941f2625a5547f9cba79da1b173da6f295
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12893
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Power 8 was once again having build issues. Adding --with-system-zlib
fixes them. It seems the builtin one is only needed when you are going
to build programs, and it falls apart in other cases.
Searching --with-system-zlib reveals this to be a very popular topic.
This has not broken other toolchain builds (for me); it should not for
anyone else. Then again, this is gcc, about which I need say no more.
Change-Id: Ica9d057d88982543b5dda471cc949c31fe15932f
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/13700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Once we lock down the SPI BAR we need to tell SMM to re-init its
SPI driver or it will be unable to write ELOG events via SMI.
This SMI is also sent at the end of depthcharge so there was just
a window where SMI events could get lost.
BUG=chrome-os-partner:50076
BRANCH=glados
TEST=enable DEBUG_SMI, boot to dev screen, press power button and
see elog events get added without without transaction errors.
Change-Id: I1f14717b5e7f29c158dde8fd308bdbfb67eba41a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 60ca24c760c70e2ebe5f3e68f95d3ffdba0fef9e
Original-Change-Id: I4e323249f00954e290a6a30f515e34632681bfdd
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326861
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13697
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The PCH does not set PM1_STS[WAK_STS] bit when waking from a
G3 state, which is triggered by hibernate now on chell when we
do a PMIC shutdown. This means the checks for S5 wake are not
done and instead it is logged as a wake from S0.
BUG=chrome-os-partner:50076
BRANCH=glados
TEST=pass firmware_EventLog test on chell
Change-Id: I3ca05a4824df3401150a63d4b6555f759de40087
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de6c9bac447edd06568193f990f1f4e278576783
Original-Change-Id: I4472498468d620fe69f2b68710e818a4ad287382
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326888
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13696
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This change will allow the kernel to use 4-lane eDP connections
if the GOP driver does not execute and set this bit. If GOP
has executed (everyone but Chrome OS verified mode) the link will
already be up and this will do nothing.
BUG=chrome-os-partner:50197
BRANCH=glados
TEST=boot on chell and ensure 4
Change-Id: I9e2328b00db84f26b9bd03220b8ac0bd5f64cfbf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cff83e18ce9936c8d507f93c8443b7056c62e844
Original-Change-Id: I3f1e5d78b91eb0e4a23fcc196aff0edadc252a0c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/327251
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13690
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This method creates a named object and should be serialized to avoid
a compiler warning from recent iasl releases.
BUG=chrome-os-partner:40635
BRANCH=glados
TEST=emerge-chell coreboot with no iasl warnings
Change-Id: If54df4eca8849a8d278816712164b30a775a41ca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9aa8c5627276be08bf0dc3d0f4b9b7bd3f40c227
Original-Change-Id: Ieb05525503bf61c9922677484aba5479856a3f35
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326843
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13689
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
oldconfig is regularly used to clean up templates that sometimes contain
duplicates or old symbols.
Since it cleans up the config, it doesn't need to fail on issues.
Change-Id: Ife0e9e3b9bfdde1eb6be0e2e38e81b9042cb7950
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13687
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The intend is to seek upgraded microcode in RW section and load it
before Fsp memoryinit, to ensure any goodness in the microcode update,
especially related to memory configuration, can be applied earlier.
BUG=chrome-os-partner:50132
BRANCH=glados
TEST=Built and boot on kunimintus. Verified microcode gets reloaded.
Boot time impact is very minor.
CQ-DEPEND=CL:327170
Change-Id: I1a5df1d1efa25fb256743dca6a661c828263ec7c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d7f700c1876e53194748d1d1c66637b9419b7086
Original-Change-Id: I7083ec6305af9e14a57d7b0cb1bd800cd9e22f44
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327193
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13688
Tested-by: build bot (Jenkins)
Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
These license headers were either not compliant with the coreboot
standard or were missing completely.
Change-Id: I0c46ad9ba7f3d950b3eff96ee6e9c36acbf1a3a5
Signed-off-by: Damien Roth <yves.r.roth@gmail.com>
Reviewed-on: https://review.coreboot.org/13288
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reduce the debug output from FMAP lookups. When we had one or
two FMAP lookups in a boot this was not a big deal, but now that
we do many lookups it is a lot of unnecessary output duplication.
This change reduces these 3 lines:
FMAP: area VBLOCK_A found
FMAP: offset: 200000
FMAP: size: 65536 bytes
To just one line:
FMAP: area VBLOCK_A found @ 200000 (65536 bytes)
And makes the header output only print once:
FMAP: Found "FMAP" version 1.0 at c10000.
FMAP: base = 0 size = 1000000 #areas = 29
BUG=chrome-os-partner:40635
BRANCH=glados
TEST=boot on chell and enjoy non-truncated memconsole
Change-Id: Ib5862b8bfad113a700faae89089557094aa6d499
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6890f36536d4ae6fc4988fc8191b0cff4e33e2e6
Original-Change-Id: Ifefee1ab26e6ee406de552880fbbd5b7916fcadd
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326887
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13695
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
These licence headers were not compliant with the coreboot standard.
Change-Id: I85bb5f971ab1f8ac3e9589f712370fbf09716b67
Signed-off-by: Damien Roth <yves.r.roth@gmail.com>
Reviewed-on: https://review.coreboot.org/13287
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Apparently acpica-unix is shipped under
"A non-open source license (the 'Intel license')" while acpica-unix2
comes under GPLv2/BSD dual license. (see https://acpica.org/Licensing)
So go with unix2.
Change-Id: I412812187bbf488eb4ad6d7fb8d2840f2f5e06d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13686
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Otherwise the image is simply unusable.
Change-Id: I1e2562ba17279d14dc73b05e4f8fa493e06fbcd2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13699
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Ensure the pads passed into the gpio functions are within
range.
Change-Id: Ic523cbfaf60a46709080347af3a36d6330f9a07c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13694
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
To allow sharing macros in ASL as well as C the macros can't
have complex expression because the ASL compiler does not
evaluate those expressions. To that end, just pre-calculate
the values. Lastly, add N_OFFSET and utilize it for symmetry.
Change-Id: I546d71008e776b27ce8bcd24d2cbd2ee1b2d8020
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13693
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The CSE places the bootblock (IBBL in Intel parlance) below 4GiB
at top of the address space. However, it's size is limited to
32KiB. For now, just limit all of bootblock to 32KiB.
Change-Id: I8f84138fb81027eae1712b7af3943942c35cf0ea
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13692
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Certain platforms may need to limit their bootblock size to within
a given size because specific constraints. Allow the size to be
provided by the mainboard or chipset by way of the arch Kconfig
being processed after those.
Change-Id: I46cc6315918cde575070fa2d3e2514f28008f575
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13691
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
We've had a second version of ulzma() that would check the input and
output buffer sizes in libpayload for a while now. Since it's generally
never a bad idea to double-check for overruns, let's port it to coreboot
and use it where applicable. (This requires a small fix in the four byte
at a time read optimization we only have in coreboot, since it made the
stream counter hit the end a little earlier than the algorithm liked and
could trigger an assertion.)
BRANCH=None
BUG=None
TEST=Booted Oak, Jerry and Falco.
Change-Id: Id566b31dfa896ea1b991badf5a6ad9d075aef987
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13637
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These SoCs have come within a kilobyte of their romstage limit, so let's
expand that a little to make room for future core code contributions.
(In the Tegra case just by copying the layout from Tegra210, because
why not? Keeps things simple.)
BRANCH=None
BUG=None
TEST=Ran abuild with and without --chromeos for Foster, Rush, Ryu, Smaug
and Urara.
Change-Id: If8c1ea81cf9827412c78d67a09d54e7a2dc044ac
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13668
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Having two separate memlayouts is an unnecessary complication.
Contributors need to make sure that their code fits into the vboot one
(with smaller stage sizes) either way, and the Tegras have plenty of
SRAM anyway. Let's just make the vboot layout the default (as it was
done on other SoCs) to keep things easier to maintain. The empty SRAM
holes on non-vboot systems where the verstage and work buffer would've
been won't hurt them.
BRANCH=None
BUG=None
TEST=Ran abuild with and without --chromeos on Foster, Rush, Ryu and
Smaug.
Change-Id: If37228facb4de1459cc720dca10bf03e04eb9930
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13667
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch generalizes the approach previously used for ARM32
TTB_SUBTABLES to "auto-detect" whether a certain region was defined in
memlayout.ld. This allows us to get rid of the explicit Kconfig for the
TIMESTAMP region, reducing configuration redundancy and avoiding
confusion when setting up future boards.
(Removing armv4/bootblock_simple.c because it references this Kconfig
and it is a dead file that I just forgot to remove in CL:12076.)
BRANCH=None
BUG=None
TEST=Booted Oak and confirmed that all pre-RAM timestamps are still
there. Built Nyan and Falco.
Change-Id: I557a4b263018511d17baa4177963130a97ea310a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13652
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some spaces crept in where there should be tabs.
Change-Id: Ie70469f5a16e8a2d5933ac632d13551b19761064
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13698
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
cbfstool has a routine to deal with old images that may encourage it to
overwrite the master header. That routine is triggered for
"cbfstool add-master-header" prepared images even though these are not
at risk, and - worse - destroys the chain structure (through a negative
file length), so avoid touching such images.
Change-Id: I9d0bbe3e6300b9b9f3e50347737d1850f83ddad8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13672
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This makes the test IDs the default, taken from depthcharge
master (board/*/fmap.dts, hwid property).
Change-Id: I25793962ac16f451f204dbba6ede6a64c847cfd5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13634
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
When updating an old .config file that has a symbol that has been
removed from the current Kconfig tree, kconfig will generate a warning
and fail to save the updated file. This is incredibly annoying, and
not the goal when trying to eliminate Kconfig warnings.
Instead of generating a warning, just print a message that it's being
ignored. This will remove the offending symbol, while allowing the
updated config file to be saved.
Split the change from 1 line to 3 lines to keep it at 80 characters.
Change-Id: I09d5775c9ed14bde80077b51b862a7f41bee098a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13674
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Those aren't used anymore.
Change-Id: If7baf2d03c47bcc6f69d63a349bbf9d5e749aeac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13685
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This was copied from mrc structure despite them having fields in different
order.
Change-Id: If10ffa3316c5fdc538a6fabf2409512bc8c3e676
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13661
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
off_t wants to be printed with %zd, not %d.
Change-Id: I3f6e1988bb306f4a7738f1f3ccb2093518e4ceb3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13655
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Make sure that the statically defined CRC functions are
enabled by the same conditionals as the code using them.
Change-Id: Ic24e2ed1a80b8e5f6623881b08d86f7b608a206e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13654
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
dep has not been defined (and will hence break the build)
LDFLAGS is not used.
Change-Id: I4f91e1e7a176367aa4e1a1c63a2afc0b3186767e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13653
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It is silly to have a single header to declare the main()
symbol, however some of the arches provided it while
lib/bootblock.c relied on the arch headers to declare it. Just
move the declaration into its own header file and utilize it.
Change-Id: I743b4c286956ae047c17fe46241b699feca73628
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13681
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
jmp_to_elf_entry() is not defined anywhere. Remove it.
Change-Id: I68f996a735f2ef3dd60cf69f9b72c3f1481cbb55
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13680
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Since we're reaching the timestamp limit on certain platforms (both for
the pre-RAM cache and the final CBMEM region), this patch increases the
amount of space for both. In the pre-RAM case, it achieves this by
always utilizing the full size of the TIMESTAMP() region allocated in
memlayout.ld, rather than arbitrarily limiting it to some constant.
BRANCH=None
BUG=None
TEST=Booted Oak and confirmed that I can once again see all pre-RAM
timestamps after picking in the LZ4 patch series.
Change-Id: Iabb075a48d8d1e3e1811afeaad5ab47e7846c972
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13651
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Early UART driver is for bootblock and romstage. It is supposed to be used
when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits
in bootblock requiered for serial to be set up.
Change-Id: I15520d566f107797e68d618885d4379e73d0fa45
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13677
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is the minimum setup needed to both get cache-as-ram setup and a
C environment working. On apollolake, we only get 32 KiB of data
loaded into an SRAM that is readonly to the main CPU. Due to this
restriction we have to set CAR and a C environment very early on.
Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13301
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Patrick Rudolph