Fixed according to the declaration in
soc/intel/common/block/include/intelblocks/cfg.h.
Change-Id: I50dbc00806fefda8f4dac8bfa21dc714a9504566
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardware_Specification.html#pm1-event-grouping
> For ACPI/legacy systems, when transitioning from the legacy to the G0
> working state this register is cleared by platform firmware prior to
> setting the SCI_EN bit (and thus passing control to OSPM). For ACPI
> only platforms (where SCI_EN is always set), when transitioning from
> either the mechanical off (G3) or soft-off state to the G0 working
> state this register is cleared prior to entering the G0 working state.
This means we don't want to clear the PM1 register on resume. By
clearing it the linux kernel can't correctly increment the wake count
when the power button is pressed. The AMD platforms implement the _SWS
ACPI methods, but the linux kernel doesn't actually use these methods.
BUG=b:172021431
TEST=suspend zork and push power button and verify power button
wake_count increments. Verified other wake sources still work.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Stoneyridge selects ARCH_X86 unconditionally and all coreboot code will
run on the x86 cores. On Picasso and later, the Chromebooks run verstage
on the PSP which is an ARM V7 core which needs some special handling
cases in the code, but this doesn't apply to Stoneyridge.
TEST=Timeless build results in an identical image for Google/Careena.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I013efd13b56c0191af034a8c4b58e9b26a31c6e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
According to https://uefi.org/specs/ACPI/6.4/16_Waking_and_Sleeping/sleeping-states.html?highlight=power%20states#
> For ACPI/legacy systems, when transitioning from the legacy to the G0
> working state this register is cleared by platform firmware prior to
> setting the SCI_EN bit.
This change makes sure we clear the PM/GPE blocks are cleared before
enabling the SCI_EN bit.
BUG=b:172021431
TEST=Boot guybrush and morphius to OS and verify suspend resume still
works.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Icc6f542185dc520f8d181423961b74481c0b5506
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use a read modify write sequence when setting the SPI_USE_SPI100 bit in
the SPI100_ENABLE register. This avoids clearing other bits in the
register which might cause instabilities of the SPI interface. The
reference code for Stoneyrige also only sets the SPI_USE_SPI100 bit and
doesn't zero out the other bits.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4d32fc2084bb34ea57924bae68511c6836587790
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Use a read modify write sequence when setting the SPI_USE_SPI100 bit in
the SPI100_ENABLE register. This avoids clearing other bits in the
register which might cause instabilities of the SPI interface. The
reference code for both Picasso and Cezanne also only sets the
SPI_USE_SPI100 bit and doesn't zero out the other bits.
TEST=Verified that Mandolin still boots. It didn't show any signs of
possibly related instabilities before though, so this test doesn't say
much.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I71c2ec1729d5cb4cdff6444b637af29caaa6f1c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
commit 90ac882a32 (soc/amd/common/block/
spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST) introduced a Kconfig
option to enable/disable the 4DW burst support in the SPI flash data
prefetcher, but missed to update the documentation above the
fch_spi_early_init prototype, so update the outdated documentation now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I07c4b0b02251da63d34a172e2636894e99845d6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
These functions can't be weak, because they actually need to configure
the GPIOs for eSPI and the TPM. With this change zork boots again.
I also noticed that zork doesn't use the early table in bootblock. This
means that zork will only boot if psp_verstage is enabled.
BUG=b:209465425
TEST=boot zork to ramstage
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Use KiB and MiB instead of multiplying/dividing with/by the numeric
value when doing region size calculations.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I56c380190b11aa3214cce31b82974327e3d15000
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This change supplies a list of ADL gpios that are connected to non-host
(x86) controllers and should be locked after initial configuration.
Set SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS to enable GPIO locking.
BUG=b:210430600
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
brya0 boots successfully to kernel.
Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
For added security, there are some gpios that an SoC will want to lock
once initially configured, such as gpios attached to non-host (x86)
controllers, so that they can't be recofigured at a later point in
time by rogue code.
Likewise, a mainboard may have some gpios connected to secure busses
and/or devices that they want to protect from being changed post
initial configuration.
This change adds a generic gpio locking mechanism that allows the SoC
to export a list of GPIOs to be locked down and allows the mainboard
to export a list of GPIOs that it wants locked down once
initialization is complete.
Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to
enable this feature.
BUG=b:201430600
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify
brya0 boots successfully to kernel.
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We only have ADL-P 6+8+2 (45W) VR configuration now. Based on the
power map, fill in correct ADL-P 6+8+2 (28W) VR configuration.
BUG=b:202486131
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: Ie8dbd95b2d8e49b5898b2a97aff72e0e64868c8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add Alder Lake-N case for adl_cpu_type and get_supported_lpm_mask.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: If2917ac356fd80f84bcaf70ed710d329e77f7a6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
The patch refectors cpu_set_p_state_to_max_non_turbo_ratio(). The
function is updated to use cpu_get_max_non_turbo_ratio().
TEST=Build the code for Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If73df17faaf7b870ae311460a868d52352683c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The patch defines below APIs :
cpu_is_hybrid_supported() : Check whether CPU is hybrid CPU or not.
cpu_get_bus_frequency() : Get CPU's bus frequency in MHz
cpu_get_max_non_turbo_ratio() : Get CPU's max non-turbo ratio
cpu_get_cpu_type() : Get CPU type. The function must be called if
executing CPU is hybrid.
TEST=Verified the APIs on the Brya board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I680f43952ab4abce6e342206688ad32814970a91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This enum is useful to have around for more than just the one file, so
move it to a common header file, and while we're there, also add an
option for UNKNOWN.
TEST=boot test on brya0
Change-Id: I9ccf0ed9504dbf6c60e521a45ea4b916d3dcbeda
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Check the Alderlake CPU ID to determine if cse sub-paritition update is
required or not.
BUG=b:202143532
Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch adds the following support to coreboot
1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B
partition of BIOS
2. Helper functions to support update.
Pre-requisites to enable IOM/NPHY FW Update:
1. NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and
FW_MAIN_B through board configuration files.
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path
SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path
2. Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition
NPHY/IOM update.
coreboot follows below procedure to update NPHY and IOM:
NPHY Update:
1. coreboot will navigate through the CSE region,
identify the CSE’s NPHY FW version and BIOS NPHY version.
2. Compare both versions, if there is a difference, CSE will trigger an
NPHY FW update. Otherwise, skips the NPHY FW update.
IOM Update:
1. coreboot will navigate through the CSE region, identify CSE's IOM
FW version and BIOS IOM version.
2. Compares both versions, if there is a difference, coreboot will
trigger an IOM FW update.Otherwise, skip IOM FW update.
Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT
PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE
boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only
if CSE boots from CSE RO Boot partition.
Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then
triggers update of NPHY and IOM FW in the CSE Region(RO and RW).
coreboot triggers NPHY/IOM update procedure in all ChromeOS boot
modes(Normal and Recovery).
BUG=b:202143532
BRANCH=None
TEST=Build and verify CSE sub-partitions IOM and NPHY are getting
updated with CBFS IOM and NPHY blobs.
Verified TBT, type-C display, NVMe, SD card, WWAN, Wifi working after
the update.
Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch adds a check to determine if the CSE's current operation mode
is ME_HFS1_COM_SECOVER_MEI_MSG or not before sending HMRFPO_ENABLE
command to CSE. If CSE is already in the ME_HFS1_COM_SECOVER_MEI_MSG,
coreboot skips sending HMRFPO_ENABLE command to CSE to unlock the CSE RW
partition.
TEST=Verify sending HMRFPO_ENABLE command on Brya system.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I387ac7c7296ab06b9bb440d5d40c3286bf879d3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The patch renames the compare_cse_version() function to the
cse_compare_sub_part_version(). It makes the function generic so that
it can be used to compare version of any CSE sub-partition like IOM,
NPHY etc.
TEST=Verified build for Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I88a44a3c0ba2ad8a589602a35ea644dab535b287
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59689
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to
specify the correct amount of PCIe I/O.
Document number 645550 indicates that Alder Lake-N has 12 PCH root ports
and no CPU root ports.
Document number 645548 indicates ADL-N has 5 clock sources and 5 clock
request signals.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The VR configuration should be based on the different Soc SKU type. And
we also have different SKU in the same SA PCI ID.
Therefore, add TDP to recognize the correct SKU and give the correct
power setting.
BUG=b:202486131
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I4d31e7afc76d9a8c772781671f92ec08f9d8713f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Guybrush uses secure counters to protect against High Definition (HD)
protected content rollback. These secure counters are hosted in TPM
NVRAM. Enable secure counters so that they are defined in PSP verstage.
BUG=b:205261728
TEST=Build and boot to OS in Guybrush. Ensure that the secure counters
are defined successfully in TPM NVRAM.
Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The Alder Lake code currently supports the PCH-M and PCH-P types, which
have some differences (so far, only the amount of PCIe I/O). Mainboards
can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which
PCH type they use: select the option to choose PCH-M, do not select the
option to choose PCH-P. While this works, it can be confusing once more
PCH types are added.
Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards
have to explicitly choose a PCH type. Also, use this option to restrict
the PCH-P defaults for PCH-dependent settings to avoid unintended reuse
of the PCH-P defaults when adding a new PCH type. To make sure only one
PCH type is selected, add some preprocessor in `bootblock.h` to provoke
a build-time error if this requirement is not met. Kconfig doesn't seem
to have a mechanism to describe sets of mutually-exclusive bool options
that allows said options to be selected (a `choice` block doesn't allow
its elements to be selected). Finally, adapt the ADL boards accordingly.
Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch drops unnecessary `pmc_ipc.c` from Makefile as this
file is getting included upon CONFIG_PMC_IPC_ACPI_INTERFACE selection.
Change-Id: Ie66f0833daf033ec16210221610508f9fbb1e6c7
Signed-off-by: Subrata Banik <subi.banik@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Despite Stoneyridge being one only SoC in soc/amd that uses the first
generation of the PSP mailblox interface, this code is common for all
SoCs that use the first PSP mailbox interface generation, so move it to
the common PSP generation 1 code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59701
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This part was copied from Picasso but Cezanne has some more bits used so
add the definitions now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Both SPI_ROM_BIOS_SEMAPHORE and SPI_ROM_EC_SEMAPHORE bits in the
LPC_PCI_CONTROL are defined in the Stoneyridge BKDG #55072 Rev 3.04,
Raven1 and Picasso PPR #55570 Rev 3.18, Raven2 PPR #55772 Rev 3.08 and
Cezanne PPR #56569 Rev 3.03 which are all platforms that use this code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This patch replaces the use of the deprecated
cbfs_locate_file_in_region() API with the new
cbfs_unverified_area_map().
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If4855280d6d06cf1aa646fded916fd830b287b30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Adding USB addressmap for sc7280.
Use common USB driver for sc7280.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: Ib92b74c8035a8c0148a9aa48e7870b261b832a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add common USB driver for qualcomm soc sc7180 and sc7280.
This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7180 and
sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: I1013ded22855286220cfa747cb25418070fe85a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
When using 32 bit PCI accesses in lpc_enable_port80, we can use the
LPC_IO_OR_MEM_DECODE_ENABLE and DECODE_IO_PORT_ENABLE4 defines and don't
need to re-define bits with offsets from the beginning of the third byte
within this 32 bit register. This allows to drop the
LPC_IO_OR_MEM_DEC_EN_HIGH register definition which points to
LPC_IO_OR_MEM_DECODE_ENABLE + 2 and to drop the re-definitions of the
bit re-definitions with a different offset.
The code in lpc_enable_port80 was originally copied from sb/amd/agesa/
hudson/early_setup.c which might be sort-of a copy from what the AGESA
reference code does.
TEST=When commenting out SOC_AMD_COMMON_BLOCK_USE_ESPI in the Kconfig of
Mandolin and selecting AMD_LPC_DEBUG_CARD, all POST codes still get
shown on the POST code LED display when this patch is applied.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I001bb1c2ccf99e36d4fbd73d3bf96b78ddb87d67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This function is unused and none of the SoCs using this code has a
physical PCI interface any more, so drop this function.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia5c5a8ec29264a075fefe75038ef2a84684d6427
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
PSP_MAILBOX_BAR is defined as PCI_BASE_ADDRESS_4, so use it instead of
PCI_BASE_ADDRESS_4 in the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8658b674b9adea85dfc71d7036ccf3ae17464b58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
PSPV2_STATUS_ERROR and PSPV2_STATUS_RECOVERY aren't used and the bit
definitions are also wrong, so drop those defines. For the PSP mailbox
interface version 2, struct pspv2_mbox is used to access the correct
status bits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8e2aadfde00e2f7b0f99b462b8e3d6954959a584
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The checking register will be cleared after EC resets, so we move
bustracker dump from ramstage to bootblock, before triggering EC reset.
TEST=bustracker shows status before watchdog resets
BUG=b:207743045
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
There will be no log in cbmem if we trigger ec reset on bootblock
stage. Therefore, call dcache_clean_all() before triggering ec
reset to flush cache to store logs on cbmem.
BUG=b:207743045
TEST=show logs on cbmem
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I1bd900beb4cc84f7121c5fb66907fa73b62517fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The patch enables cse_fw_sync() before DRAM initialization.
cse_fw_sync() sends HECI commands in order to set CSE's boot partition
and to trigger CSE firmware update.
As part of CSE firmware update, coreboot sends HMRPFO_ENABLE HECI
command. Since CSE supports the command after DRAM Initialization,
cse_fw_sync() is called after DRAM initialization.
Starting from CSE Litev16.0.15.1545, CSE support HMRFPO_ENABLE command
before DRAM initialization too. So, cse_fw_sync() is called before DRAM
initialization.
BUG=b:175516533
TEST=Dependency with CSE Litev16.0.15.1545 integration
Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55364
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch renames X86_AMD_INIT_SIPI Kconfig to leverage
the same logic (to skip 2nd SIPI and reduce delay between
INIT and SIPI while perform AP initialization) even on
newer Intel platform.
Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56651
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Raise little CPU to 2GHz at romstage.
TEST=check little core cpu frequency is 2GHz
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
