Commit Graph

35844 Commits

Author SHA1 Message Date
Elyes HAOUAS ad619a2473 src/drivers/usb/ehci_debug.c: Add missing include
Replace unused <stddef.h> with missing <stdint.h>. This is needed for 'u64'.

Change-Id: Ie99c27bd6a7d982bba9a93342f3e3b83a1c09e8d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-14 16:11:27 +00:00
Elyes HAOUAS 854782330c src: Remove unused 'include <stdint.h>
Found using:
diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<'

Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14 16:11:10 +00:00
Elyes HAOUAS 5320f5387e src/acpi/soundwire.c: Add missing <stddef.h>
size_t needs <stddef.h>. Replace unused <stdint.h> with <stddef.h>.

Change-Id: Ib9ab5555adeeddd9eea7a93dbb166d8479eca42e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43340
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14 16:10:43 +00:00
Elyes HAOUAS 225be5f7ee src: Remove unused 'include <types.h>'
Files found using:
diff <(git grep -l '#include <types.h>' -- src/) <(git grep -l 'BIT(\|size_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\|MAYBE_STATIC_NONZERO\|zeroptr\|int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|bool\|true\|false\|cb_err\|CB_SUCCESS\|CB_ERR\|CB_ERR_ARG\|CB_CMOS_\|CB_KBD_\|CB_I2C_\|cb_err_t\|DIV_ROUND_CLOSEST\|container_of\|__unused\|alloca(\|ARRAY_SIZE\|ALIGN\|ALIGN_UP\|ALIGN_DOWN\|IS_ALIGNED\|__CMP_UNSAFE\|MIN_UNSAFE\|MAX_UNSAFE\|__CMP_SAFE\|__CMP\|MIN(\|MAX(\|ABS(\|IS_POWER_OF_2\|POWER_OF_2\|DIV_ROUND_UP\|SWAP(\|KiB\|MiB\|GiB\|KHz\|MHz\|GHz\|offsetof(\|check_member\|member_size' -- src/)|grep -v vendor |grep '<'

Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41677
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14 16:10:17 +00:00
Elyes HAOUAS 5a8e072020 src: Remove unused 'include <string.h>'
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/) |grep -v vendorcode |grep '<'

Change-Id: I12802d0a6254b2fa39d59f485008bb2012f7b32d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41913
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14 16:09:44 +00:00
Rob Barnes f0d1c9a423 mb/google/zork: Add USB to baseboard devicetree
Add USB ports, USB user-facing camera and USB bluetooth to devicetree.
USB ports 4 and 5 are duplicated for picasso and dali.

BUG=b:158096224
TEST=Boot Trembyle and Dalboz, Dump acpi tables

Change-Id: Icf8628d91e27a3afdc5fd67a53b44089c809da87
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-14 16:09:01 +00:00
Rob Barnes ddeba9f196 mb/google/zork: Split devicetree between baseboards
Split zork baseboard devicetree between dalboz and trembyle.
The devicetree is simply duplicated, no other changes in this commit.

BUG=b:158096224
TEST=Build coreboot for zork

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5b26770790092c69db9567fa4337edd21a6ed809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-14 16:08:43 +00:00
Wisley Chen 51c6d4429c mb/google/hatch: Set SA slow slew rate to 1/2 for jinlon/dratini
Screen flickered on VT2 on some devices  after idle a period of time.

Remove SSR (1/8) setting for SA to default SSR (1/2), screen flicking
issue disappeared, and didn't affect acoustic noise much.

Because CB:38212 (commit eae254e) caused this issue.

BUG=b:160754994
TEST=build dratini, observe that screen flick issue disapppered

Change-Id: I9e81c2f15dd6babfa360eee213fc4ab6310c7455
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43284
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14 16:08:06 +00:00
Shreesh Chhabbi 370868766b mainboard/volteer: Enable SaGv for volteer2, delbin & voxel
SaGv needs to be enabled for only QS. On ES2, we are seeing system
instability.

BUG=b:159198381
TEST=Tested for boot. Power and performance tests were run with
volteer2 with qs setup. System showed stability.
Tested for boot stability on on delbin.

Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-14 16:07:25 +00:00
xuxinxiong 8cf43f6c98 mb/google/kukui: Add new configs 'Cerise' and 'Stern'
New boards introduced to Kukui family.

BUG=b:160854400
TEST=make # select Cerise and Stern
BRANCH=kukui

Change-Id: I5841d57c0891d5191dd96097b90da889855b56c8
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43320
Reviewed-by: Zhaoyou Hong <hongzhaoyou@huaqin.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14 16:05:49 +00:00
Angel Pons 30392ae396 sb/intel/lynxpoint: Define SerialIO devfns
This reduces differences with Broadwell.

Tested with BUILD_TIMELESS=1, Google Panther remains identical.

Change-Id: I81c34fd03a176d0575f2fbd254052d90f2b38487
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-07-14 16:04:56 +00:00
Nick Vaccaro 20cf396c96 mb/google/volteer: config QS silicon devices for CSE LITE
Configure volteer2 and delbin, the two variants currently using
preQS or QS silicon, to use CSE Lite.

BUG=b:158140797
TEST=cd to volteer's asset_generation folder, execute
"./gen_all_variant_images.sh" and verify that all variant
images are produced.

Change-Id: I5e444529b090d82094b9da0df2648ea4cdb2888e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-14 04:52:51 +00:00
Rob Barnes 009a23d5c8 soc/amd/picasso: supply SMBIOS type 17
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in
cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects
from cbmem to build SMBIOS type 17 tables.

BUG=b:148277751,b:160947978
TEST=dmidecode -t 17
BRANCH=none

Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-13 21:39:05 +00:00
Furquan Shaikh 33d9eeae5f mb/google/zork: Fix check for variant_uses_v3_schematics()
CB:43224 ("mb/google/zork: Add helpers for v3 schematics and wifi
power enable") added helper functions for determining if a board uses
v3 schematics. However, it introduced a regression by adding a wrong
check for variant_uses_v3_schematics() in variant_audio_update(). This
change fixes the check to ensure that dmic_gpio is updated when
variant is not using v3 schematics.

BUG=b:161141258,b:161128964
TEST=Verified on trembyle that trackpad works again (it was broken
because of the regression).

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I0e6ad844f68cface7b545f1547bd94470c30dde4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43415
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-13 21:23:50 +00:00
Kane Chen 411a6ab703 mb/google/zork: Create Woomax variant
Create the woomax variant of the zork reference board by copying
the template(coreboot-zork/util/mainboard/google/trembyle)
files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.1).

BUG=b:158343602
BRANCH=None
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I0bb8ce1851f4064d24e48fd8957e2f9fe1e80b53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-13 19:08:51 +00:00
Angel Pons 26f25d7105 mb/google/beltino/bootblock.c: Drop unused include
Change-Id: I2994b8bf5521b539a9f3585a3221452b1807837a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-12 23:21:57 +00:00
Martin Roth 637f941f66 mb/google/zork: Update SPI mode to 100MHz, 1-2-2
Change SPI speed from 66MHz, mode 1-1-2 to 100MHz mode 1-2-2.

“1-2-2" means command, address and data are transmitted
through 1 wire, 2 wire and 2 wire, respectively.

BUG=b:160603142
TEST=Boot on trembyle, verify register settings.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I14f96e3c085126c70e64ef3a3f5b7b54ce6cbffe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43306
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:44:26 +00:00
Mate Kukri 45b51e0180 soc/intel/baytrail: Add dedicated devices for MMC and MMC 4.5 controller
- Correctly detect device 17h as the MMC 4.5 controller
- Support detection of the "old" MMC controller at device 10h

Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I9f0007b1cf01df09f775c088397c3b9c846908c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-12 19:44:02 +00:00
Maxim Polyakov 355d1c9870 soc/intel/gpio: Convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE()
As with other macros, convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE() to
make the code in gpio_defs.h cleaner.

Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard
does not change.

Change-Id: Iadc9c4b3c96ae04c56d060cb060737a8eba7f165
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41034
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:43:38 +00:00
Maxim Polyakov c0dfa7596b soc/intel/gpio: Convert PAD_CFG0_RX_POL_* to PAD_RX_POL()
Converts PAD_CFG0_RX_POL_* macros to PAD_RX_POL() to make the code
cleaner and reduce the length of the macro.

Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard
does not change.

Change-Id: I09a048fd38ccb994f53c8829c549bc2b368fa546
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41033
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:43:23 +00:00
Maxim Polyakov 3787b67d41 intel/gpio: Convert PAD_CFG0_TRIG_* to PAD_TRIG()
Converts PAD_CFG0_TRIG_ * macros to PAD_TRIG() to make the code cleaner
and reduce the length of the macro, which is often used.

Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 & T10-TNI carrierboard
does not change.

Change-Id: I9e1b4118fd6c6f0d58ee38a743aa8c27535f0dd9
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41032
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:43:00 +00:00
John Zhao 025af31423 mb/intel/tglrvp: Add SMI handler for tglrvp
This change adds SMI handler for SCI, S3/S5 wake up and LID closed
events on tglrvp platform.

TEST=Built image and booted to kernel.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I0bc72f164e86f1921e0cad39f9749e8e3be0778f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-12 19:41:47 +00:00
John Zhao 35a30c5526 mb/intel/tglrvp: Add EC_HOST_EVENT_USB_MUX for tglrvp
This change allows EC to change state of host-controlled USB MUX.

TEST=Built image and booted to kernel.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia7c331157b1b4039e42c373f5b130a66f7594458
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42955
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:41:39 +00:00
Selma BENSAID a3a8ff97fb payloads/external: fix depthcharge build from source
Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Change-Id: I17ae7450a9641268fe392bed0f24846abc8e6f56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43203
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:41:24 +00:00
John Zhao 8f5fbb0f26 superio/nuvoton: Avoid NULL pointer dereference
Coverity detects dereferencing a pointer that might be "NULL" when
calling acpigen_write_scope. Add sanity check for scope to prevent
NULL pointer dereference.

Found-by: Coverity CID 1420207

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Icc253c63aadef1c0ecb116a38b608f64f80abc79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-12 19:40:53 +00:00
Christian Walter 4a924dce99 mb/prodrive/hermes: Deselect PCIEXP_CLK_PM and L1_SUB_STATE
Set default of PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE to n as this breaks
booting Windows with a PCIE NVIDIA.

Change-Id: Ie8768b91c27c4159f9b3c7f94699134a82decea0
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-07-12 19:40:33 +00:00
Christian Walter 18d315910a soc/intel/common/block/pcie: Select ASPM on mainboard basis
Current the common soc code automatically selects PCIEXP_CLK_PM and
PCIEXP_L1_SUB_STATE which breaks booting Windows with a PCIE NVIDIA
graphics card attached on mainboards that do not have a CLKREQ# signal.

This is commonly used on server and workstations boards where the
additional power savings of L1 substate are not required.

Make the PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE default y but do not
select it anymore by the soc code, thus we can disable it in the
mainboard code.

Tested on CFL with Windows 10.

Change-Id: I025e13d6d8183256647e4c034e31bafa235f7eb7
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41696
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:40:19 +00:00
Tim Wawrzynczak 07ac2ec021 mb/google/volteer: Convert static ASL files to new DPTF implementation
This patch converts the current DPTF policies from static ASL files into
the new SSDT-based DPTF implementation. All settings are intended to be
copied exactly.

Change-Id: I964c53afbd503d47a07b982672425f0e7a986a3f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41895
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:39:43 +00:00
Karthikeyan Ramasubramanian c34079cea0 mb/google/dedede: Add ability to provide override GPIO table
For variants with slightly different GPIO configuration, add support to
pass an override GPIO configuration table.

BUG=None
TEST=Build and boot the waddledee mainboard.

Change-Id: I2f1c6dc2ea5499bff96a471c4461339ef01ee19a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-12 19:39:24 +00:00
Johnny Lin c8d8777750 mb/ocp/deltalake: Pull POST complete pin low before booting payload
Delta Lake uses GPIO pin GPP_B20 for POST complete event,
BIOS needs to pull this pin low for BIC (Bridge IC) to start
reading sensors.

Tested=On Delta Lake oBMC, bic-util slotx --get_gpio to confirm
the pin is low.

Change-Id: I7e05f8a7caead8ee0632af4ff60ccd8b2412b3dd
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-12 19:39:05 +00:00
Anna Karas 86acc04d28 tests: Improve test_skip_atoi() in /lib/string-test test case
Confirm that the pointer is updated to point behind the parsed number.

Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: If75a51056229904612c6a9ea20db4182d1935009
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-12 19:38:39 +00:00
Anna Karas f7cd0d5a05 tests: Move the console stubs to a dedicated directory
Move the console functions definitions out from lib/b64_decode code to
a dedicated directory.

Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: I22a6a592f0d4d509f19920f4ad2b18e8ed83a03e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-12 19:38:28 +00:00
Brandon Breitenstein 478d47f777 mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4
This change enables PCIEXP_HOTPLUG to support resource allocation for
TCSS TBT/USB4.

BUG=b:149186922

Change-Id: Id3066204c8a780ade251c7be4052a60a861e43db
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-07-12 19:38:03 +00:00
Shaunak Saha dbf6f688aa mb/intel/tglrvp: Enable recovery in TGL RVP
Share "EC in RW" GPIO with depthcharge. Also we define the CONFIGS
needed CHROME, CHROME_EC and use the chrome lid and recovery.

BUG=None
BRANCH=None
TEST=Build and boot TGL RVP. Check recovery works with
crossystem recovery_request.

Change-Id: I1e88200e3f8418e5b0ab39ac65ed1b3545ce111e
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-07-12 19:37:50 +00:00
Jonathan Zhang 1866a8cba4 soc/intel/xeon_sp/cpx: use HOB_TYPE_GUID_EXTENSION to interpret platform HOBs
Platform HOBs (in particular IIO_UDS and MemoryMap HOBs) are of HOB type
HOB_TYPE_GUID_EXTENSION, therefore they do not have resource structure.

Remove the erroneous code related to resource structure.

Remove unnecessary function prototypes from header files, and define them
as static in hob_display.c.

Since we have the HOB pointer, there is not need to search HOB by GUID.
Remove unnecessary calling of fsp_find_extension_hob_by_guid().

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: Ib99bce39e6eb2aeb95242dfba36774653bbe91fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43335
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:37:34 +00:00
Wisley Chen 8b85e8152b mb/google/dedede/var/drawcia: support internal usb camera
BUG=b:160741778
TEST=build drawcia, and check camera can be regconized

Change-Id: I67bee9773b53451653abd76088d1d4062fe3da8f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42929
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:37:20 +00:00
Wisley Chen a339c3600f mb/google/dedede/var/drawcia:Add audio support (ALC5682 codec, MX98360A spk amp)
Select the drivers for ALC5682 codec and MX98360A spk amp

BUG=b:158202026
TEST=FW_NAME=drawcia emerge-dedede coreboot chromeos-bootimage

Change-Id: If271f11f10a85ade6f61ff8c25bfafeb67a69af6
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-12 19:37:08 +00:00
Aaron Durbin c676ecaecf vc/amd/fsp/picasso: add DMI data structure definitions
Provide the data structures for parsing SPD information
supplied by FSP.

BUG=b:160947978

Change-Id: If847646625448547599018a823712d5c14e4bd76
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43350
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:36:54 +00:00
Jingle Hsu e07ea4cd38 soc/intel/xeon_sp: Add RTC failure checking
Add a weak function mainboard_rtc_failed() for mainboard customization.

Check RTC_PWR_STS bit for RTC battery removal or CMOS clear jumper
triggered event.

Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Change-Id: Ic6da84277e71a5c51dfa4d97d5d0c0184478e8f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-12 19:36:42 +00:00
Johnny Lin 145a76182c mb/ocp/deltalake: Use VPD data to configure FSP UPD at romstage
Read VPD variable 'fsp_log_enable' to decide enabling FSP log or not.
With VPD_RW_THEN_RO, VPD_RW takes precedence over VPD_RO, and
would be set to enabled if both places cannot find it.

Tested=On OCP Delta Lake, use vpd to create and set fsp_log_enable
and verified the results are expected.

Change-Id: I0b3463acedd90e8e17f7e4eedc2fab63644f87e1
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: insomniac <insomniac@slackware.it>
2020-07-12 19:36:18 +00:00
Jonathan Zhang 0ccb3828bc vendocode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww28 release and adapt soc
CPX-SP FSP ww28 release adds UPDs to allow enablement of VT-d and VMX.
Also update IIO UDS HOB definition file accordingly.

Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG.
Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel
is that they will converge to use FSPM_CONFIG over time. So both will
co-exist for some time. Today coreboot common code expects FSP_M_CONFIG.
Accomodate this situation in FspmUpd.h.

The CPX-SP soc code is updated accordingly.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: If6d0a041eaad9eb2f811e74d219fff1cc38e95a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-12 19:34:28 +00:00
Tim Wawrzynczak bb50c67227 soc/intel/tigerlake: Move tco_configure to bootblock
On ChromeOS systems with a serial-enabled BIOS and vboot writing a new
firmware image to the Chrome EC, it was possible for the TCO watchdog
timer to trip 2 times before tco_configure() was called in romstage.
This caused an extra reboot of the system (at a rather inopportune time)
and because the EC didn't perform a full reset, the system boots into
recovery mode.

This patch moves the call to tco_configure() for Tiger Lake from
romstage to bootblock, in order to make sure the TCO watchdog timer is
halted before vboot_sync_ec() runs in romstage. It should be harmless to
configure the TCO device earlier in the boot flow.

BUG=b:160272400
TEST=boot Volteer (to a non-recovery kernel!) with a freshly imaged EC

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iefdc2c861ab8b5fde7f736c04149be7de7b3ae0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43313
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:33:30 +00:00
Angel Pons 2e1f764429 sb/intel/common/acpi/irqlinks.asl: Add missing IRQs
IRQ 10 and IRQ 11 are valid for all southbridges using this code, as per
their respective datasheets. So, add them for the sake of completeness.

Change-Id: Ib4504861ed316a95b9735e0ed79f108f18071b3b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43158
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:32:15 +00:00
Angel Pons db5557972a mb/getac/p470: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: Ida12426c51313a7642b5c363e58a79d77b1b096b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-12 19:32:04 +00:00
Angel Pons f3de8859a8 mb/supermicro/x9scl: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I65fedfa7e8b2fbb72b3109a8790445e38909976a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-12 19:31:51 +00:00
Angel Pons f33ab7c30f arch/x86/mpspec.c: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I8280d29b9a7bc835c2cb7e3e3dfca70768672a5f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-12 19:31:21 +00:00
John Zhao 23d3ad0f64 mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4
This change enables s0ix for tglrvp up3 and up4 platform.

TEST=Built image and booted to kernel.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I657bee1d7ee120ae15ccb4a33f9eb2fcf5cca65a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42954
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:31:01 +00:00
Jamie Ryu ef079c86ea mb/intel/tglrvp: Enable CpuReplacementCheck
Enable CpuReplacementCheck for TGLRVP with a CPU socket.

Test=build and verified with tglrvp

Change-Id: I75b4a4609c172c341087077228e23c6d31a9e7e1
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-07-12 19:30:55 +00:00
John Zhao 6aedba2f13 soc/intel/tigerlake: Configure Type-C Input Output Manager(IOM) device
This adds Type-C Intel Input Output Manager(IOM) device with HID
INTC1072. It provides MMIO range from 0xfbc10000 with size 0x1600.
Intel Input Output Manager(IOM) kernel driver reads relevant
information such as Type-C port status (whether a device is connected
to a Type-C port or not) and the activity type on the Type-C ports
(such as USB, Display Port, Thunderbolt) using this memory resource.

BUG=b:156016218
TEST=Able to detect USB, TBT and USB4 on Volteer.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic733e831643bda6e052edf797ba0e6206eb4ddd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41762
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:29:59 +00:00
John Zhao 21aece8653 soc/intel/tigerlake: Add Type-C IOM base address and size macro
This adds Type-C IO Manageability engine base address and size.
Tigerlake EDS(#575681) section 3.4.3 describes host bridge
REGBAR(MCHBAR) + 7110h for IOM REGBAR with size 1600h. IOM has a
port ID 0xc1. MCHBAR is programmed with 0xfedc0000. IOM REGBAR is
determined from mmio (MCHBAR + 0x7110), which has value 0xfb000000.
IOM has base address 0xfbc10000 from IOM REGBAR + (0xc1 << 16).

BUG=🅱️156016218
TEST=Built and booted on Volteer.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41759
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12 19:29:51 +00:00