Commit Graph

41386 Commits

Author SHA1 Message Date
Eric Lai 87e27e1d0e mb/google/mancomb: Enable Chrome EC
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id1617be67bfc5d2f142358ae8a70c3e575a94c6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05 16:40:08 +00:00
Raul E Rangel b95f848766 soc/amd: Make espi_clear_decodes private
espi_setup already clears most of the controller registers. So this
change consolidates the clear logic into one spot.

This shouldn't result in a behavior change on Picasso. Picasso already
has the eSPI decodes clear on boot, so this change is a nop.

BUG=b:183524609
TEST=Boot guybrush to the OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 16:39:11 +00:00
Raul E Rangel 61ac1bc530 soc/amd: Make espi_configure_decodes private
This is only ever called after espi_setup.

55861 - AMD System Peripheral Bus Overview also says that io ranges
should be configured before enabling the BUS_MASTER bit.

BUG=b:183524609
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 16:38:23 +00:00
Seunghwan Kim c988d0516c mb/google/dedede/var/sasuke: Update DPTF parameters
Remove TSR2, use DPTF parameters from internal thermal team.

BUG=b:183749595
BRANCH=dedede
TEST=emerge-dedede coreboot

Change-Id: I3182b96bf36c8d07299fe435a29e6b8c0b8a6927
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-05 15:37:42 +00:00
Seunghwan Kim 6ffaf5a691 mb/google/dedede/var/sasuke: Configure I2C times for touchpad/audio
Configure I2C rise/fall time in device tree to ensure I2C CLK runs
accurately at I2C_SPEED_FAST (< 400 kHz).

Measured I2C frequency just as below after tuning:
I2C0(touchpad): 385 kHz
I2C4(audio): 380 kHz

BUG=b:180335053
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400kHz

Change-Id: Ic92ee0379456e80260a8026bc38ee41325dad6d2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-05 15:32:09 +00:00
Raul E Rangel 66c52ffb2b soc/amd/common/espi: Clear DNCMD_COMPLETE on completion
Tidy up the interrupt status. This will leave SLAVE0_INT_STS = 0.

BUG=b:183524609
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I950cfb81521e35758c120a482670cfdb924201d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52056
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 15:02:10 +00:00
Raul E Rangel b92383a8a5 soc/amd/common/espi: Reset eSPI registers to known state
This sets the eSPI registers to the reset values specified in the PPR.

On Cezanne, the PSP modifies these registers such that the eSPI
peripheral cannot send DEFER packets. This causes random bus errors.

These reset values are identical to what is currently used on Zork.

I didn't clear out ESPI_DECODE because it's currently being done by
cb:51749.

BUG=b:183524609
TEST=Boot guybrush to the OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 15:02:00 +00:00
Raul E Rangel 1d0e4930ba soc/amd/common/espi: Add missing eSPI register definitions
These are defined in the public Picasso PPR - 55570-B1 Rev 3.15.

BUG=b:183524609
TEST=Build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e601f767327e0a24a086146623af039388b2e7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 15:01:50 +00:00
Aaron Durbin a435c3e2ea mb/google/dedede: add lalala variant
The Lalala variant is a design that differs only
in replacing Cr50 with a discrete TPM part.

BUG=b:184151664

Change-Id: I2f7abb9637cd5a13ac896396781b19feb156c948
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
2021-04-05 14:31:15 +00:00
Aaron Durbin 7164ad74bf mb/google/dedede: add discrete TPM 2.0 configuration
There are forthcoming designs that will be utilizing
a discrete TPM 2.0 solution. Split the existing dedede
configuration options so future mainboard variants can
easily select the appropriate Kconfig option using the
newly introduced options:
- BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
- BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
The existing variants all select the former option,
BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 since all those
designs currently utilize Cr50.

BUG=b:184151664

Change-Id: I2bdb1ca4fd78cc0628256d49678ea042c55f6fba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52030
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 14:31:08 +00:00
Furquan Shaikh f7f715dff3 mb/google/brya: Enable south XHCI ports 1 and 2
FSP v2081 has a bug where it uses the information about south XHCI
ports to enable TCSS XHCI ports. This change works around this bug by
enabling south XHCI ports 1 and 2 in brya baseboard devicetree. brya0
already enables south XHCI port 1 in overridetree.cb, however, it is
still enabled in baseboard/devicetree in case more variants are added
to brya before FSP is fixed.

BUG=b:184324979
TEST=Verified that TCSS XHCI ports 1 and 2 are now enabled.

Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-05 14:15:31 +00:00
Angel Pons 5304ce108e nb/intel/sandybridge: Drop `pci_mmio_size`
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.

Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:16:43 +00:00
Angel Pons f2e8660fa2 sandybridge boards: Drop default `pci_mmio_size`
2 GiB is the default already.

Change-Id: I294460949659c97d4e19ad4e9d14f8c3566cca3f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52071
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:16:36 +00:00
Angel Pons e24f97c081 nb/intel/ironlake: Drop `pci_mmio_size`
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.

Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:16:22 +00:00
Angel Pons 83e319d6f5 device/dram/ddr3: Drop unused MRS helpers
These aren't used anywhere anymore.

Change-Id: I4cf2fc0d07a772886e90fba4f66591a7b0a40e6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05 13:03:58 +00:00
Angel Pons ae5e636b96 nb/intel/sandybridge: Rename `pdwm_mode` enum
The `pdwm` part was supposed to be an abbreviation of `power down`, but
it is neither self-explanatory nor properly-spelled. Rename the enum.

Change-Id: I7b83c71d4534b62e18ced04eebe6a65089e1d874
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05 13:03:24 +00:00
Angel Pons 623d75e828 spd.h: Remove unused definitions
These definitions are unused and not particularly useful. Drop them.

Change-Id: I40a824888701870b6713c1a16ab671c19b3770ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51900
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:02:59 +00:00
Angel Pons e97a66d371 nb/intel/i945/raminit.c: Replace `DIMM0`
Use the actual value as it is more informative.

Change-Id: Id3bd8ccdf79d1e3fdf97cda049f81271bb017ef7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05 13:02:41 +00:00
Angel Pons a60b42a26a nb/intel/i945: Refactor `dump_spd_registers` function
Use the mainboard-provided SPD map and skip unused addresses.

Change-Id: I2b5b71cff290343c1000d5613209049fa9724e3d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05 13:02:27 +00:00
Angel Pons 6c6e049282 device/dram/ddr4.h: Align with DDR3 and DDR2
Drop unnecessary typedefs and rename DDR4-specific definitions to avoid
name clashes, as done for DDR3 in earlier commits. This allows including
and using both DDR3 and DDR4 headers in the same compilation unit.

Change-Id: I17f1cd88f83251ec23e9783a617f4d2ed41b07f0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51898
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:02:00 +00:00
Angel Pons acd30e9017 include/spd_ddr2.h: Remove unused and redundant file
DDR2-related definitions exist in `device/dram/ddr2` already.

Change-Id: I509f728138327d8a0a88e4503235f05bf14aed20
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51897
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:01:51 +00:00
Angel Pons 18571389d5 device/dram/ddr3: Rename DDR3 SPD memory types
To avoid name clashes with definitions for other DRAM generations,
rename the enum type and values to contain `ddr3` or `DDR3`.

Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:01:37 +00:00
Angel Pons afb3d7e7ec device/dram/ddr3: Get rid of useless typedefs
These typedefs are not necessary. Remove them, and rename some elements
to avoid any confusion with other DRAM generations, such as DDR4.

Change-Id: Ibe40f33372358262c540e371f7866b06a4ac842a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51895
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:01:29 +00:00
Raul E Rangel 4774012515 soc/amd/common/espi: Add ESPI_ prefix to SLAVE0_INT_EN
This matches the other register definitions.

BUG=b:183524609
TEST=Build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0ed92add633f294f92c6a0dde32851d01b10db3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 00:44:43 +00:00
Martin Roth f3314c20de soc/amd/cezanne: Clear eSPI ranges before configuring eSPI
The Cezanne PSP configures the eSPI with the assumption that it's a
majolica, setting up both the serial port and the majolica EC IO decode
ranges.  Since guybrush is NOT a majolica, this doesn't work very well
there.  Clearing the decode ranges allows the guybrush platform to set
the decode ranges needed for its EC.

BUG=b:183524609
TEST=Set up eSPI on Guybrush

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I77cfb948cb9ae6d1cf001bd9e66cede8d93f50b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 00:44:19 +00:00
Martin Roth 011bf13715 soc/amd/common: Add func to clear eSPI IO & memory decode ranges
Previously, the eSPI code would only add to existing decode ranges, and
there wasn't any way to clear ranges.  This clears all the ranges so
the eSPI configuration can start fresh.

BUG=b:183207262, b:183974365
TEST=Verify on Guybrush

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic4e67c40d34915505bdd5b431a064d2c7b6bbc70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 00:43:55 +00:00
Angel Pons da335abfe7 soc/ti/am335x/mmc.c: Fix memset length argument
The sizeof() operator was being applied to a pointer-to-struct type.
Correct this, so that the entire struct space gets cleared.

Change-Id: Ieab3aaa2d07a928f27004b94132377d5dae935c0
Found-by: Coverity CID 1451732
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52054
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Sam Lewis <sam.vr.lewis@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-04 09:58:26 +00:00
Michael Niewöhner 0887fc4dbc docs/mb/supermicro: add SUM tool for flashing with disabled ME
Change-Id: I08543c0908a6cb4ef9fb46d0eb3a7aa481fb95d9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49887
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-03 20:25:44 +00:00
Julius Werner 0972871a23 coreboot_tables: Print strapping IDs when adding them to coreboot table
These used to be printed before CB:46605. Having them in the logs can be
a huge timesaver when debugging logs sent to you by other people
(especially from systems that don't boot all the way). Let's add them
back.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifdbfdd29d25a0937c27113ace776f7aec231a57d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-02 21:23:13 +00:00
John Su 45e103ca87 mb/google/zork/vilboz: Fix audio test failure on LTE SKU
Use board id to switch acp_i2s_use_external_48mhz_osc enable.

BUG=b:181720406
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I085c39accd82bf72e4ebbc0394382ed4a7d4e901
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-04-02 20:52:57 +00:00
Tim Wawrzynczak a10cc8a98b mb/intel/adlrvp: Update VBT filenames
These files were just renamed to put `adlrvp` in between `vbt`
and the memory technology type.

Change-Id: Icefbac462d0ec9c660541e9cf44686d6dcf82dfd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52032
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-02 20:47:28 +00:00
Karthikeyan Ramasubramanian 1e36dc078e mb/google/guybrush: Enable early EC Software Sync
BUG=None
TEST=Build and boot to OS in Guybrush. Ensure that the EC Software Sync
is complete.

Change-Id: Id8655b6f805e14ce3cb71777c1cc175f45841fcc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-02 16:25:11 +00:00
Karthikeyan Ramasubramanian ad7c33abd2 soc/amd/cezanne: Add support to perform early EC sync
Ideally we would like to perform EC Software Sync in payload. But with
the hardware requirement (EC_IN_RW) and firmware requirement (TPM
command to get EC execution environment) not met yet, adding the support
to perform early EC Software sync. With EFS2 enabled, this will also
help cr50 to set the boot mode as NORMAL instead of NO_BOOT.

BUG=None
TEST=Build and Boot to OS in Guybrush. Ensure that the EC software sync
is successfully complete.
CBFS: Found 'ecrw.hash' @0x50400 size 0x20 in mcache @0x020171ec
VB2:check_ec_hash() Hexp RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:check_ec_hash()            Hmir: 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
<snip>
VB2:check_ec_hash() Heff RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:sync_ec() select_rw=RW(active)

Change-Id: I820e651c6b22a833fef6f17a4ceb5a8cfb6f1616
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-02 16:25:03 +00:00
Karthikeyan Ramasubramanian 0f4191204b mb/google/guybrush: Add Elan Touchpad configuration
Enable Touchpad by configuring the enable GPIO to logic high. Add
touchpad configuration for ELAN touchpad.

BUG=b:182207444
TEST=Build and boot to OS in Guybrush. Ensure that the trackpad events
are detected using evtest.

Change-Id: Ib47fbb33f2b181eb85f6ded98a5b0ce08fbc7b64
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51962
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-02 16:16:14 +00:00
Boris Mittelberg 9965228c66 mainboard/google/brya: Disable touchpad as S3 wake source
This change disables touchpad interrupt, as it sends spurious wake signal
via GPP_F14 and immediately wakes the system from S3. It happens because
touchpad's power is gated by deassertion of PLTRST#. The behaviour for
S0ix is unchanged.

BUG=183738135
TEST=manually

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: Ia7d282f38d205a94cc43eaa1832729f4606437c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51831
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-02 16:10:34 +00:00
Boris Mittelberg 6c2f80c4a2 mainboard/google/brya: Enable tight timestamp
This change exposes the PCH_INT_ODL line in GPP_F17 as interrupt resource for
CREC device

BUG=none
TEST=manual test

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I0c05160cb7894b5f7beee93a0c93776f973eae56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-02 16:10:27 +00:00
Boris Mittelberg 65fce098e3 mb/google/brya: change reset signal for GPP_F17 from PLTRST to DEEP
PCH_INT_ODL (GPP_F17) is used to wake AP from S3, however it was configured
to reset state on PLT reset assertion. This change reconfigures the pad
using DEEP instead of PLTRST to retain pad configuration across S3.

BUG=b:178545523
TEST=manual: verified that asserting PCH_INT_ODL wakes system and the wake
source is GPP_F17

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I8df5dafedabc7b6af74c39621f0e1eb7019a9a17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-02 16:10:20 +00:00
Angel Pons 07ccc8d9cd nb/intel/pineview: Correct COMP register write
Reference code does an and-or operation with zero as or-value, reading
and writing to the same address. The accessed register is 32-bit, and
reference code programs bits 22, 21, 20, 16 to zero. However, coreboot
code reads the value from bits 7..0 instead. Correct this.

Change-Id: I33bf268449c2f799321be81a02bbccff855ee1fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-02 14:34:23 +00:00
Bill XIE b77f01642c mb/hp/snb_ivb_laptops: Remove undefined variable in cmos.default
There is no "volume" defined in cmos.layout now, so removing "volume="
from cmos.default, otherwise building will fail with
CONFIG_USE_OPTION_TABLE set.

Change-Id: I1d6bb68fb927882ddcc052b432bb34b42c58eac7
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Iru Cai (vimacs) <mytbk920423@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-02 08:08:08 +00:00
Julius Werner ffa83fc7f8 google/trogdor: Don't build for rev0 by default
We've mostly stopped using Trogdor-rev0 now and are starting to bring up
rev2 instead. Therefore, the default revisions this builds for should be
the newer ones.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie433ebb2a03fb1636b5012b4a0567ba6f982579d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52007
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-01 22:23:36 +00:00
Kevin Chiu d90f8ac741 google/grunt: Add ALC5682 ACPI I2S machine driver
The is used for AMD Grunt board which uses ALC5682 and MAX98357 codec.
kernel driver will need to retrieve MISC FCH memory resource for CLK
enabling per different CID/HID.

BUG=b:171755306
BRANCH=master
TEST=emerge-grunt coreboot

Change-Id: I5f29a2d784a9fc749fff61a9c96c0a487b71a2d7
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51659
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-01 19:21:02 +00:00
Tony Huang ebf380b566 mb/google/dedede/var/lantis: Configure Acoustic noise mitigation UPDs
Enable Acoustic noise mitigation for lantis and set slew rate to 1/4
which is calibrated value for the board. Other values like PreWake,
Rampup and RampDown are 0 by default.

BUG=b:183561593
BRANCH=dedede
TEST=EE verify acoustic noise test passes.

Change-Id: I5e5f24ed934910726c220678068d085b6ee2bcf6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51762
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-01 16:45:21 +00:00
Raul E Rangel cce7d826db mb/google/guybrush: Add IRQ numbers
BUG=b:183737011
TEST=cat /proc/interrupts and see i2c controllers and gpio controller
listed

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5b2f23b2c2a7c4cec198276814d80f545e85aa41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-01 15:40:56 +00:00
Raul E Rangel e925af29d6 soc/amd/cezanne: Enable GENERIC_GPIO_LIB
Needed so we write the correct resource into the ACPI tables.

BUG=b:183737011
TEST=Boot OS and see GPIO devices working

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2ba4349e0ed500912db40aa6ef9b649046f4358f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51961
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-01 15:40:47 +00:00
Raul E Rangel 32fc4e350b soc/amd/cezanne: Add device tree support for I2C
This allows the cr50 on guybrush to show up in ACPI.

BUG=b:183737011
TEST=Boot OS and see I2C devices initialized

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifb5679b7bbefbf753217981874bb1bdaef35f6db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51958
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-01 15:40:36 +00:00
Raul E Rangel f63f2f291b mb/google/guybrush: Enable VBOOT_LID_SWITCH
Needed so get_lid_switch will actually call the EC. Otherwise it
returns -1.

BUG=b:183524609
TEST=Depthcharge no longer halts complaining that coreboot didn't sample
the pin

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4639b3713d726192e251dcffa14381dd92518fa2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-31 21:14:25 +00:00
Raul E Rangel 6ef0e80bf4 mb/google/guybrush: Switch eSPI to 16 MHz
It looks like we are having SI issues on eSPI at 33 MHz. Switching to 16
MHz makes everything a lot more stable.

BUG=b:183524609
TEST=Boot to OS and run `ectool version` 1000 times and see no problems.
Before with 33 MHz there was an error every few cycles.
declare -i i=0; while ectool version; do i+=1; echo "$i"; sleep .11; done; echo "Finished: $i"

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ab515629703a157c1d1ac6adcf5cf379e80f8ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-03-31 21:14:13 +00:00
Raul E Rangel a7659ebe4e soc/amd/common/block/graphics: Don't add VBIOS to cbmem when using GOP
pci_rom_ssdt reloads the oprom from cbfs. It then places it into cbmem
and writes the offsets as the ROM ACPI node. The GOP driver modifies the
VBIOS so we don't want to reread from cbfs. When using GOP we also pass
the offsets with the VFCT table.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaf53e750564f1f0e115cd354790da62e672d74b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-31 21:12:36 +00:00
Felix Held 3920bc9626 soc/amd/picasso/acpi: pass correct enum to acpigen_write_CSD_package
The coordtype parameter of acpigen_write_CSD_package expects a CSD_coord
enum value, but HW_ALL that got passed as parameter is a PSD_coord enum
value, so replace that with the correct CSD_HW_ALL enum value.

TEST=Timeless build results in identical binary for Mandolin.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Found-by: Paul Menzel <pmenzel@molgen.mpg.de>
Change-Id: I90b19345b8dc6d386b6acfa81c6c072dcd6981ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-31 21:06:33 +00:00
Chris Wang 3e343559e2 mb/google/zork/vilboz: set the eDP phy overriden for WWAN SKU
Move the eDP phy overridden to variant for WWAN SKU.

BUG=b:171269338
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I0400e8f78b152f260c632fba3cfa43aeca2f6776
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-31 14:36:08 +00:00