Enable caching of memory training data for recovery as well as normal
mode. We had HAS_RECOVERY_MRC_CACHE selected in the sc7280 Kconfig,
but never allocated a RECOVERY_MRC_CACHE in the herobrine fmap so it
never worked. Adding RECOVERY_MRC_CACHE and also removing
RO_DDR_TRAINING, RO_LIMITS_CFG, RW_LIMITS_CFG entries which have been
deprecated.
BUG=b:236995289
BRANCH=None
TEST=run dut-control power_state:rec twice and make sure that
DDR training doesn't run on the second boot.
Change-Id: I39ac7eca4ae94075874324b13c69eef59522e3c5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Having PTT means mocking secdata, so saving/reading the hash always
succeeds, but there is no data stored/read from/to TPM. The code
comparing MRC hashes did not care if secdata mocking was enabled
and failed during hash comparison with invalid data. This broke the
fastboot even if the MRC cache data was filled and correctly
checksummed. If mocking is enabled simply fallback to checksum
computing to proceed with fastboot.
TEST=Boot MSI PRO Z690-A WIFI DDR4 in fastboot mode with PTT and vboot
enabled.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic0cf04b129fe1c5e94cd8a803bb21aa350c3f8da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
With CB:65012, google_chromeec_vbnv_context() is no longer used. Remove
it from the codebase.
BUG=b:178689388
TEST=./util/abuild/abuild -t GOOGLE_STOUT -a -x
Change-Id: I717f600f0f73c3ca932b6a442a9d5b90c35c8f3b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We have clarified the powerdown sequence with Nvidia, and the EEs have
come up with this modified sequence which still meets the requirements
from the hardware design guide.
BUG=b:233959099
TEST=Verified by ODM and EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I37715165ab488f994c825fb9ff532ebf8d7f4cb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
These changes made my crude pattern matching work with
coccinelle simpler.
Change-Id: I83f3ef38b8663640594b4d726838f7a6f96a58a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Commit 0cc56a2848 (nb/intel/gm45/dsdt: Fix number of PCI busses) derives
the maximum PCI bus number at runtime. However, IASL complains about the
initial 0 in the resource template, which rendered the PB00 definition
self-contradictory at build time (maximum was lower than minimum +
length - 1).
Let's return to the old default values (min: 0, max: 255, length: 256)
and adapt max and length at runtime. Also fix some surrounding whites-
pace.
NB. The issue wasn't detected before merging commit 0cc56a2848 because
of broken IASL versions that can't count errors.
Change-Id: I359d357f276feda8fe04383080d51dc492c3f2e8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64347
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Stefan Ott <coreboot@desire.ch>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Return the correct processor family code for smbios per System
Management BIOS (SMBIOS) Reference Specification DSP0134 revision 3.5.0.
BUG=b:234409052
TEST=Boot chausie to chromeos and verify "dmidecode -t processor"
outputs the correct processor family.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I617ce3e23f4b28a197034756d285339595d3b53b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65364
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for osiris board. Please refer Intel doc#723158 for
more information.
BUG=None
TEST=Verify the build for osiris board
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia30a7b915df14c91a2526dca3e374436da286b7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
The tutorial documents were updated from the wiki very early in the
transition to markdown, and the style has changed over time. This
updates the markdown style to match documents that are being created
now.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I619c04f420042f530335482c30070436f9190865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The previous two patches removed all of the soc/Kconfig files, so there
is nothing to include anymore. Get rid of the 'source' command that
includes them.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I95067c4702ef25a8a6db4d480c089f06986ce9b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65329
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most of the src/soc/Kconfig files are only there for AMD and Intel to
load the main SoC Kconfig files before any common files. That can be
done in src/Kconfig instead. Moving the loads to the lower level allows
the removal of all but the Intel soc/Kconfig file, which can be removed
in a follow-on patch.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5061191fe23e0b7c745e90874bd7b390806bbcfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Clean up Makefile.inc by sorting entries and moving common entries to
all-y. In this way it is more clear to know what drivers have been
involved in each stage and the hardware differences between each SoC.
BUG=none
TEST=emerge-corsola coreboot
TEST=emerge-asurada coreboot
TEST=emerge-cherry coreboot
Change-Id: Idfc7de36ebf36650f7c6bd1584ef77e2a540cde9
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65315
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `send` and `recv` API functions currently print error messages
if a timeout occurs while polling the EC, but they perform the I/O
transaction regardless. This can put the EC in a bad state or
otherwise invoke undefined hardware behavior.
Most callers ignore the return value currently, but for callers
which do not, we should make sure our behavior is correct.
Signed-off-by: Abel Briggs <abelbriggs1@hotmail.com>
Change-Id: Ifb87dd1ac869807fd08463bd8fef36d0389b325e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64350
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust sensor trigger point and fan duty according to thermal team
tuning results.
BRANCH=brya
BUG=b:215033682
TEST=Built and tested on taniks board
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I8135684d471fdcfdbbe2f1bc5455902d56bb71de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kano board. Please refer Intel doc#723158 for
more information.
BUG=None
TEST=Verify the build for volmar board
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I4d12f7214a306ded54b4536a27fe0fb7f3c33b8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This CL fixes my previous CL (commit ca741055e)
which introduced a couple of issues found by Coverity (see below).
The Coverity explanation is: "Potentially overflowing expression "size_field * 1048576U" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned)."
*** CID 1490122: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
/src/soc/intel/alderlake/systemagent.c: 305 in get_dpr_size()
*** CID 1490121: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
/src/soc/intel/alderlake/systemagent.c: 254 in get_dsm_size()
BUG=b:149830546
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage' builds correctly.
Tested on an Anahera device which successfully boots to ChromeOS
with kernel version 5.10.109-15688-g857e654d1705.
Change-Id: Ib2d66ad24a5ad67b51036ad376a6938f698134c3
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65212
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fixes an issue introduced with commit ca741055e
(soc/intel/adl: Add missing claimed memory regions) where PRMRR base
should be read using MSR 0x2a0 and mask from MSR 0x1f5 instead
System Agent PCI configuration space.
With this change, coreboot is able to read PRMRR base when the
PRMRR size > 0.
TEST=Able to read PRMRR base MSR 0x2a0 in proper with this CL.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3770b1a92dbd2552cf1b9764522c9cac9f29c13c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
This patch adds a new mainboard variant called mc_apl7 which is based
on mc_apl4. So far only the names have been adjusted with no further
changes. Following commits will introduce the needed changes for this
mainboard variant.
Test: build mc_apl7, flash to mc_apl4 and compare log level 8 output
Change-Id: Ie9f2f5c29d071de442f8f3e3eaf4b3c2a6b8920f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65283
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The common AMD ACPI GPIO access code is verified to be correct for
Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I834076c0a1d1784a272896f2d8f082ebfb86a383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The MCA banks were updated in commit 736d68c0b3 ("soc/amd/sabrina/mca:
update MCA bank names to match the hardware"), but seems that I forgot
to remove the TODO about checking if this is still correct for Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd86113ccb9eeab704679afab0b985f9febed13b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65314
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The common microcode update mechanism is verified to be correct and work
on Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5c41674299a829507438beb3ea597a71a0c5a972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Current implementation only supports glibc (by looking for __GLIBC__)
and fails to build on systems with alternative libc implementations,
such as musl; sys/io.h is never included, there are no outb/inb
functions which results in undefined references at linking stage.
Using __linux__ instead of __GLIBC__ to test whether the system is Linux
seems to be a more proper way to detect Linux and it also fixes
nvramtool compilation on musl systems.
Tested on Gentoo Linux with musl 1.2.2 (builds and works fine) and Void
Linux with glibc (still builds and works fine).
Change-Id: Idcdc3a033b40f16a6053209813f1e06209ee459a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48757
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is an existing issue for nissa boards where wake up from
RTC wake is not working during suspend_stress_test.
This issue was root caused to the patch which was setting GPE_EN
bits for the GPIOs before locking.
Reference: https://review.coreboot.org/c/coreboot/+/64089
Later issue was found to be with GPP_F14 configuration for nissa
boards. When coreboot skips setting GPE_EN bit for GPP_F14, RTC
wake works properly. Another way to make it work is to skip locking
GPP_F14 GPIO to allow kernel to configure it properly.
This patch skips the locking for GPP_F14 to allow kernel to
configure it later. This fixes the issue of RTC wake not working.
Note: This patch provides workaround for the existing issue and
BUG will be closed once actual reason is identified and proper
fix is available.
BUG=b:234097956
BRANCH=None
TEST=RTC wake works on Nivviks board with the patch.
Change-Id: Ie8091ab8acf2b3f064cb79bdf4700f6b4c1674a5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Add the support RAM parts for Xivu.
Here is the ram part number list:
DRAM Part Name ID to assign
MT62F1G32D4DR-031 WT:B 0 (0000)
MT62F512M32D2DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 1 (0001)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:236576117
BRANCH=None
TEST=Use part_id_gen to generate related settings and
emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I02866f7dcdc70d1051d187fdda30e04bb654ece3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65252
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the xivu variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:235025984
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_XIVU
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I12341a2414e58ebc1c22429d35a03afef27adace
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65235
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When printing or setting the PCH straps use the PSL directly instead
of multiplying it by 4.
Change-Id: Ia91697fdf0c6d80502e8611b259c444f39c6cd57
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Show the build options that are passed to edk2 in one clear block.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I917a8c1d3ac8f2a223e584fec10689679835630c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Enable PwrOptEnable FSP S UPD and hook it to the inverted value of
SataPwrOptimizeDisable to allow it to be disabled from the devicetree.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I056fd7b16dadb213b3326523b0c7943ce35b8dc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Add support for MT62F512M32D2DR-031 WT:B and K3LKLKL0EM-MGCN.
These will be used as backup parts if there is issues getting the
Hynix parts.
BUG=b:233822880,b:236423310
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I6ace8788ffb2ec40d01b91d0a4d751e0a95883f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Arbitrage is an internal tool at Google to work with schematics
programatically. In particular, it features an "export-coreboot-gpio"
command, which, does it's best to try and make a gpio.c from the
schematics to avoid human errors when translating to C code.
This commit adds a gpio.c generated by running:
"arb export-coreboot-gpio ghost4adl:P0_2022_06_17"
This GPIO config will require hand modification. This is done in a
follow-up CL. (i.e., this CL intentionally leaves the config exactly
how it was generated by Arbitrage so we get a good diff on the changes
we needed to make)
BUG=b:234626939,b:231719130
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I35a85202768a366357073d3ebc177d0e0da661f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65210
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initial boards will not have an internal panel. Enable TCSS display
detection so we can boot on an external panel over Type-C.
BUG=b:235294840
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I6f65ddc24701d6f6ad0250560cc05b5e1d32370f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
The TPM PPI code was only generated for memory mapped non-CRB TPMs.
There is no reason why CRB TPM should not have the PPI, e.g. PTT.
Call the relevant method to add the PPI to SSDT.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3d3f08ea686c95ef75ae8fe7a5dcf16f7492ce68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Update header files for FSP for Meteor Lake platform to version 2222_01, previous version being 2173_00.
FSPM:
Includes below 2 UPDs
1. TdcEnable
2. TdcTimeWindow
FSPS:
Address Offset changes.
BUG=b:234701164
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I529118c35fa9f851ee2b5f23712ac70e2a5b53c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64878
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
We have too many acronyms to keep track of. At one point, AMD and
Intel used to use the same terms for things, but no longer. When I
look at Intel patches now, I have no idea what they mean anymore.
When I started trying to do the release notes, I kept having to
look up the acronyms, so I figured I'd make a list.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4571bf468bbfc6a1a6f33399ba61032a18fe41ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This is a wordlist that I've compiled to use in spellcheckers to ignore
all of the coreboot specific terms.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I718519000eaf31786380474eb71b99ca442e3bed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Based on 'commit 0b917bde36 ("mb/google/brya/var/kinox: Set power
limit based on charger type")' to refactoring update_power_limits
function for kinox.
BUG=b:231911918
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I1fcb593090f95bf23808e577dd11b8a836f47494
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Boards using VBOOT_VBNV_EC (nyan, daisy, veyron, peach_pit) are all
ChromeOS devices and they've reached the end of life since Feb 2022.
Therefore, remove VBOOT_VBNV_EC for them, each with different
replacement.
- nyan (nyan, nyan_big, nyan_blaze): Add RW_NVRAM to their FMAP (by
reducing the size of RW_VPD), and replace VBOOT_VBNV_EC with
VBOOT_VBNV_FLASH.
- veyron: Add RW_NVRAM to their FMAP (by reducing the size of
SHARED_DATA), and replace VBOOT_VBNV_EC with VBOOT_VBNV_FLASH. Also
enlarge the OVERLAP_VERSTAGE_ROMSTAGE section for rk3288 (by reducing
the size of PRERAM_CBMEM_CONSOLE), so that verstage won't exceed its
allotted size.
- daisy: Because BOOT_DEVICE_SPI_FLASH is not set, which is required for
VBOOT_VBNV_FLASH, disable MAINBOARD_HAS_CHROMEOS and VBOOT configs.
- peach_pit: As VBOOT is not set, simply remove the unused VBOOT_VBNV_EC
option.
Remove the VBOOT_VBNV_EC Kconfig option as well as related code, leaving
VBOOT_VBNV_FLASH and VBOOT_VBNV_CMOS as the only two backend options for
vboot nvdata (VBNV).
Also add a check in read_vbnv() and save_vbnv() for VBNV options.
BUG=b:178689388
TEST=util/abuild/abuild -t GOOGLE_NYAN -x -a
TEST=util/abuild/abuild -t GOOGLE_VEYRON_JAQ -x -a
TEST=util/abuild/abuild -t GOOGLE_DAISY -a
TEST=util/abuild/abuild -t GOOGLE_PEACH_PIT -a
BRANCH=none
Change-Id: Ic67d69e694cff3176dbee12d4c6311bc85295863
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Adjust sensor trigger point and fan duty according to thermal team
tuning results.
BRANCH=brya
BUG=b:215033683
TEST=Built and tested on tarlo board
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib543cee82f6940ab35a1a40af1d41bb2b8bf8521
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Shelley Chen