When CONFIG_EXPERT is set, compilation fails with:
src/superio/winbond/w83627hf/superio.c:61:13: error: ‘w83627hf_16_bit_addr_qual’ defined but not used [-Werror=unused-function]
cc1: all warnings being treated as errors
This function isn't used in the code, so just remove it.
Change-Id: I117e221fb3c3a20a7d7e7e2e86d7dbfdffc2cbff
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/533
Tested-by: build bot (Jenkins)
The current code uses static values for the physical address size
supported by a CPU. This isn't always the right value: I.e. on
model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
Xeons from the same family have 38 bits, which results in invalid
MTRR setup. Fix this by getting the right number from CPUID.
Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/529
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The comparision is the wrong way round: as long as tsc
is below tsc1, the timeout is not reached
Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/530
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Change-Id: If681a33deb7df752b37c6a8a20482d3c374af936
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/528
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Philip Prindeville <philipp@redfish-solutions.com>
This function prevents the linker from choosing the right
get_cst_entries(), preventing writing the _CST tables.
Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/496
Tested-by: build bot (Jenkins)
Adds a missing return statment which will stop misleading the users
Change-Id: I53741f1136b396e9493ce959b54efc00c9b09764
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/522
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ie3872c57990f9784aafda14f8c7fc842b3a65260
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/518
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Fixed indentation using indent tool in the src/drivers/i2c tree
Change-Id: I5b396e5753544aff13ac5d16afc59e193a6b1da1
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/506
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
The AGESA wrapper init late call generates the SSDT and other ACPI tables. The
call was failing without heap space allocated causing the ASSERT messages in
the output. I think are there may still be other issues in integrating the
SSDT table with the DSDT, but now it is there to debug.
The changes were made in Persimmon and copied to the other Fam14 mainboards.
Change-Id: I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/517
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The old SSDT ACPI code would only include the AGESA or the coreboot SSDT. Now
include both. AGESA generates the Pstate SSDT and the second coreboot SSDT is
for TOM and TOM2. Now, generate the coreboot SSDT instead of patching it. This
fixes some ACPI errors in Linux and Windows bluescreens.
The Persimmon acpi_tables.c is where the main changes were made and then
replicated in the other Fam14 boards. Please test the other mainbords if you
have one.
Change-Id: I808c863597e024e3e8aeec0821e8618d96cc96a6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/516
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Fix whitespace and tab issues on fam14 mainbords in preperations for upcoming
changes
Change-Id: I6d63d428dde0a5d9748027e603b03de25d3be472
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/515
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add interrupt routing for APU GNB internal Graphic and HD audio device, and
other pcie bridge device in GNB.
south_station, union_station, inagua, persimmon and e350m1 mainboard
are included herein.
Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/452
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
I misunderstood how kconfig select works. It needs to be selected with a config option. Moved the select to the correct location.
Change-Id: If9b1e21e6cbc5af4671efb76cf87dd18dbbe2234
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/487
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
CMOS accesses are not safe for multi-processor and only the BSP CPU
should count reboots and test CMOS sanity.
A questionable single byte CMOS read access from AP CPUs remains.
AP CPUs should always select the same romstage prefix as BSP CPU.
Change-Id: I29118e33c07c0080c94abb90f703e38312c72432
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/446
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Enable HD audio over HDMI.
Tested in Ubuntu-11.10 with ATI Catalyst Proprietary Driver installed.
Change-Id: I013c2c15ee56a7b134d980da1aa1856778a1eb4c
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/450
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Added the default ID to the mainboard Kconfig.
Change-Id: Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/488
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Some keyboards take pretty long to respond to a reset command, some even
delay the ACK to the command. To make the keyboard driver more robust,
increase the timeout for this special command. Also do an interface test
after the self-test to ensure the keyboard is functioning properly.
Another point is to reenable the keyboard *after* the scancode was set,
not before. We also set the system bit when enabling the keyboard
because this seems to be what older operating systems do expect.
One of the problematic keyboards, which will work with this patch
applied, is the DELL RT7D20. Without the patch an overly optimistic
operating system, read Linux 2.4, will not recognise the keyboard
because coreboot didn't fully initialize it.
Change-Id: I28c8e05bdde61f71b7de084c96bc2447c1b9575e
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/486
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Verb data is required for the HDA audio codec in the sb800 southbridge. Verb
data is not required for mainboards that use G-Series HDMI. It is also a setting
the may be boards specific. This fixes issues with Windows audio on Persimmon.
Change-Id: I067506871e92078d122cf79872363d8937d47e50
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/490
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The EC allows to select the order in which batteries are (dis)charged.
Make this setting available to the user.
Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/475
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
Checking RBIL, int10 AH=0x10 does never output a character.
The two output functions are AH=0x09 and AH=0x0e.
Change-Id: Id7f4d260b63024748ef771f949e8b60f934bacbc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/483
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
The read_option macro still emitted CMOS_VSTART_*/CMOS_VEND_* symbols,
which fail without an option table (as no option_table.h defines them).
Discard them by using a macro instead of a static inline function.
Change-Id: I8d001f971681277a344b6788725746491546b607
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/442
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This fixes problems in AP init when multiple APs are trying to access
PCI config space. All Fam10 CPUs setup and support MMCONF.
Change-Id: I00a25bbf4e4152c89024f14a3c4c1c36b48d0128
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/455
Tested-by: build bot (Jenkins)
Reviewed-by: Alec Ari <neotheuser@ymail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change the DSDT Table ID for M4A785T-M
from M4A785-M to M4A785T-M.
This fixes a small copypasta.
This is an updated patch set.
Change-Id: I43ee024222cf04d03685ffaee616971100cc9e6c
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/474
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Allocation size for the section was miscalculated, so the section
did not honour its upper-bound address.
Also align the section start to 4 bytes, so it starts with code
instead of pad bytes.
Change-Id: Ic2a43981836a0873b50abecfcad2def7b6586a5d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/453
Tested-by: build bot (Jenkins)
Reviewed-by: Alec Ari <neotheuser@ymail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Untested, changes ramstage build for boards:
supermicro/h8qme_fam10
amd/serengeti_cheetah
amd/serengeti_cheetah_fam10
AMD 8132 was not built for any mainboard due to a typo.
AMD Serengeti Cheetah:
Chip 8151 is referenced in devicetree.cb but was not built.
AMD Serengeti Cheetah Family10:
There are indications the board has 8151, but it is not listed
in the devicetree.cb. The 8151 chip is not added in the build.
Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/471
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Detection of a CPU being a BSP CPU is not dependent of the existence
of northbridge and/or southbridge init code in the bootblock.
Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP
CPU of a hyper-threading CPU and needs to return actual BSP bit from
MSR.
Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/447
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This pulls it all together and adds the real board-specific code.
Confirmed to be working:
- IDE
- SATA
- floppy
- USB1.1
- USB2.0
- PS/2 keyboard
- PS/2 mouse
- serial
- parport
- sound
- ethernet
- PCI slots
- AGP
- powernow
- fan speed monitoring
- flashrom write
Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/390
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)
Fix the DIMM mappings, channel 0 is "B" on board,
and secondary channel is on 0x51,0x53
Change-Id: I8c49c4efb90a4297aaea0be2159435dadab9ac0a
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/449
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
and remove it from mainboard/intel/mtarvon, as this function
is implemented in the southbridge code.
Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/469
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Without that fix the linux kernel cannot change the frequency
of the CPUs with cpufreq.
Change-Id: Ie00e4b11b2561356952d8ae28bd0a00523b6d85f
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/458
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This mainboard is very similar to the M4A785-M, but it has
DDR3 instead of DDR2.
That's why most of the code was copied or included from
the m4a785-m directory
Notable changes between the two mainboards include:
* the selection of the last microcode (mc_patch_010000b6.h)
which made it pass the CPU init.
* the selection of DDR3 which made it pass the ram init
This change was tested with the Trisquel 5.0 GNU/Linux distribution
which uses the linux-libre version 2.6.38-12-generic
The mainboard boots fine, however some special care is required for
the onboard sound CODEC, and the onboard video chip:
* the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue
is the same than the ASUS M4A785-M mainboard:
It causes a flood of interupts which prevents booting
* The internal video chip currently requires pci=nocrs, else
the graphics are frozen as soon as the radeon module loads,
and dmesg would print the following(the card only has 256M,
and the mainboard was equiped with 2G of RAM):
[ 3.674762] [drm] radeon: 3584M of VRAM memory ready
[ 3.679863] [drm] radeon: 512M of GTT memory ready.
instead of :
[ 45.876088] [drm] radeon: 256M of VRAM memory ready
[ 45.876089] [drm] radeon: 512M of GTT memory ready.
* The screen(both VGA and HDMI) flickers at high resolution
* Sometimes the computer freeze while changing the resolution
(even the serial console stops responding)
The following peripherals were tested:
* The ath9k PCI wireless card was tested
* The SATA hard disk works fine
* the USB keyboard and mouse work fine
* htop see 2 cores
* serial port works under coreboot and GNU/Linux
* power off and reboot works
CPU frequency cannot be changed yet, this is addressed
in a new commit.
More detail are available here:
http://www.coreboot.org/ASUS_M4A785T-M
dmesg is available here:
http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html
The mailing list thread on the graphic problem is here:
http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html
Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/457
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Apply the normal method of recursively including subdirectories
for src/vendorcode. Remove redundant references under
mainboard and northbridge.
Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/468
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Following files were no longer used in the build and are deleted:
src/arch/x86/init/entry.S
src/arch/x86/init/ldscript.ld
Also fix ugly whitespace in code copyrights and comments.
Change-Id: Ia6360b0ffc227f372d5f997495697a101f7ad81b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/440
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
