Commit Graph

5203 Commits

Author SHA1 Message Date
Jens Rottmann b9ee31d881 SMC_CONFIG is needed before the device tree is ready and some people
would rather not have mainboard settings like sio_gp1x_config in the
device tree anyway.  So found a nice united home for both in Kconfig,
where users can change them without having to mess around in the C code.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-31 19:19:16 +00:00
Jens Rottmann 3063d5dfde Make ALIX.2D3 support 2D2 as well.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-31 19:02:45 +00:00
Zheng Bao 9fae99fc4e Get Byte65/66 for register manufacture ID code. RegMan1Present will
be used in write levelization training.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-31 06:10:54 +00:00
Myles Watson bd61a81949 Make yabel work for non-zero bus numbers. The link_num is not the bus number.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 21:52:38 +00:00
Stefan Reinauer 704b59662d We call this cache as ram everywhere, so let's call it the same in Kconfig
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 17:53:13 +00:00
Stefan Reinauer 849498d447 Fix intel mtarvon compilation by switching it over to CAR.
This should be unproblematic, as there are other boards with the same "socket"
that work with CAR already. Tests are highly appreciated though!

Acked-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 16:52:48 +00:00
Jens Rottmann 9a684fcb0f Restructured all vendors' Kconfig files to no longer source the boards'
Kconfigs from within the choice/endchoice block.  This makes it possible to
define user visible board specific options.  Moved all vendor names and PCI
ids to the vendors' Kconfigs.  Now all options in each file depend on the same
symbol, so replaced all "depends on"s with a single "if".  Sorted boards
(sort -d), cleaned whitespace.

This patch also introduces a dummy option BOARD_SPECIFIC_OPTIONS, which is
always "y" and never used.  It it simply needed to have something to attach
the boards' "select" statements to.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 16:36:51 +00:00
Andreas Schultz 459b0d2ddd This file was missing from r5751.
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 16:32:23 +00:00
Andreas Schultz 4c94c05b7c Support for Lanner EM-8510 Board
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

---
 src/mainboard/Kconfig                     |    8 ++
 src/mainboard/lanner/Kconfig              |    8 ++
 src/mainboard/lanner/em8510/Kconfig       |   38 +++++++++++
 src/mainboard/lanner/em8510/Makefile.inc  |   21 ++++++
 src/mainboard/lanner/em8510/chip.h        |   23 +++++++
 src/mainboard/lanner/em8510/cmos.layout   |   74 +++++++++++++++++++++
 src/mainboard/lanner/em8510/devicetree.cb |   60 +++++++++++++++++
 src/mainboard/lanner/em8510/irq_tables.c  |   56 ++++++++++++++++
 src/mainboard/lanner/em8510/mainboard.c   |   27 ++++++++
 src/mainboard/lanner/em8510/romstage.c    |  103 +++++++++++++++++++++++++++++
 10 files changed, 418 insertions(+), 0 deletions(-)
 create mode 100644 src/mainboard/lanner/Kconfig
 create mode 100644 src/mainboard/lanner/em8510/Kconfig
 create mode 100644 src/mainboard/lanner/em8510/Makefile.inc
 create mode 100644 src/mainboard/lanner/em8510/chip.h
 create mode 100644 src/mainboard/lanner/em8510/cmos.layout
 create mode 100644 src/mainboard/lanner/em8510/devicetree.cb
 create mode 100644 src/mainboard/lanner/em8510/irq_tables.c
 create mode 100644 src/mainboard/lanner/em8510/mainboard.c
 create mode 100644 src/mainboard/lanner/em8510/romstage.c




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 16:22:22 +00:00
Andreas Schultz b6b29dbbb9 Rework i855GM/i855GME support
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

---
 src/northbridge/intel/i855/Kconfig       |   30 +
 src/northbridge/intel/i855/i855.h        |   76 +++
 src/northbridge/intel/i855/northbridge.c |   21 +
 src/northbridge/intel/i855/raminit.c     | 1036 +++++++++++++++++++++++++-----
 src/northbridge/intel/i855/raminit.h     |   14 +-
 5 files changed, 1002 insertions(+), 175 deletions(-)
 create mode 100644 src/northbridge/intel/i855/i855.h





git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 16:19:04 +00:00
Andreas Schultz 1bab1fb839 mPGA479M Sockets can take Intel Mobile Celeron.
The 1.2GHz model has CPUID F29. This adds them to the list of CPUs for that socket.

Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

This patch likely breaks the following two boards since it unconditionally
activates CAR code for this socket:

 * digitallogic/adl855pc
 * intel/mtarvon

stepan suggests moving those two boards over to CAR, too, so we don't have to
worry.

---
 src/cpu/intel/socket_mPGA479M/Kconfig      |    1 +
 src/cpu/intel/socket_mPGA479M/Makefile.inc |    2 ++
 2 files changed, 3 insertions(+), 0 deletions(-)




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 16:16:01 +00:00
Kerry She 819ee74888 Multi-DIMMS on AMD ddr2 MCT channel B fixed.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 09:40:41 +00:00
Kerry She 99cfa1e6bd Multi-DIMMS on AMD ddr3 MCT channel B works.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 07:31:31 +00:00
Kerry She 108d30ba86 Trivial syntax correction of AMD mct_ddr3 dir.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Kerry She <Kerry.she@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 07:24:13 +00:00
Stefan Reinauer f7b98f5766 fix compilation of hello.elf example payload.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-28 23:23:47 +00:00
Jens Rottmann b3f8090f4e drop three unneeded config variables:
- HAVE_HIGH_TABLES
- HAVE_LOW_TABLES
- FALLBACK_SIZE

Jens Rottmann sent an almost identical patch at the same time, so
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-27 09:36:41 +00:00
Myles Watson 78265d5609 Remove unused mainboard_config definitions. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26 18:24:04 +00:00
Jens Rottmann 0d11f2db1f CONFIG_DEBUG_RAM_SETUP and CONFIG_DEBUG_SMBUS are only available if the board /
chipset support it.  But this involves a long list of 'depends', which you have
to remember updating manually.  Converted this into HAVE_... properties, which
will be inherited automatically if someone copies a chipset to create a new
one.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26 12:46:02 +00:00
Stefan Reinauer d058ad1b4a One of my boards needs this mini delay in order to survive ram initialization.
Odd. The others don't.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26 12:43:58 +00:00
Stefan Reinauer 6e523a20ca kontron 986lcd-m: Fix compilation if there is no oprom execution at all...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26 12:42:43 +00:00
Stefan Reinauer bc8613ecaf Fix i945 based boards
- prevent GCC from inlining do_ram_command - it will break RAM initialization.
- fix the PCIRST# mechanism in those boards that do it, it requires 200ms, not 
  200us
- move PCIRST# as early as possible (before ich7_enable_lpc)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-25 18:35:42 +00:00
Aurelien Guillaume 6f22ecc2c9 * Adds support for PC Engines Alix.2D(1)3 board to Coreboot.
* DRAM initialization done message is now printed in debug-mode only, rather than everytime.

Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-24 12:58:17 +00:00
Stefan Reinauer 83628902ad mark unused variables in x86emu as unused. gcc has a mechanism for this.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-23 18:43:27 +00:00
Wang Qing Pei 53a811eeb5 Fix up some copyrights
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 20:02:27 +00:00
Xavi Drudis Ferran 3bff8b523f I've checked Revision Guide for AMD Family10h processors (#41322) rev
3.74 June 2010 for errata 351 and it agrees with the comment on
setting ForceFullT0= 000b but I believe the code didn't honor the
comment.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 20:00:42 +00:00
Xavi Drudis Ferran aa81b69bfd RB_C3 should also apply the workaround for errata 354, according to
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:59:27 +00:00
Xavi Drudis Ferran 4a43b7d2bb RB_C3 and HY-D0 should also apply the workaround for errata 344, according to
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010

My processor wasn't getting the workaround

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:56:47 +00:00
Xavi Drudis Ferran 4793ef1f82 documented workaround erratum 414, see
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010

with patch.erratum414 it stops here (next patches don't make it get further,
but they're needed according to documentation, don't break anything for me and
I still don't have a solution for booting, so I'm keeping them there in case
they fix something.

testx = 5a5a5a5a                                                                
Copying data from cache to RAM -- switching to use RAM as stack... Done         
testx = 5a5a5a5a                                                                
Disabling cache as ram now                                                      
Clearing initial memory region: Done                                            
Loading stage image.                                                            
Check CBFS header at fffffd2e                                                   
magic is 4f524243                                                               
Found CBFS header at fffffd2e                                                   
Check fallback/romstage                                                         
CBFS: follow chain: fff00000 + 38 + 15b41 + align -> fff15b80                   
Check fallback/coreboot_ram                                                     
Stage: loading fallback/coreboot_ram @ 0x200000 (1114112 bytes), entry @
0x20000

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:54:26 +00:00
Xavi Drudis Ferran 213ab94ea4 documented workaround erratum 372, see
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010

with this one  it stops here or earlier (as soon as before the patch,
sometimes):
               
*** Yes, the copy/decompress is taking a while, FIXME!                          
v_esp=000cbf48                                                                  
testx = 5a5a5a5a                                                                
Copying data from cache to RAM -- switching to use RAM as stack... Done         
testx = 5a5a5a5a                                                                
Disabling cache as ram now                                                      
Clearing initial memory region: 

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:51:34 +00:00
Xavi Drudis Ferran e9f0dfe631 Complete code for errata 343. Revision Guide for AMD Family10h
processors (#41322) rev 3.74 June 2010 says to set the register 
to 1 before CAR and to 0 after. We were setting it to 0 after CAR,
but not to 1 before.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:49:46 +00:00
Xavi Drudis Ferran cc6244a922 Include RB_C3 in erratum 346
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:48:29 +00:00
Xavi Drudis Ferran 752f1b4ee7 Add RB_C3 to AMD_FAM10_ALL so that it gets its MSR right for mtrs, ht, etc.
While reviewing impact of this change it seems code for erratum 531 was not in
sync with current docs. I have checked uses of AMD_FAM10_ALL, but I
haven't looked up the docs for all of them, at first sight it seems ok
to include all FAM10 revisions in this mask.

Apply errata 531 only to revisions listed in  Revision Guide for AMD Family10h
processors (#41322) rev 3.74 June 2010. Before it was applied also to
DR-B0, DA-C3 or HY-D0 which are not affected according to current docs.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:45:57 +00:00
Anders Juel Jensen 28e4af5801 Add suport for normal register dumping on ite8510E/TE/G
Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:41:47 +00:00
Anders Juel Jensen 3d0ff918f8 Add another port to find ite8510 on.
Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:40:58 +00:00
Anders Juel Jensen 4fd7df9535 Add support for non LDN register/device naming.
Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:40:11 +00:00
Anders Juel Jensen 280275dcb5 The LDFLAGS = -lz is needed to compile on slackware.
Clubbering CFLAGS is never a good idea.

Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:39:04 +00:00
Myles Watson 3613d05e24 Remove a couple of warnings. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-20 20:45:04 +00:00
Oskar Enoksson 37106a762a Add support for the HP DL145 G1, based on the Tyan s2881.
Signed-off-by: Oskar Enoksson <oskeno@foi.se>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-20 20:37:27 +00:00
Jens Rottmann ca1a762479 libpayload: fix garbage on screen with Geode-LX VGA
Clear initial garbage in VGA memory and fix scroll_up, which scrolled 1 scanline
instead of 1 text line by mistake.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-18 21:23:27 +00:00
Wang Qing Pei d6c4395927 The attached file add pa78vm5 dev3 detection function to avoid the building error.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-18 01:55:11 +00:00
Rudolf Marek c7d2773e12 Attached patch removes unnecessary IRQ routing info (for ACPI, mptable etc needs to be fixed too). The devicetree.cb changes should reflect now the real board configuration. It has one 16x slot and 1x slot (GPP device 9) and GPP device a is onboard ethernet. The mainboard.c now presents the board name and
I removed the gpio asserts - I think those are not used here.

The pcie 1x slot works, the x1 card I have does not work in 16x slot, but in orig bios I cannot see it any slot, so it is kind of better.

The classic PCI slot works fine too. However it seems SATA has some issues.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17 21:03:17 +00:00
Jens Rottmann da71ba5284 Correct for size_t would be %zx, but coreboot's printf doesn't support this.
Trying to keep it simple:  Two sizes are expected equal so use same %x for both.
Cast to unsigned int to make sure it fits.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17 16:32:42 +00:00
Wang Qing Pei 0ede4c08a9 Commit (non-working!) Jetway PA78VM5 mainboard
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17 15:19:32 +00:00
Wang Qing Pei 42e7c32cc5 Support for Fintek F71863FG. This might need some work on the copyright
notices. Getting it into the tree so people can get to it.

Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17 15:05:05 +00:00
Marc Bertens acc3749644 image parsing for getpir
when adding for example build/coreboot_ram as parameter
it looks in the file for the PIRQ table prints it to stdout 
and shows if the checksum is correct. 

getpir works as before without any commandline parameters.

This is very handy for developing a PIRQ table.

Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17 11:32:21 +00:00
Wang Qing Pei 931d6f3782 Another AMD 780/700 mainboard: Gigabyte MA78GM-US2H
http://www.gigabyte.cn/products/product-page.aspx?pid=3118#ov
the simple config is
AM2+DDR2+SB700+RS780, the superIO is IT8718F

The patch has been tested with SeaBIOS + SUSE11.2

Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17 11:22:40 +00:00
Wang Qing Pei 543f767dbf Tilapila supports both dual slot and single slot. The difference should be
detected by the existence of dev3. Some other RS780 mainboard has 
the same function. The patch added the function to make these boards work
smoothly.

Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17 11:11:09 +00:00
Wang Qing Pei 3f90125ab5 Add support for Gigabyte MA785GMT mainboard.
Details of the hardware configuration can be found at
http://www.gigabyte.com/products/product-page.aspx?pid=3478

Brief configuration is:
  1. CPU:Support for AM3 processors: AMD PhenomTM II processor/ AMD Athlon™ II processor
  2. North Bridge: AMD 785G
  3. South Bridge: AMD SB710
  4: Super IO : ITE8718F

The mainboard has two bios flashchip. Coreboot ROM should be flashed into the
M_BIOS (which means main bios).

Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17 11:08:31 +00:00
Stefan Reinauer 92fafbd0d3 fix nokia ip530 Kconfig, missed on last check-in
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17 10:54:36 +00:00
Stefan Reinauer 59a1b7f7f1 libpayload: Add function to fix CMOS checksum.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17 10:14:50 +00:00