Commit Graph

4214 Commits

Author SHA1 Message Date
Jingle Hsu 4067fa3512 util/inteltool: Add support for Intel Lewisburg SKU C621A
Add support for dumping GPIOs on Intel Lewisburg SKU C621A.

Tested=On OCP Delta Lake DVT, verify it executes successfully.

Change-Id: I58797914aa5816aedace094c179e832150ad5e2e
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09 10:19:08 +00:00
Zheng Bao 795d73c6d8 soc/amd/picasso: Update coreboot UPD variable names to include units
Use command below to change the variable globally.

sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \
   --exclude-dir=build --exclude-dir=crossgcc`

BUG=b:171334623
TEST=Build

Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-06 13:02:24 +00:00
Benjamin Doron 7bb756fad7 util/intelp2m: Update macros
Change-Id: Ia0a7dea89fdb69e01f0abe577488f26a5d2bd6ed
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-04 21:14:58 +00:00
Zheng Bao 3384e4a709 soc/amd: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION
Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 09:42:18 +00:00
Zheng Bao 77a2c67dfe amdfwtool: Change all error output to fprintf stderr
Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 09:42:04 +00:00
Zheng Bao 9e90807b40 amdfwtool: Add an option to show debug message
Change-Id: I3e3bcc2c9e1b3edfed1ce845c1603b2a9a2bb044
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-04 09:41:58 +00:00
Nico Huber 9e20e2f158 util/qemu: Add comprehensive default config for QEMU Q35
This config tries to mimic the actual devices of a mainboard
with Intel's Q35 chipset. It provides a much better base to
test coreboot (e.g. its allocator) and payloads.

Change-Id: Id465016e37ee75628a55b9da68facb4ae0efe822
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-04 09:39:50 +00:00
Nico Huber a08328ecff util/qemu: Add `qemu` make target
Add some mechanics to automatically have a `qemu` make target for
supported configurations. So with a QEMU target selected in Kconfig,
one would ideally only have to run `make qemu` to test things.

There are some notable variables that can be set or adapted in
`Makefile.inc` files, the make command line or the environment.

Primarily for `Makefile.inc` use:
 QEMU-y           the QEMU executable
 QEMU_CFG-y       a QEMU config that sets the available default devices,
                  used to run more comprehensive tests by default,
                  e.g. many more PCI devices

For general use:
 QEMU_ARGS        additional command line arguments (default: -serial stdio)
 QEMU_EXTRA_CFGS  additional config files that can add devices

 QEMU_CFG_ARGS    gathers config file related arguments,
                  can be used to override a default config (QEMU_CFG-y)

Examples:

  $ # Run coreboot's default config with additional command line args
  $ make qemu QEMU_ARGS="-cdrom site-local/grml64-small_2018.12.iso"

  $ # Force QEMU's built-in config
  $ make qemu QEMU_CFG_ARGS=

Change-Id: I658f86e05df416ae09be6d432f9a80f7f71f9f75
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-04 09:39:11 +00:00
Patrick Georgi 5193312e1e util/sconfig: Report which key is duplicate
It slightly helps debugging issues when you know what to look out for.

Change-Id: I21eafaf8291701316aa920e458ba74535121b0a1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-04 09:38:08 +00:00
Usha P 412679d892 util/ifdtool: Enable CPU read of the ME region
We are implementing a mechanism in coreboot to update CSME firmware,
this requires coreboot to be able to read CSME region. Exposing the
CSME data is not an issue since the data stored by CSE is all encrypted.

This patch provides a command line option "-r" which will enable read
access to CSME region when locking.

Without this change, locking SPI regions using ifdtool will block BIOS
access to read/access CSME. This will cause failure since BIOS can't
read basic information such as CSME version.

TEST=Flashrom returns success while erasing the SI_ME region.
After rebooting the DUT, DUT boots into OS without any issues on
Drawlat EVT.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02 10:39:27 +00:00
Patrick Georgi 8aa087ece6 .gitignore: Ignore .test/.dependencies globally
These were originally ignored only inside util/ but these files
shouldn't be tracked anywhere.

Change-Id: Ie0846bd8bdd6e52f420f9dd2e72a8a922102ff90
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-31 18:21:36 +00:00
Tim Wawrzynczak 24b4af668b fw_config: Convert fw_config to a 64-bit field
We all knew this was coming, 32 bits is never enough. Doing this early
so that it doesn't affect too much code yet. Take care of every usage of
fw_config throughout the codebase so the conversion is all done at once.

BUG=b:169668368
TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG
and verify the console print contained that bit.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 15:24:52 +00:00
Zheng Bao c5e28abaf8 amdfwtool: Take a config file instead of command line parameters
To verify the consistency, see if timeless builds with and without
this patch result in identical coreboot.rom files.

BUG=b:154032833
TEST=Build & boot on mandolin

Change-Id: Icae73d0730106aab687486e555ba947796e5e757
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-30 12:10:04 +00:00
Patrick Georgi 0a9eea0f5b util/docker: Add sdcc to our build nodes
core-ec will need it.

Change-Id: Id7d677a6f92ce266f893372a2540d77abb613707
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-10-30 09:28:41 +00:00
Patrick Georgi 6065f616eb .gitignore: Split into subdirectory files
There's no need for the global list of files to ignore, so use git's
ability to work with more local configuration.

Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 07:05:27 +00:00
Stefan Reinauer e4e08f2bfe ifdtool: add "reserved" regions
This will let you at least dump / add these regions.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I195ba5e93823603e712cd16cecbb48141302bed6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-10-28 19:41:51 +00:00
Martin Roth 93122a7e77 util/testing: Allow what-jenkins-does to skip lint testing
The linters touch every file under src and probably util.  This makes
it difficult to see what files have been accessed by the builder.

The JENKINS_SKIP_LINT_TESTS variable will only be set on the jenkins
build that looks for unused files.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I12fa31641c2a72c5e07be1c4958467f7165f21bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:10:56 +00:00
Martin Roth b043277866 util/testing: Update test-abuild output directories
This matches the what-jenkins-does target.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I20b455e0161dcebf2eb9022bd142bbec99937a19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:10:14 +00:00
Martin Roth 2aba15fce1 util/docker: Update atime mount point options for jenkins
- The ccache files don't need atime.
- Enable strict atime for the git repos.  This will help find unused
files.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I94bcc55ea5c5a74f3ad0292ca50b74874a0d920d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:09:50 +00:00
Martin Roth a266299490 util/docker: Update agent-root to node-root for jenkins
Jenkins has changed the name of the build directory, so it's not
currently building out of memory, it's writing to the SSD. This
changes the build back to tmpfs.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iefcf53757862feb2025aa5696f9f5dbce9dd70dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:09:06 +00:00
Martin Roth 7d520ff98f util/docker: Add tests to coreboot-sdk build process
This tests some of the basic targets that coreboot-sdk needs to be
able to run.

I was running most of these tests manually after creating the sdk
image, but adding it into the Dockerfile makes sure they get run.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0d4a2ad82042733a7966edb8ccf927676618977c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:08:45 +00:00
Martin Roth ebeec5aed3 util/docker: Update coreboot-sdk consolidate coreboot build
Because docker saves a container for every run command, by breaking
the coreboot build into 3 commands, it greatly increased the size of
the docker containers needed.  When combined as one run command, the
coreboot repo that is downloaded, along with the coreboot test build
are deleted before the container is created.  Since those directories
are deleted in a later run command, they don't even make it into the
final container, and just force coreboot-sdk users to download extra
data for no reason.

While splitting the build may help with debugging failures when
creating the docker container, that debugging can be done locally by
splitting up a working copy.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia28ee4e22c0a76dc45343755c45678795308adca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:07:20 +00:00
Martin Roth b86d2b0935 util/docker: Update coreboot-sdk to set python2 as default
Even though both python2 and python3 are now installed to the SDK, the
default python program is not.  This sets the default to python2.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4220c316df86cb2481143a79fadb70fc734e6879
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:06:17 +00:00
Martin Roth bd8e6dd2ca util/docker: Update coreboot-sdk with additional tools
- cscope: Run cscope targets
- ctags: Run ctags targets
- pbzip2: Allow compression on all cpu cores

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I31ca45fcc5880f2b0346ca3f7d36a71ae18da979
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:06:00 +00:00
Martin Roth ce19f4f8ad util/testing: Remove test for util/broadcom/secimage
util/broadcom/secimage was removed in commit aea00f496b, so don't
try to test it anymore.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ibcc018a6b8ed4ecd407f2dc374cec62900920a92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:05:15 +00:00
Julius Werner 11298542cd cbfstool: Don't build unneeded commonlib sources
These sources are built but not used by cbfstool. The only .c file in
commonlib/ it really needs is fsp_relocate.c. Get rid of the others.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6ebbb4161874f6279b6dbaffe7c3144226a6f9b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46253
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:59:53 +00:00
Stefan Reinauer 3a7825983c ectool: Don't ignore fgets return code
Change-Id: I12dc449e06dee31b4b0811ab23c6e8635cf31512
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:56:56 +00:00
Stefan Reinauer 9d50efe19d ectool: Add newline to warning message
Cosmetic fix:

$ sudo ./ectool -p
Cannot get EC ports from /proc/ioports, fallback to default.EC RAM:

Change-Id: Icc2b5bbbbfe7685e4fe512af029ce00b33a26daa
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:56:49 +00:00
Stefan Reinauer f3b1a53858 inteltool: Only use real graphics devices
Right now IGD is hard coded to 0:2.0 and if that
device is there, it is blindly used, even if it is
not a graphics device. Look at the PCI class to make
sure we're not using the wrong device.

Change-Id: Ia7f52071bd202e2960faba0f46e4fa5e14ad65f8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:56:36 +00:00
Stefan Reinauer 91893ee785 inteltool: initial Hewitt Lake support
Change-Id: Ifed43d058c70f75d88e9f4b2b07527782ebcbac5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:56:26 +00:00
Tim Wawrzynczak ba4a4909a8 sconfig: Split up sconfig-generated static.h
Currently sconfig generates a `static.h` to accompany
`static.c`. However, some payloads may decide they would like to consume
the FW_CONFIG macros as well. The current state of `static.h` makes this
impossible (relying on `device/device.h`).

This patch splits up `static.h` into 3 files: `static.h,
`static_devices.h`, and `static_fw_config.h`. `static.h` simply includes
the other two `.h` files to ensure no changes are needed to other
code. `static_devices.h` contains the extern'd definitions of the device
names recently introduced to sconfig.  `static_fw_config.h` contains the
FW_CONFIG_FIELD_* macros only, which makes it easily consumable by a
payload which wishes to use FW_CONFIG.

Also refactor the generation of all these output files, as the code was
getting messy.

Change-Id: Ie0f4520ee055528c7be84d1d1e2dcea113ea8b5f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-26 06:54:16 +00:00
Benjamin Doron 0310279411 util/intelp2m: Fix typos
Change-Id: I7210fb44ed54d365181ca23c6b92d2269dc8a697
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:49:03 +00:00
Angel Pons 4eedd938fa util/abuild/abuild: Do not check out submodules
This force-downloads the qc_blobs repository, whose license is then
automatically accepted. This may also cause race conditions with git.

Change-Id: Id760172289abbe4d5ad5f230c9f1d3e1ab3908ec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45607
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 07:07:31 +00:00
Nico Huber e16971ac64 util/supermicro: Always include commonlib/bsd/compiler.h
We rely on `compiler.h` for definitions like `__packed`. Without it,
`smcbiosinfo.c` simply declared a global struct with that name, but
nothing was packed.

Found-by: reproducibility test

Change-Id: Ide055317115fc374a63812bcd3791445ca4f2dcc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-19 07:04:43 +00:00
Angel Pons 04bf41b5aa util/lint: Capitalise lint descriptions
Most test descriptions are capitalised already. Follow suit.

Change-Id: I756331323a39643244c4adea4c440f305424d6d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-14 09:19:58 +00:00
Elyes HAOUAS 90d00dea55 {src/mb,util/autoport}: Use macro for DSDT revision
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13 18:27:04 +00:00
Matt DeVillier ceeeadb890 util/superiotool: Add EC registers for IT8728F
Add support for dumping registers, default values for
EC on ITE IT8128F. Taken from datasheet 'IT8728F V0.4.2'

Test: 'superiotool -d -e' on board with IT8728F Super IO

Change-Id: I7074b740565edf458d6894c066b61c083a657cb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12 21:43:12 +00:00
Maxim Polyakov 726282b44f util/intelp2m: Update output information format in the comments
Update the information format in the comments above the macros in the
generated gpio.h file:

PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE,
DISPUPD), /* LPSS_UART0_TXD */ -->(i)

/* GPIO_39 - LPSS_UART0_TXD */ --> (ii)
/* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii)
/* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iii)
/* _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), */ --> (iiii)
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE,
DISPUPD),

Also, in the case of field macros:

/* GPIO_39 - LPSS_UART0_TXD */ --> (ii)
/* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii)
/* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iii)
/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE,
DISPUPD), */ --> (iiii)
PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),

By default, if do not use the -i... option, then additional information
in comments will not be generated.

TEST:
git clone https://github.com/maxpoliak/inteltool-examples.git test
./intelp2m -n -file test/inteltool-asrock-h110m-stx.log
./intelp2m -fld cb -file test/inteltool-asrock-h110m-stx.log
./intelp2m -fld fsp -file test/inteltool-asrock-h110m-stx.log
./intelp2m -fld raw -file test/inteltool-asrock-h110m-stx.log

Before and after (now with -i key) the patch, gpio.h is no different.

Change-Id: I760f4aadece786ea455fb7569f42e06fefce2b61
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45168
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12 08:43:14 +00:00
Matt DeVillier f81944f9c9 intelmetool: Add PCI ID for Cometlake-U
Tested on out-of-tree CML-U Purism board

Change-Id: I0371e913a75e47b8e6f5a3e4da47b1e401a72b5d
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45929
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12 08:41:29 +00:00
Nick Vaccaro 6745056a06 util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC
Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC.

BUG=b:161772961
TEST=none

Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-12 08:38:27 +00:00
Duncan Laurie e335c2e02f sconfig: Allow chipset to provide a base devicetree
This change extends the devicetree override one more layer and allows
the chipset to provide the base devicetree.  This allows the chipset to
assign alias names to devices as well as set default register values.
This works for both the baseboard devicetree.cb as well as variant
overridetree.cb.

chipset.cb:
device pci 15.0 alias i2c0 off end

devicetree.cb:
device ref i2c0 on end

BUG=b:156957424

Change-Id: Ia7500a62f6211243b519424ef3834b9e7615e2fd
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-09 23:25:46 +00:00
Kangheui Won 4b5c8b5541 rules.h: change verstage name if it starts before bootblock
VBOOT_STARTS_VEFORE_BOOTBLOCK indicates that verstage starts before
bootblock. However "cbmem -1" will first try to match "bootblock
starting" to find out the beginning of console for current boot.

Change ENV_STRING for verstage to "verstage-before-bootblock" in the
case and add regex in cbmem utility to grab it.

BUG=b:159220781
TEST=flash and boot, check `cbmem -1`
BRANCH=zork

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ica38f6bfeb05605caadac208e790fd072b352732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-08 01:22:20 +00:00
Paul Fagerburg f52e4a03ec templates: add an empty SPD to SPD_SOURCES
Add an empty SPD in SPD_SOURCES when creating a new variant of
hatch, volteer, waddledee, or waddledoo, so that coreboot can build
successfully.

For variants that use spd_tools, add an empty mem_parts_used.txt so
that the developer can add the supported memory parts and regenerate
the Makefile.inc with the correct SPD references.

Add an empty SPD for LPDDR4x for waddledee and waddledoo to use.

BUG=b:169422833
TEST=create a new variant of hatch, volteer, waddledee, and waddledoo.
Observe that each one succeeds.

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I06dfb6103701bf8949180595f1e98fac48bcc585
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-06 18:27:31 +00:00
Zheng Bao 9c8ce3e423 amdfwtool: Remove the assumption of ROM_SIZE
Every platform passes (and need to) the --flashsize to the command
parameter, so we remove the macro definition about a built-time
romsize defined in Makefile.

Change-Id: I894e833ed23a7da38b36986b624e7dcdf1f4090c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-05 08:37:46 +00:00
Zheng Bao 473969163d amdfwtool: Use a variable to get the return value of write
New Jenkins complaint about the original code that return
value gets to nowhere. Fix that with a new variable.

Change-Id: I8099b856ccb751dc380d0e95f5fe319cc3e2c6cc
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45812
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 08:37:37 +00:00
Zheng Bao 7698a55202 amdfwtool: Clean up the Makefile of amdfwtool
Add Makefile.inc to compliant with other tools.
Makefile is kept for building amdfwtool by typing make
in the folder.

Change-Id: I3688d93de4459f5f838955892086b4b9bf30a9b8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-05 08:37:28 +00:00
Rob Barnes 34cf7ccebc Revert "util/spd_tools: output binaries instead of hexdumps"
This reverts commit f23794cf04.

Reason for revert: This change breaks compatibility if the changes
in CB:44775 are not also included. CB:44775 is still under discussion,
so revert this change to make spd_tools usable again.

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5840a1b895dcbc8b91c76d8b60df2f95b93a4370
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44999
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 16:29:00 +00:00
Zheng Bao 6d402acbc0 amdfwtool: Fix the gcc warning about sign comparison
New (maybe) compile tool complains the warning below.
warning: comparison between signed and unsigned
integer expressions [-Wsign-compare]
Fix all of them.

Change-Id: I59624326233284e6c3595df49625563254949c45
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-02 16:01:45 +00:00
Subrata Banik a5f4781d81 util/ifdtool: Include ADL dynamic check as per Gen12 SPI flash guide
BUG=b:153888802
TEST=Able to list correct PCH revision, SPI/eSPI frequency as per
ADL SPI flash guide.

Without this CL :
PCH Revision: 500 series Tiger Point

With this CL :
PCH Revision: 500 series Tiger Point/ 600 series Alder Point

Change-Id: I0faf0f0fdb625ff82eb0033b5b77e6470971bc23
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-02 04:01:08 +00:00
Maxim Polyakov c65f1f95dc util/intelp2m/apl: Remove unused plat-spec function
Change-Id: I42074387a08b66b038ad2939f31be263eaa3af0e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44473
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28 15:44:23 +00:00
Tom Hiller 9e7c99dcae Intel GBE 82579LM bincfg set and spec
Using bincfg, generate Intel 82579LM GBE region firmware.

* Intel 82579LM is used in Lenovo models including x220 and x230.
* PXE is disabled.
* Intel 82579V variant could be generated with a few modifications to
set.  Noted in set file comments.

Change-Id: I377cbe2f77f2aef39f452dc6511a0ea6b2015963
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-28 09:44:45 +00:00
Maxim Polyakov fd76c5e540 util/intelp2m: Remove unnecessary tabs
Change-Id: I5aa4b9ac4fa1ceb6f3c2ade214d47b29246ece55
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-28 09:42:24 +00:00
Amanda Huang 873accd4a8 util: Add new memory part for zork boards
Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data
sheets.

BUG=b:165611994
TEST=Compared generated SPD with data sheets and checked in SPD

Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-09-28 06:11:54 +00:00
Idwer Vollering 458e7dff6d util/crossgcc: correct the spelling of what should have read 'verifying'
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I46af7a225238046f393bbc4b3a214bebc527e079
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45733
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27 13:33:32 +00:00
Paul Fagerburg 39dbb86bbe templates: add ddr4-spd-empty.hex to SPD_SOURCES
We need at least one SPD in SPD_SOURCES when creating a new variant
of trembyle or dalboz, or else coreboot won't build. Add the empty
DDR4 SPD so that we can build the new variant.
Add an empty mem_parts_used.txt so that the developer can add the
supported memory parts and regenerate spd/Makefile.inc using
spd_tools.

BUG=b:169199396
TEST=create a new variant of dalboz or trembyle and observe that
the build succeeds.

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I764690c76529780186d0a1d156a623821f9d6972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-09-24 15:29:50 +00:00
Pablo Stebler 9ac91d220f util/intelmetool: Fix the BootGuard dump feature
Read the correct bits for measured and verified boot, print information
about some other bits.

Signed-off-by: Pablo Stebler <pablo@stebler.xyz>
Change-Id: Ie79d6da33032aee94d716bf0698b5501bbc424fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-23 20:58:28 +00:00
Felix Held d57c1286de util/cbfstool/fmaptool: generate defines for all fmap sections
Add defines for the start and size of the FMAP sections to the
optionally generated header file. For the defines the name of the
corresponding FMAP section is used without the full path, since every
section name should be unique anyway as documented here:
Documentation/lib/flashmap.md

BUG=b:157068645
TEST=Generated header file contains expected defines.
BRANCH=zork

Change-Id: Ie31161cfd304b69a3cb4bb366bf365d979e77c64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-23 13:39:21 +00:00
Felix Held c99bd4a6c9 util/cbfstool/fmd: make flashmap_flags bitfield struct elements unsigned
One bit wide bitfields should always be unsigned, since they can only be
either 0 or -1, but never 1 which is assigned to that bit field in some
cases. Making this unsigned allows it to have the values 0 or 1 which is
what we want there.

BUG=b:157068645
BRANCH=zork

Change-Id: I99c236df583528848b455ef424504e6c2a33c5d6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-23 13:39:14 +00:00
Paul Fagerburg 8b1ee26ac1 template/waddledoo: remove acpi/camera.asl
ACPI tables are generated at runtime for camera components. Remove
the static ASL file.

BUG=b:168755528
TEST=create a new variant of Waddledoo and observe that the build
succeeds.

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: Ie9e3d5856d5e95562df03814ab31e4e79a40a968
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45629
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23 04:44:16 +00:00
Iru Cai 8c6d1610d1 util/autoport: Always output quoted Kconfig string
Change-Id: I2076af9c70b626673a83af9abf464d376cda711b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-21 08:13:08 +00:00
Maxim Polyakov 0a6f82835e util/intelp2m: Check keywords in common code
TEST = ./intelp2m -n -file inteltool.log;
       ./intelp2m -fld cb -file inteltool.log;
       ./intelp2m -fld fsp -file inteltool.log;
       ./intelp2m -fld raw -file inteltool.log.
       Before and after the patch, gpio.h is no different.

Change-Id: I8af28960e41fcb97f03fe97c42cdddde07b3615a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21 08:07:26 +00:00
Michael Niewöhner e0d749c23b lint: check for misuse of Kconfig SUBSYSTEM_*_ID
Check that nobody misuses the Kconfigs SUBSYSTEM_*_ID. They are meant to
be used for overriding the devicetree subsystem ids locally but shall
not be added to a board's Kconfig. Instead, the devicetree option
`subsystemid` should be used.

Add a linter script for this that finds and warns about such misuse.

Also add a note in the Kconfigs' description.

TEST=CB:45513

Change-Id: I21c021c718154f1396f795a555af47a76d6efe03
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-20 17:03:32 +00:00
Duncan Laurie cbd0bd8155 sconfig: Add function for parse+override of tree
Extract the steps to parse and override a devicetree into a function
so it can be used multiple times without copying the same logic.

Change-Id: I4e496a223757beb22e3bd678eb6115968bd32529
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-18 22:41:56 +00:00
Duncan Laurie 51c8373593 sconfig: Switch to getopt
Instead of positional arguments switch sconfig to use getopt and pass
the arguments as options in the build system.  This will make it easier
to add additional options.

Change-Id: I431633781e80362e086c000b7108191b5b01aa9d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-18 17:50:00 +00:00
Yilin Yang 46eaa5a1ba util/rockchip: Port make_idb.py to python3
BUG=chromium:1023662
TEST=buildbot pass
TEST=1. Use python2 script
     2. Run `emerge-kevin coreboot` twice, so we get bootblock.bin.1
     and bootblock.bin.2
     3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex
     and bootblock.bin.2.hex
     4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the
     difference. (at least, the time info changes)
     5. Migrate to python3
     6. Similar steps, we get bootblock.bin.py3.hex
     7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference
     is similar. (time info, git hash changes)

Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I04253084ec9b65310c52598b629390051cd2172b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45447
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18 13:30:05 +00:00
Yilin Yang 1502494cba util/exynos: Port *_cksum.py to python3
BUG=chromium:1023662
TEST=1. Create a tiny file `in.txt` as input
     2. Run `fixed_cksum.py in.txt out.txt 20` with py2 and py3 version,
     the output is the same
     3. Run `variable_cksum.py in.txt out.txt` with py2 and py3 version,
     the output is the same

Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I9428269dfb826a3a95fffef9ea3f7c1a7107ef84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-18 08:00:39 +00:00
Yilin Yang f944e619dd util/mtkheader: Port gen-bl-img.py to python3
BUG=chromium:1023662
TEST=1. Use python2 script
     2. Run `emerge-asurada coreboot` twice, so we get bootblock.bin.1
     and bootblock.bin.2
     3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex
     and bootblock.bin.2.hex
     4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the
     difference. (at least, the time info changes)
     5. Migrate to python3
     6. Similar steps, we get bootblock.bin.py3.hex
     7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference
     is similar.

Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I788e7c9b09257142728a0f76df8c2ccc72bf6b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-18 08:00:22 +00:00
Masanori Ogino 33f64b5d78 crossgcc: Fix libcpp to address -Wformat-security
On some systems where the system compiler enables `-Wformat-security
-Werror=format-security` options by default, building libcpp fails
because the code passes a variable directly as a format string.

This change addresses this problem by patching the affected code.

Tested with the default compiler of Nixpkgs unstable, GCC 9.3.0 with the
options described above enabled by default.

Signed-off-by: Masanori Ogino <mogino@acm.org>
Change-Id: Ibf3c9e79ce10cd400c9f7ea40dd6de1ab81b50e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 07:11:59 +00:00
Jacob Garber 07201d7a0f coreinfo: Use SPDX license identifiers
- Remove copyright notices and add authors to AUTHORS
- Use SPDX license identifiers for all files
- Add coreinfo to the license header lint

Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ib0c5328a4027849b1eda4f57141a898335230726
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 07:05:27 +00:00
Martin Roth 1ba86f685b utils/docker/coreboot-sdk: Update python to python2, add python3
The latest debian image needs the python2 package specified instead of
just 'python'.  Also add python3 to the builder as we'll probably be
getting python3 scripts before too long.

Change-Id: Iceea3981b1e219141bf06ad0b559cdbf1c98b360
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-13 23:14:16 +00:00
Nico Huber 8e1ea525d1 sconfig: Allow to link devices to other device's drivers
Rarely, the driver of one device needs to know about another device
that can be anywhere in the device hierarchy. Current applications
boil down to EEPROMs that store information that is consumed by some
code (e.g. MAC address).

The idea is to give device nodes in the `devicetree.cb` an alias that
can later be used to link it to a device driver's `config` structure.
The driver has to declare a field of type `struct device *`, e.g.

    struct some_chip_driver_config {
            DEVTREE_CONST struct device *needed_eeprom;
    };

In the devicetree, the referenced device gets an alias, e.g.

    device i2c 0x50 alias my_eeprom on end

The author of the devicetree is free to choose any alias name that
is unique in the devicetree. Later, when configuring the driver the
alias can be used to link the device with the field of a driver's
config:

    chip some/chip/driver
            use my_eeprom as needed_eeprom
    end

Override devices can add an alias if it does not exist, but cannot
change the alias for a device that already exists.

Alias names are checked for conflicts both in the base tree and in the
override tree.

References are resolved after the tree is parsed so aliases and
references do not need to be in a specific order in the tree.

Change-Id: I058a319f9b968924fbef9485a96c9e3f900a3ee8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35456
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 17:34:01 +00:00
Patrick Georgi 28276fc834 util/abuild: Remove symbols that don't exist anymore in Kconfig
Bayou and OpenBIOS aren't supported by the coreboot build system
anymore, so remove these mentions.

Change-Id: Ibdf6fdc776068041cb468fdbf5b56b06f85c2d4b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-10 15:50:27 +00:00
Rob Barnes 97dd498815 util/mb/google: Update dalboz/trembyle template
- Fix relative path to spd folder.
- Add spd folder with empty files.

BUG=None
TEST=None

Change-Id: Iae88ff9c8255f60544312f0eeadf1ce617437baf
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-09 10:46:43 +00:00
Rob Barnes ad1da3a326 util/spd_tools: Support comments in mem_parts_used
Allow comments prefixed with '#' in mem_parts_used csv file.

BUG=None
TEST=Run gen_part_id with mem_parts_used file containing comments

Change-Id: Ia9e274d45aa06dea7a3a5f8cd1c8ee2b23398876
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-09 10:46:03 +00:00
Michael Niewöhner f23794cf04 util/spd_tools: output binaries instead of hexdumps
Instead of generating hexdumps, output binary SPD files since we plan to
convert all hex SPD files to binary. Also adjust the file extension
where needed.

Test: compared generated binaries with converted binaries from hex files

Change-Id: Ie99d108ca90758d09dbefad20fe6c9f7fc263ef1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08 05:46:41 +00:00
Michael Niewöhner e10efa3a03 util/apcb_edit: fix handling of binary SPD files
Passing binary SPD files to apcb_edit can lead to an encoding error,
since the files were read in text mode. To fix this, read SPD files
always in binary mode and only decode them, when `--hex` is set.

Tested by comparing output files from the same SPDs in both, binary and
hex mode.

Change-Id: I6b75a9e1234e71667bdc8cb4eb10daf8c0ac3c17
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08 05:44:28 +00:00
Subrata Banik 60296aec76 util/ifdtool: Add NULL check for pointer fpsba
This patch adds NULL check inside get_ifd_version_from_fcba()
function to fix Klocwork issue.

BUG=b:153888802

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I525054376b36c658b93760b185ef6dd170f5aea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-08 05:37:36 +00:00
Sam McNally 911db1f997 util/mb/google/tmpl/puff: Update DPTF to the new implementation
Apply the change in CB:44905 to the puff template, moving DPTF policies
from static ASL files into the new SSDT-based DPTF implementation.

BUG=b:158986928
BRANCH=puff
TEST=None

Change-Id: I601fd4c6aeaa3afee0f7fd9d13376f2fffd6d793
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-06 23:41:00 +00:00
Patrick Georgi 80370ff991 crossgcc: Ensure that GMP is built for a generic CPU on x86
While GMP supports fat builds on x86 that adapt to the CPU's
capabilities, by default it builds for the CPU of the builder.
Running that binary on an older CPU then can fail.

Change-Id: Iafdc2eb696189b9e2c5ead316f310d98c949ef74
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45044
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-03 18:47:09 +00:00
Martin Roth b1f648fc5c util/amdfwtool: Add PSP verstage signature entry
Add the field for the PSP verstage signature entry.  This adds the
public key signing token to the PSP Directory table to verify the signed
PSP verstage binary

BUG=b:166100797
TEST=Build in a file and verify that it's present with the correct ID.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7525045d8746b6857979d07b02758ab4d4835026
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03 16:30:14 +00:00
Martin Roth eca423b44f util/amdfwtool: Fix warning taking address of packed struct member
GCC9 introduced a new warning [-Waddress-of-packed-member].  This
is giving the following warning when building amdfwtool: warning: taking
address of packed member of ‘struct _bios_directory_entry’ may result in
an unaligned pointer value. Looking at the definition of the struct, it
looks like this is probably true.

Since the function being called doesn't read from the values, zeroing
them out in the beginning of the function, the code just passes pointers
to the temporary variables without initializing them.

BUG=None
TEST=Build & use AMD firmware table.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2f1e0aede8563e39ab0f2ec6daed91d6431eac43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03 16:25:40 +00:00
Subrata Banik e5d3992639 util/ifdtool: Fix eSPI frequency as per Gen 11 SPI flash guide
BUG=b:153888802
TEST=Able to list correct eSPI frequency as per TGL SPI flash guide

Without this CL :
Found Component Section
FLCOMP     0x093030f6
  Dual Output Fast Read Support:       not supported
  Read ID/Read Status Clock Frequency: 50MHz
  Write/Erase Clock Frequency:         50MHz
  Fast Read Clock Frequency:           50MHz
  Fast Read Support:                   supported
  Read Clock Frequency:                20MHz

With this CL :
Found Component Section
FLCOMP     0x093030f6
  Dual Output Fast Read Support:       not supported
  Read ID/Read Status Clock Frequency: 50MHz
  Write/Erase Clock Frequency:         50MHz
  Fast Read Clock Frequency:           50MHz
  Fast Read Support:                   supported
  Read eSPI/EC Bus Frequency:          60MHz

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I20840e6f931d7c1fabea0b6892e3bd19ead81168
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02 07:17:44 +00:00
Subrata Banik d16ef4d21e util/ifdtool: Fix SPI frequency as per Gen11 SPI flash guide
BUG=b:153888802
TEST=Able to list correct SPI frequency as per TGL SPI flash guide

Without this CL :
Found Component Section
FLCOMP     0x093030f6
  Dual Output Fast Read Support:       not supported
  Read ID/Read Status Clock Frequency: 33MHz
  Write/Erase Clock Frequency:         33MHz
  Fast Read Clock Frequency:           33MHz
  Fast Read Support:                   supported
  Read Clock Frequency:                20MHz

With this CL :
Found Component Section
FLCOMP     0x093030f6
  Dual Output Fast Read Support:       not supported
  Read ID/Read Status Clock Frequency: 50MHz
  Write/Erase Clock Frequency:         50MHz
  Fast Read Clock Frequency:           50MHz
  Fast Read Support:                   supported
  Read Clock Frequency:                20MHz

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Id0a0a0cbd948ef8334cf522c09e881b464e87f0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02 07:17:39 +00:00
Subrata Banik bd2da5a4b5 util/ifdtool: Add FLMAP3 dump for Gen11 onwards PCH
BUG=b:153888802
TEST=Able to dump FLMAP3 for Volteer platform with TGP
> ifdtool -d coreboot.rom

FLMAP3:      0x00000000
  Minor Revision ID:     0x0000
  Major Revision ID:     0x0000

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I681abd6ae7b87f6638d4f6dc59168cf22b93c787
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44818
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02 07:17:33 +00:00
Subrata Banik ac1b1dd83e util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH
This patch performs below operations:
1. Remove reserved NR field from Gen 5 onwards SPI programming guide
2. Convert ISL to PSL as applicable for Gen 5 onwards PCH
3. Skip FLMAP2 register dump due to nonuniformity since Gen 5 onwards PCH
4. Dump FLILL1 register as applicable for Gen 5 onwards PCH
5. Remove FLPB register as not applicable since Gen 5 PCH

BUG=b:153888802
TEST=Dump FD for Hatch platform as below
> ifdtool -d coreboot.rom

PCH Revision: 300 series Cannon Point/ 400 series Ice Point
FLMAP0:    0x00040003
  FRBA:    0x40
  NC:      1
  FCBA:    0x30
FLMAP1:    0x45100208
  PSL:     0x45
  FPSBA:   0x100
  NM:      2
  FMBA:    0x80

FLILL1     0xc7c4b9b7
  Invalid Instruction 7: 0xc7
  Invalid Instruction 6: 0xc4
  Invalid Instruction 5: 0xb9
  Invalid Instruction 4: 0xb7

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I5141ae5dd174659fde5401fac313a701ae4f8f44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02 07:17:25 +00:00
Subrata Banik 26058dca96 util/ifdtool: Identify between ICH and PCH Revision
Consider IBEX_PEAK onwards all chipsets are belong to PCH family.

BUG=b:153888802
TEST=Able to print correct PCH revision on Hatch Platform.
> ifdtool -d coreboot.rom

Without this CL :
ICH Revision: 300 series Cannon Point/ 400 series Ice Point

With this CL :
PCH Revision: 300 series Cannon Point/ 400 series Ice Point

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ifd40dddc9179f347c0ea75149ec08089a829fdb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02 07:17:16 +00:00
Subrata Banik 89db2255d0 util/ifdtool: Identify chipset without platform name
Able to uniquely identify the chipset without specifying the platform
specific quirks (adl/cnl/icl/jsl/tgl etc.).

BUG=b:153888802
TEST=Able to dump FD contains correctly without specifying platform
quirks on Hatch Platform.

> ifdtool -d coreboot.rom

Without this CL :
ICH Revision: 100 series Sunrise Point

With this CL :
ICH Revision: 300 series Cannon Point/ 400 series Ice Point

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I83763adb721e069343b19a10e503975ffa6abb24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44815
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31 06:57:42 +00:00
Subrata Banik d52df3cd84 util/ifdtool: Skip unused and reserved Flash Region
This patch ensures all unused and reserved flash region sections are not
getting listed while using -d option to dump FD.

BUG=b:153888802
TEST=List only used flash region section with below command
> ifdtool -p tgl -d coreboot.rom

Without this CL :
Found Region Section
FLREG0:    0x00000000
  Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
FLREG1:    0x1fff0400
  Flash Region 1 (BIOS): 00400000 - 01ffffff
FLREG2:    0x03ff0001
  Flash Region 2 (Intel ME): 00001000 - 003fffff
FLREG3:    0x00007fff
  Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
FLREG4:    0x00007fff
  Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
FLREG5:    0x00007fff
  Flash Region 5 (Reserved): 07fff000 - 00000fff (unused)
FLREG6:    0x00007fff
  Flash Region 6 (Reserved): 07fff000 - 00000fff (unused)
FLREG7:    0x00007fff
  Flash Region 7 (Reserved): 07fff000 - 00000fff (unused)
FLREG8:    0x00007fff
  Flash Region 8 (EC): 07fff000 - 00000fff (unused)

With this CL :
Found Region Section
FLREG0:    0x00000000
  Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
FLREG1:    0x1fff0400
  Flash Region 1 (BIOS): 00400000 - 01ffffff
FLREG2:    0x03ff0001
  Flash Region 2 (Intel ME): 00001000 - 003fffff
FLREG3:    0x00007fff
  Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
FLREG4:    0x00007fff
  Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
FLREG8:    0x00007fff
  Flash Region 8 (EC): 07fff000 - 00000fff (unused)

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I900a29d8968bd61d66c04012e60e1ba4baff786d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-31 06:57:29 +00:00
Subrata Banik 15da174652 util/ifdtool: Add platform specific quirks for ADL/ICL/JSL/TGL
BUG=b:153888802
TEST=Able to dump FD contain using below command
> ifdtool -p tgl -d coreboot.rom

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I0c9106051f4daf592d2467ebf79f9ddb037011dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-31 06:56:53 +00:00
Elyes HAOUAS 796c567b1c lint/lint-extended-007-checkpatch: Remove obsolete path
Change-Id: I8a91d2a8bc6a1fa709aeadd3b7482d1785068276
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-31 06:40:55 +00:00
Elyes HAOUAS 668132a47c {intel/gma,include/device}: Delete unused 'drm_dp_helper.h' file
'drm_dp_helper.h' file is duplicated and not used.

Change-Id: Ibb08f7ff91c3914940dfe899be331b06e292c7c9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-31 06:36:18 +00:00
Karthikeyan Ramasubramanian cb5961d148 cross-repo-cherrypick: Do not prepend "Original-" to "Cq-Depend:"
Marking dependencies has undergone some change in Chrome OS tree. The
script to cherry-pick the changes to ChromeOS tree prepends "Original-" to
the concerned meta data i.e. Cq-Depend becomes Original-Cq-Depend. This
causes dependencies to not take effect when changes are submitted to the
continuous integration. Do not prepend "Original-" to the dependency
meta data.

BUG=None
TEST=Ensure that the Cq-Depend line is added without any prefix.

Change-Id: I0503234954f872ee56708e19e89cae9d9fa30df7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-31 06:33:56 +00:00
Matt DeVillier 62e883d73b util/inteltool: Add support for Comet Lake-U
Add support for 10th-gen/Comet Lake-U based boards:
- add PCI IDs for host bridge, IGD, LPC devices
- add support for dumping GPIOs, PCRs, etc

Tested on an unbranded CML-U board running AMI firmware

Change-Id: I44871917565fc628fd1073a6e5c36b6a3246a61c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-29 13:41:04 +00:00
Rob Barnes 8283ae6bab util: Add memory parts needed by zork boards
Add memory parts needed by zork boards. Attributes are derived from data
sheets.

BUG=b:162939176
TEST=Compared generated SPDs with data sheets and checked in SPDs

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I67f205f9af24bbc5c12656be1f363a15fe975955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44447
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 14:29:44 +00:00
Nick Vaccaro 913ea9278f util/gen_spd: translate DeviceBusWidth to die bus width
If a memory part is a x16 part that has two dies and only a single
rank, then the x16 describes the part width (since this solution will
need to be a stacked solution) and as such, we must translate the
DeviceBusWidth to the "die bus width" instead.

Change DeviceBusWidth variable name to PackageBusWidth to be more
descriptive

BUG=b:166645306, b:160157545
TEST=run gen_spd and verify that spds for parts matching description
above changed appropriately.

Change-Id: Ia6f3ca109d344b7a015da28125a94ce10d2bdfb8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-28 14:20:30 +00:00
Aaron Durbin 0245f43bcd Revert "util: update lp4x gen_part_id tool to include memory type"
This reverts commit eb7a1dd80e.

MEMORY_TYPE = lines in Makefiles are not longer needed. Drop it.

Change-Id: I96ac39a30555a870e7778a0e71d738407b6b89ef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44895
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 05:01:31 +00:00
Rob Barnes a662648a7f util: Add support to spd_tools for fixed id
For boards that have already assigned memory ids, there needs to be a
way to fix parts to a specific id. After assigning all the fixed ids the
tool still attempts to minimize the SPDs entries. Since a fixed ID could
be anywhere, gaps can be created in the list. So an empty SPD entry is
created to fill the gaps in the list until they are used.

BUG=b:162939176
TEST=Generate various outputs

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1f8ea1ff4f33a97ab28ba94896a1054e89189576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-28 04:36:55 +00:00
Nick Vaccaro 48fc1640a8 util: volteer/dedede: move generic SPDs to common location
Now that generic SPD files have the memory type prepended to the
filename, they can be stored in the same location.  This CL moves
the generic SPDs to the new location.

Change the ddr4 gen_part_id.go and gen_spd.go tools to use
"ddr4_spd_manifest.generated" instead of "spd_manifest.generated".

Change the lpddr4x gen_part_id.go and gen_spd.go tools to use
"lp4x_spd_manifest.generated" instead of "spd_manifest.generated".

Move TGL DDR4 and LPDDR4x generic SPDs into a common location.

Move JSL DDR4 and LPDDR4x generic SPDs into a common location.

Change the volteer/spd/Makefile.inc to use the new path for the spds.

Change the dedede/spd/Makefile.inc to use the new path for the spds.

BUG=b:165854055
TEST="emerge-volteer coreboot" and verify all variants build correctly.

Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 04:35:56 +00:00
Rob Barnes c19140b49f util: Add check for duplicate entries in mem parts json
Check for duplicate entries in mem parts json file.

BUG=b:162939176
TEST=Verified that tool throws error when there is a duplicate.

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I7c638c7938958727cfc832e7b4556acbc04b0ca4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44478
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27 22:39:32 +00:00
Rob Barnes 8cc80d5e50 util: Add Picasso and Pollock platforms to spd_tools
PCO = Picasso
PLK = Pollock

BUG=b:162939176

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I43b74f68871062112f53fbbef8a170db53734b3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44477
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27 21:41:30 +00:00
Rob Barnes a2e431331c util/spd_tools: Support comments in json
Allow comments in json file for better documentation. Comments must be
on seperate line.

BUG=none
TEST=Injest global_ddr4_mem_parts.json.txt with comments

Change-Id: I51295408d4f916708e4ed5bc42d5468ccdc68a6b
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-27 21:41:18 +00:00
Rob Barnes 196e9c0021 util/spd_tools: Remove intel subfolder
Move ddr4 and lp4x to spd_tools root folder. The tool now applies to non
intel platforms.

BUG=b:162939176
TEST=Run tool

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I0941ea036d760ee27eb34f259f4506a4b7584bee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44844
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27 20:14:34 +00:00
Nick Vaccaro eb7a1dd80e util: update lp4x gen_part_id tool to include memory type
Add "MEMORY_TYPE = lp4x" to the generated Makefile.inc to indicate
this is lpddr4x memory and to use the generic SPDs from the lpddr4x
respository of SPDs.

BUG=b:160157545
TEST=run gen_part_id for volteer and verify that it adds the line "MEMORY_TYPE =
lp4x" to the makefile produced.

Change-Id: I416690ae8aff8052474b16ef0d3e940e72e6a2fb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-25 18:27:59 +00:00
Nick Vaccaro 90aeb4d1b5 util: Add spd_tools to generate DDR4 SPDs for TGL boards
Serial Presence Detect (SPD) data for memory modules is used by Memory
Reference Code (MRC) for training the memory. This SPD data is
typically obtained from part vendors but has to be massaged to format
it correctly as per JEDEC and MRC expectations. There have been
numerous times in the past where the SPD data used is not always
correct.

In order to reduce the manual effort of creating SPDs and generating
DRAM IDs, this change adds tools for generating SPD files for DDR4
memory used in memory down configurations on Intel Tiger Lake (TGL)
based platforms. These tools generate SPDs following JESD79-4C and
Jedec "4.1.2.L-5 R29 v103" specification.

Two tools are provided:
* gen_spd.go: Generates de-duplicated SPD files using a global memory
  part list provided by the mainboard in JSON format. Additionally,
  generates a SPD manifest file (in CSV format) with information about
  what memory part from the global list uses which of the generated
  SPD files.

* gen_part_id.go: Allocates DRAM strap IDs for different DDR4
  memory parts used by the board. Takes as input list of memory parts
  used by the board (with one memory part on each line) and the SPD
  manifest file generated by gen_spd.go. Generates Makefile.inc for
  integrating the generated SPD files in the coreboot build.

BUG=b:160157545

Change-Id: I263f936b332520753a6791c8d892fc148cb6f103
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-25 16:48:02 +00:00
Elyes HAOUAS 9618706da6 crossgcc: Upgrade MPC to version 1.2.0
Change-Id: I8b754c2bbb18e38d2f8619f6ac8e1544702836ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44551
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24 09:13:44 +00:00
Patrick Georgi 0d431acf6c util/abuild: Don't pass kconfig output through head
Closing stdout early seems to have a detrimental effect on kconfig on a
system under high load (e.g. when doing lots of builds in parallel).

Change-Id: I6987f1deac596124c7b397bf7bc5a78d691cc538
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-08-24 09:08:21 +00:00
Patrick Georgi c01a49fb3f util/abuild: Delete temporary config in failure case
Change-Id: I9b6e6b6dcfbf2b1f43c98027acae8d9af61bd6d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44624
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24 09:06:42 +00:00
Martin Roth 48dd9fe21f util/amdfwtool: Refactor APOB_NV requirements
amdfwtool currently assumes that we MUST have an apob_nv area if we
have an aopb.  This is not required, so if neither the apob_nv size or
base are specified, just move on.

BUG=b:158363448
TEST=Build an image with no APOB_NV region.  Dump regions to show that
it's not there.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibaeacd3dcdfd73f690df61c2a19d39bbb9dcc838
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44045
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21 18:46:58 +00:00
Patrick Georgi 942c199341 util/abuild: Avoid another git submodule invocation
.xcompile is generated before the submodules handling, but there's no
need for the submodules to be around, so skip here, too.

Change-Id: I60205f65b124a09067de5ae50f066b5cf64733f2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-08-19 20:21:33 +00:00
Elyes HAOUAS 8f1853c4b0 crossgcc: Upgrade LLVM to version 10.0.1
Change-Id: I1d96654fd66a5972c6c5cc24311ca2d889866331
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39921
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18 13:50:02 +00:00
Elyes HAOUAS 9c69369805 crossgcc: Upgrade CMake to version 3.18.1
Release Notes:
  https://cmake.org/cmake/help/v3.18/release/3.18.html

Change-Id: I20b75b7c29be838c3c168547bcab25ea5c1af462
Signed-off-by: Griffin98 <griffin98@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-18 11:43:29 +00:00
Matt DeVillier 5eeead2d73 util/intelp2m: Add support for Cannonlake-LP SoCs
Add support for Cannonlake-LP SoCs (Whiskeylake-U,
Coffeelake-U, Cometlake-U) as a separate parsing profile,
copying the existing 'Sunrise' profile and adjusting for differences
in reset mapping and GPIO macro generation

Test: convert inteltool GPIO log dump into coreboot macros for
an out-of-tree CML-U board.

Change-Id: I86296697ee892af7aa0818fb608b6d68fad2f307
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-08-18 08:49:27 +00:00
Harshit Sharma ac8e1062cb crossgcc: Enable GCC to get asan shadow offset at runtime
Unlike Linux kernel which has a static shadow region layout, we have
multiple stages in coreboot and thus require a different shadow offset
address. Unfortunately, GCC currently only supports adding a static
shadow offset at compile time using -fasan-shadow-offset flag.

For this reason, we enable GCC to determine asan shadow offset address
at runtime using a callback function named __asan_shadow_offset().
This supersedes the need to specify this address at compile time. GCC
then makes use of this shadow offset to protect stack buffers by
inserting red zones around them.

Some other benefits of having this GCC patch are:
a. We can place the shadow region in a separate linker section with
   all its advantages like automatic fit insurance. This ensures if
   a platform doesn't have enough memory space to hold shadow region,
   the build will fail. (However, if we use a fixed shadow offset on a
   platform that actually doesn't have enough memory, it may still
   build without any errors.)
b. We don't modify the memory layout compared to the current one, as
   we are placing the shadow region at the end of the space already
   occupied by the program.
c. We can be much more flexible later if needed (thinking of other
   stages like bootblock).
d. Since we are appending the shadow buffer to the region already
   occupied, we make efficient use of the limited memory available
   which is highly beneficial when using cache as ram.

Further, we have made sure that if you compile you tree with ASan
enabled but missed this patch, it will end up in the following
compilation error:
"invalid --param name 'asan-use-shadow-offset-callback'"
So, you cannot accidentally enable the feature without having your
compiler patched.

Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-17 09:03:19 +00:00
Elyes HAOUAS d592909014 crossgcc: Upgrade IASL to version 20200717
Summary of changes: https://acpica.org/node/183

Change-Id: Ib325fa5c37c32702c572ab56c99e1f8f785cbe53
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-17 07:07:33 +00:00
Elyes HAOUAS 384e2c9218 crossgcc: Upgrade Python to version 3.8.5
Change-Id: I660994ece28f04d97de2fe3a074ebcf93fb4d2f4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39148
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:05:56 +00:00
Elyes HAOUAS 2574590f8c crossgcc: Upgrade nasm to version 2.15.03
Change-Id: I4b38595cef72053f82216df43f3667abed4c1989
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42855
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:05:36 +00:00
Elyes HAOUAS a15a7a5c13 crossgcc: Upgrade binutils to version 2.35
Using "MAKEINFO = @MAKEINFO@", it fails to compile, so
binutils-2.35_no-makeinfo.patch will change that to "MAKEINFO = true"

Change-Id: I0ad01e5da34c96fee6a9b1a63897a9fb28471c75
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38666
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:05:11 +00:00
Elyes HAOUAS 150c438334 crossgcc: Update MPFR to version 4.1.0
Changes: https://www.mpfr.org/mpfr-current/#changes

Change-Id: I1df2c952229056b44d4c618cebe774ea27b55bd1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43360
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:04:14 +00:00
Elyes HAOUAS e541268b0a crossgcc: Upgrade GMP to v6.2.0
gmp_freebsd-configure.patch is integrated in upstream so we don't need
it anymore.
Changes: https://gmplib.org/gmp6.2

Change-Id: I8404872f1b65e9173c1fcbd24d7da7bdd7937503
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38465
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:03:11 +00:00
Subrata Banik 46f8073249 util/ifdtool: Add Alderlake platform support under IFDv2
Change-Id: Ief8ab6ad280d8a2625404c19d57cd2a24f23cf13
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39533
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-01 06:55:25 +00:00
Subrata Banik a717e2f896 util/ifdtool: Make JSL platform entry for lock_descriptor
Change-Id: Ia2ddb4eceab29810b22766a0f241ba4b11e79538
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44057
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-01 06:54:51 +00:00
Rob Barnes ce036bd176 util/apcb: Strip SPD manufacturer information
Strip manufacturer information from SPDs before injecting into APCB.
This allows more flexibility around changing DRAM modules in the future.

BUG=b:162098961
TEST=Boot, dump memory info

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1bbc81a858f381f62dbd38bb57b3df0e6707d647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-29 09:35:05 +00:00
Maxim Polyakov 82ec61e9d7 util/intelp2m: Add Intel Pad to Macro utility
This patch adds a new utility for converting a pad configuration from
the inteltool dump to the PAD_CFG_*() macros [1] for coreboot and GPIO
config data structures for FSP/sdk2-platforms/slimbootloader [2,3].
Mirror: https://github.com/maxpoliak/pch-pads-parser.git

[1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h
[2] https://slimbootloader.github.io/tools/index.html#gpio-tool
[3] 3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/GpioSampleDef.h

Change-Id: If3e3b523c4f63dc2f91e9ccd16934e3a1b6e21fa
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35643
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28 22:06:02 +00:00
Peter Lemenkov 21f01c5a53 intelvbttool: Fix some typos in error messages
Change-Id: Id6298883c39c21179b13696dab630818b81026ff
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43905
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28 19:20:05 +00:00
Martin Roth a020903307 util/lint/Kconfig_lint: Update Naked BOOL reference to error
The lint-stable makefile target only watches for errors in the Kconfig
file, so has not protected additional "Naked" references to BOOL type
Kconfig symbols from entering the tree.  Update it to an error so that
they can't continue coming into the codebase.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Icce2a9a627c4fbcaa220df18474cb8bfea8b2a8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-27 05:07:51 +00:00
Benjamin Doron 552ce003a5 util/inteltool/gpio_names: Make group and community titles consistent
Consistency is good for scripting and automation.
The lowercase "group" in Sunrise Point-LP, for example, was
breaking pattern matching used in intelp2m.

Change-Id: Iffa8a8ac9c17c5cbd8d7b838d9c703cae6a858b5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43068
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:48:48 +00:00
Paul Menzel 56642930ab mb/lenovo: Prepend EC event number with 0x to denote hex notation
Currently, the message below is printed, suggesting it’s decimal
notation:

    coreboot-4.12-1530-g7acbd5fc45 Sun Jul 19 07:47:58 UTC 2020 smm starting (log level: 7)...
    EC event 48
    GPI (mask 1000)

Prepend 0x, so it’s clear it’s hexadecimal notation.

    EC event 0x48

Use the command below change all places:

    git grep -l 'EC event %02x' | xargs sed -i 's/EC event %02x/EC event %#02x/'

Change-Id: I8d1e6434a0e550c5a19576f9f7fea05e7a812e49
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:40:16 +00:00
Rob Barnes 4d2db06ab5 util: Remove extra newlines in log messages
Print adds a newline implicitly. Simply remove the extra newlines.

BUG=None
TEST=Build zork, observe build log

Change-Id: Idb150c12c90719ba1465e7e7fe45c26d456e2a1c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43786
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:16:35 +00:00
Peter Lemenkov f04b262710 autoport: Don't initialize already initialized fields in acpi_tables
Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already. Also add some comments.

See also these commits:

* Commit a76cf28 with Change-Id
  I2ccf4699ba3ed3f5b9402c0340153d4a5bf82682 ("mb/lenovo/*/acpi_tables:
Don't initialize already initialized fields").
* Commit 0c52638 with Change-Id
  I71f092ed7582b4931122d72f41d0b42a7569b96e ("mb/lenovo: Remove
thermal.h header").

Change-Id: I1a0042bc93a2b30babcb896b3df23faf37998f3c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40479
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:14:10 +00:00
Jan Dabros ffa58cfc12 util/lint: Add lint and checkpatch coverage for tests/ dir
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I8018b75844e630c9ed46c8bc48f2aa1634bf3369
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-07-26 21:11:05 +00:00
Matt Papageorge be4376c6c6 util/amdfwtool: Add support for EFS SPI values for F17h and F15h
The Embedded Firmware Structure contains various SPI parameters for
the PSP to program. This change adds support to amdfwtool for
populating these values as well specifying SOC Family and Model.

BUG=b:158755102
TEST=Read EFS values at appropriate offsets using a hex editor. Boot
test on Tremblye and Morphius.

Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9
Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:06:10 +00:00
Angel Pons a29f9e51b0 */mb/google/volteer/**/gpio.h: Fix up license header
There's a `GPL-2.0-or-later` version of this file in volteer2, so use it
in place of these weirdly-licensed files.

Change-Id: Icde2f6539d9c726d6967350f74e7bc015e01e7b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-26 20:55:19 +00:00
Elyes HAOUAS e65280cbef autoport/bd82x6x.go: Remove generated extra line
Change-Id: I48125b7efd599b6a6718d7353156217df874d490
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25 01:16:58 +00:00
Tim Wawrzynczak ac2282e907 util/mb/google/volteer: Delete dptf.asl
Since we are not using raw ASL files anymore for DPTF, delete the
template file too, so that it does not keep getting added for new
board variants.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia128989c64b8c02759c326431b4ee30fd2b483e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-24 23:27:39 +00:00
Maxim Polyakov de7092b8a3 inteltool/gpio: Add support for new Lewisburg chipsets
- Add SKUs and Super SKUs of new Lewisburg series chipsets:
  C621A, C627A, C629A [1].
- These changes allow the utility to generate the GPIO config
  registers dump.

[1] https://review.coreboot.org/c/coreboot/+/40395

Change-Id: I9b63c0a3860a901e58af0c0d5184361661bab5e3
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43534
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 16:40:48 +00:00
Maxim Polyakov ec0551c6b0 util/inteltool: add missing L0 and L1 pads for Lewisburg
The description for L0 and L1 was missed in the datasheet, however,
configuration registers for these pads are present. In addition, the
chipset contains the "GPP_L0/CSME_INTR_IN" and "GPP_L1/CSME_INTR_OUT"
pads in a circuit diagram. Use all available information to add a
description for the missed pads.

Change-Id: I7a0488c26b3df9de1adc037d94ae290837d65dd8
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40044
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 16:39:14 +00:00
Paul Fagerburg 31b7d95350 util/mb/google: add template files for dalboz and trembyle
Now that Zork is using upstream coreboot, we need the template files
in the main branch.

BUG=b:157570490
TEST=n/a

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I6cab4ab0b414473e0a759dce81df9872a40d3f26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43419
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15 20:45:03 +00:00
Paul Menzel df5571dc9d util/board-status: Reject logs with unknown timestamps
Check the output of `cbmem -t` for unknown timestamps. If present, ask
the user to rebuild `cbmem`.

Change-Id: Ief7aa1a698f10d9721964ad1bee057fcd9f4aa40
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-15 12:31:46 +00:00
Evgeny Zinoviev 7c1fe4bd12 util/intelmetool: Fix error message
Add a missing space to the message.

Change-Id: I7d4042ebb587af8558294fb4961100b43910fd4a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-07-15 08:33:55 +00:00
Idwer Vollering 66dcda9e15 util/inteltool: add PCI ID for ICH10DO
Change-Id: I3561679ef50f4c094d2503539074c957f759ecef
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43321
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09 21:54:33 +00:00
Patrick Georgi 793bf7e605 util/xcompile: Look for the host compiler in XGCCPATH, too (and first)
If there's a host compiler in XGCCPATH, it's likely the same
relatively-current version we use for coreboot, and it's a well-known
quantity, so let's prefer that over alternatives by default.

In addition, look for the C++ host compiler as well.

Change-Id: If50341df169a476899b5a5ffd4c4fb6d21c3f4ac
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43144
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 08:53:41 +00:00
Patrick Georgi f2741aa632 util/crossgcc: Always bootstrap for gcc < 4.9
Building cbfstool requires at least 4.9 due to optimizer bugs in gcc
3.x to 4.8.x, so let's not work around ancient compilers in our tree
but ensure that users get a newer compiler.

Closes: https://ticket.coreboot.org/issues/240
Change-Id: I4e0f80e2790514e6a1b5d5de1a373f365df1569c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43143
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 14:45:40 +00:00
Benjamin Doron c01fa5ad5d util/inteltool: Support dumping more BARs on Skylake mobile SoCs
Support dumping MCHBAR, EPBAR, DMIBAR and PCIEXBAR on SKL-U/Y.
These chipsets are similar to others supported by the tool.

Working on SKL-U.

Change-Id: Ic43d54ef189d500701872a56e67781a744990328
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-07 08:56:13 +00:00
David Wu d964fea5a6 lp4x: Add new memory parts and generate SPDs
This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL:
1. MT53E512M64D4NW-046 WT:E
2. MT53E1G64D8NW-046 WT:E

BUG=b:159195585,b:152936481,b:156435028
TEST=build.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-07-07 04:18:55 +00:00
Patrick Rudolph 7d28f20051 pgtblgen: Update comment to match what the code does
Change-Id: Ib87c804b139a96a4173a6f392f0f99a77d32fc01
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-06 17:24:59 +00:00
Kyösti Mälkki b2a10f8264 devicetree: Remove weak declarations for ops
Make it compulsory to build with all the drivers that are
visible in the board devicetree.cb file.

Change-Id: Ifb783e2f733d5c65c615e5c1879e3e4c7a83e049
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-06 16:11:02 +00:00
Edward O'Callaghan d0089c2b07 util/tmpl/puff: Allow USB2/3 wakeups to (un)plug events
BUG=b:159187889
BRANCH=none
TEST=none

Change-Id: Ib59108ec42955b5414f76b591cce5073f7dad1a9
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42990
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 00:02:55 +00:00
Patrick Georgi 8edfddcb54 util/futility: Check for pkg-config and libcrypto
When building a configuration that requires futility (e.g. Chrome OS
builds), pkg-config and libcrypto are required. Since vboot's build
system isn't the most helpful about it, test ourselves and fail out
with some actionable message.

Tested:
 - configs that don't need futility don't test for pkg-config, so it's
   not required for them.
 - failing pkg-config test leads to the message
 - working pkg-config test leads to a successful build

Fixes https://ticket.coreboot.org/issues/242

Change-Id: I103ce5115284352e0a3a7fdcf8b427f56ce15ba7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-01 18:12:05 +00:00
Patrick Georgi c6dd4435d2 util/cbfstool: Defuse vboot's openssl linking
Vboot determines openssl through pkgconfig, so pointing its build
system to /bin/true makes the build not break unless it needs to use
valid information about openssl.

Vboot's use of openssl is only for some special features, mostly around
PKCS key format parsing and not needed by cbfstool. While cbfstool
can link vboot, it can't link with openssl because openssl's license
is deliberately incompatible with the GPL.

Change-Id: Ia3825f9625a1964d7cefc47ab3c3a8250ceefafb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-07-01 18:06:16 +00:00
Elyes HAOUAS 157851fdbb crossgcc: Upgrade IASL to version 20200528
Update fixes build issues with host GCC 10.

Other changes:
  https://acpica.org/node/177
  https://acpica.org/node/178
  https://acpica.org/node/179
  https://acpica.org/node/181

acpinames utility removed:
"Removed support for the acpinames utility. The acpinames was a simple
utility used to populate and display the ACPI namespace without executing
any AML code. However, ACPICA now supports executable opcodes outside of
control methods. This means that executable AML opcodes such as If and
Store opcodes need to be executed during table load. Therefore, acpinames
would need to be updated to match the same behavior as the acpiexec
utility and since acpiexec can already dump the entire namespace (via the
'namespace' command), we no longer have the need to maintain acpinames."

Change-Id: Ibd995561ca53458b04f87cee5693850c0d90d3d6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38907
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01 12:28:41 +00:00
Kyösti Mälkki 0c1dd9c841 ACPI: Drop typedef global_nvs_t
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.

Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30 09:19:10 +00:00
Julius Werner bc1cb38ce1 Add qc_blobs repository
This patch adds a separate blobs repository for Qualcomm blobs,
analogous to the existing AMD blobs. Qualcomm's binary licenses allow
files to be redistributed and used by anyone, but they explicitly
require the user to agree to the license terms when just *downloading*
the binary (even if they're not using them to build any firmware). Some
community members do not like to have to agree to licenses for files
they're not actually using, so we are keeping these files separate from
the main blobs repository and adding an extra Kconfig to make sure the
user is aware of and must explicitly agree to this before downloading
these files.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I247746c1b633343064c9f32ef1556000475d6c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-30 08:57:03 +00:00
Stefan Reinauer 88e54e38d4 Fix up Docker paths to match jenkins nomenclature
Jenkins is calling its build nodes "agent". Reflect that in
the path names we use in configuration.

Change-Id: I88a4d3d32a565ade768e3de6428f46d355bedfb2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42819
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26 18:56:48 +00:00
Patrick Georgi b9d0c0f7a3 util/abuild: Only update submodules once
Without this, each build will try to update the submodules. Not
necessarily a problem but git locks repos, creating spurious error
messages.

Change-Id: Iba20677d4b5f9365c92f7ed247ca56acb7d33b27
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-25 16:59:19 +00:00
Zhuohao Lee 36aaddf7d7 util/mainboard/google/volteer: Add dptf.asl to the template
The dptf.asl is needed when creating a new volteer variant, otherwise,
it will make the variant build failed. The error could be found from
this link: https://review.coreboot.org/c/coreboot/+/42709

BUG=b:158797761
TEST=Generate the Delbin correctly

Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Change-Id: Ib4059df9e08d6a1dba88f0299bb39c8c6ae406ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-24 05:07:27 +00:00
Edward O'Callaghan 5d33d03d3f util/mb/google/tmpl/puff: Fix overridetree.cb to swap USB ports
Switch USB2 port1 and port3 due to circuit change from rev0.

BUG=b:154071868,b:154585046,b:156429564
BRANCH=none
TEST=none

Change-Id: I5b9a20bd657ed587ec891e52f66629d554df6166
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 01:15:14 +00:00
Edward O'Callaghan b6737fc54a util/mb/google/tmpl/puff: Import overridetree.cb copy
BUG=b:154071868
BRANCH=none
TEST=none

Change-Id: I40faa5f80e78cd73ba5ef977574f7f662c0ab8a1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 01:13:12 +00:00
Edward O'Callaghan 4229dfc215 util/mb/google/tmpl/puff: Generate correct gpio muxing
BUG=b:154071868
BRANCH=none
TEST=none

Change-Id: Iae4fe48b6a3df730b2334cb1f32b35addc90bec0
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 00:06:56 +00:00
Edward O'Callaghan 6ceca5d064 util/mb/google/tmpl/puff: Fix include paths for gen board
BUG=b:154071868
BRANCH=none
TEST=none

Change-Id: Ifa5cd021ae37d61ddb9eb9bf6a970a931058e33c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 00:06:43 +00:00
Elyes HAOUAS a138366f3a src/mainboard: Remove unused include 'sandybridge.h'
Change-Id: I9356a56c34d1c6746cf8acfe931386ffed58ba74
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22 16:30:48 +00:00
Stefan Reinauer 57ead89356 lint: convert checkpatch_json.py to python 3
Align all coreboot scripts on one python version.

Tested by running the original suggested test:
 $ nice -n 20 git diff HEAD~ | util/lint/checkpatch.pl \
     --no-signoff -q - | tee checkpatch.txt
 $ util/lint/checkpatch_json.py checkpatch.txt \
     comment.json checkpatch.txt

Change-Id: Iec2bb0be23b27a3eaf92f293c962a8e6bfb03af0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-06-18 08:30:47 +00:00
Elyes HAOUAS a0eb64ad33 crossgcc: Upgrade GDB to version 9.2
Change-Id: I30dae356ec3b373ac036c7eced7d6e89ddd08246
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38787
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 16:32:05 +00:00
Elyes HAOUAS 91fb139956 crossgcc: Remove "Make"
In its current state, it draws more dependencies in than it solves
which makes it useless.

Change-Id: I08f592731c3da2ac19e1f93682256f559a067fc4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-17 11:20:30 +00:00
Patrick Rudolph 802cbee789 ifdtool: Improve PCH strap handling
Read the PCH Strap Length field in FLMAP1 as described in the
"SPI Programming Guide" and print the number of fields specified there.

This code dumps the following straps:
* Intel GM45: 8 straps
* Intel C216: 72 straps
* Intel C240: 360 straps

Add a new function to easily set PCH straps, which is useful for debugging.

Change-Id: Ieb7891b214d82c984379794de9b3fe1a6d0d3466
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-17 09:16:51 +00:00
Angel Pons d71754d1b9 sandybridge boards: Factor out MAX_CPUS
Also update autoport accordingly.

Change-Id: I12481363cf0e7afc54e2e339504f70632e8d72e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41839
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 22:49:23 +00:00
Kyösti Mälkki c36469e0b1 util/cbfstool: Add option --pow2page
For add-stage command, --pow2page is equivalent of passing
-P log2ceil(sizeof stage). The sizeof stage can be hard to
determine in Makefile to be passed on the commandline.

Change-Id: If4b5329c1df5afe49d27ab10220095d747024ad6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-15 18:34:27 +00:00
Paul Menzel 2c4866228e util/board_status: Also check remotely retrieved coreboot console log
Currently, the logs are only checked, if retrieved locally. Moving it
after the if statement, now logs retrieved remotely are also checked.

The change in behavior is, that now all commands are executed first, so
before hitting this error, other errors might occur unrelated to the
console log.

Change-Id: I016bbde66c58a654042ad880c6007ddc1d143691
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-14 16:44:05 +00:00
Matt DeVillier 3380faa283 util/intelmetool: Add support for Intel Cannon Point LP HECI Controller
Tested on Intel NUC 8i5BEH (CFL) and Purism Librem Mini (WHL)

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I1054455fff2dcae8d17afe2adf3329eb44aa862a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-14 16:42:47 +00:00
Furquan Shaikh c3bb6923bd util/cbfstool: Drop IS_TOP_ALIGNED_ADDRESS() check in cbfstool_convert_fsp
This change drops the check for IS_TOP_ALIGNED_ADDRESS() before
setting offset to 0 in cbfstool_convert_fsp(). If the user provides a
baseaddress to relocate the FSP to, then the offset should be set to 0
since there is no requirement on where the file ends up in cbfs. This
allows the user to relocate the FSP to an address in lower DRAM.

BUG=b:155322763

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ibeadbf06881f7659b2ac7d62d2152636c853fb9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-13 06:49:50 +00:00
Nico Huber 91844b1f35 Revert "util/abuild: Have abuild generate the .xcompile if it doesn't exist"
This reverts commit 9ff4029db9.

Pulling the toplevel Makefile into a tiny one has all sorts of side
effects. For instance, the toplevel (random) .config is also included
so the results depend on the board that is selected there. What finally
broke it is a line that is unconditionally printed for AMD Picasso
boards resulting in lots of lines like this:

  skipping LENOVO_W520 because we're missing compilers for		\
  (Adding PSP c7ce61492157d3237f679c4a40a08b79				\
  .../coreboot/3rdparty/amd_blobs/picasso/PSP/PspBootLoader_prod_RV.sbin)

While both issues, the random .config and amd/picasso, could be worked
around easily, it seems hard to predict what other pitfalls are lurking
in the Makefile inclusion. Also, the problem solved by its inclusion
can be fixed by a much simpler `make .xcompile`.

Change-Id: I2ff70f561d717eb30e5f3c06c83e83468e174ec5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-10 21:26:23 +00:00
Nico Huber ad9f8cf02d util/abuild: Ensure .xcompile exists
abuild requires the `.xcompile` file to be present already before it
runs any actual `make` builds that would generate it.

Change-Id: Ib485e7741b7700fa241c192e60900ae5f1d977f5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-10 21:26:13 +00:00
Paul Fagerburg b468d569f6 templates: remove Dedede and Volteer Makefile.inc
SPD sources for Dedede and Volteer are being auto-generated by SPD
tools now, and so we can remove SPD_SOURCES from Makefile.inc for
those templates. That makes Makefile.inc empty for those reference
boards, so remove Makefile.inc from the templates.

BUG=b:158492307
BRANCH=None
TEST=Create new variant of volteer, waddledee, and waddledoo, and
verify that we can still build the coreboot image.

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Iba5264384302300cc8d2256a6b43f3353770154a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42204
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 17:27:34 +00:00
Iru Cai 571eda609e crossgcc: Backport GNAT exception handler v1 patch
The GCC 10 GNAT toolchain uses a new exception handler ABI, so older
GNAT cannot be built with GCC 10. This patch backports the new
exception handler in libgnat to make GNAT able to be built.

The libgnat patch doesn't remove the old exception handler, so it can
still be built with older compilers.

The cross toolchain can now be built with GCC 10.1.0 in Arch Linux
(with the latest IASL in CB:38907 that can be built in Arch), and the
toolchain can build a working coreboot image with libgfxinit for HP
EliteBook 2560p.

The original and patched crossgcc built with Debian 10.4 GCC 8.3.0,
and the patched crossgcc built with Arch GCC 10.1.0 generate identical
coreboot images with `make BUILD_TIMELESS=1`.

Change-Id: I757158056bf4698d3c68715e026c226615bc70a1
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42158
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 09:44:50 +00:00
Martin Roth 9455474f1b util/amdfwtool: Add option for setting PSP/FW shared memory location
This tells the PSP where in main memory to copy the vboot workbuf.

BUG=b:152576063
TEST=Build sharedmem destination into AMDFW, verify shared memory
gets placed at that location.

Signed-off-by: Martin Roth <martin@coreboot.org>
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830
Original-Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08 14:19:24 +00:00
Martin Roth 37305e78fc util/amdfwtool: update to allow building in any location
For the verstage-on-PSP implementation, we need 2 additional copies
of the AMD firmware tables at non-standard locations.  These are
for RW-A & RW-B fmap regions.  This change allows us to build the
AMD firmware tables into those regions.

BUG=b:148767300
TEST=boot with psp_verstage, verify boot location

Signed-off-by: Martin Roth <martin@coreboot.org>
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534
Original-Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: I7f841db8617b953dc671a9c12576145f85263581
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-08 14:08:20 +00:00
Furquan Shaikh bcb4a77fb1 spd/lp4x: Set manufacturer part name to blank (0x20)
As per JEDEC spec, manufacturer part name should be set to
blank (0x20). This change updates gen_spd.go to set bytes 329-348 as
0x20 and regenerates SPDs for TGL and JSL.

Change-Id: I6af18d89afd7264cec7e54b38e95df83d55aa058
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42023
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08 06:42:19 +00:00
Furquan Shaikh 20ecf2268b lp4x: Add new memory parts and generate SPDs
This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL and JSL:
1. MT53E512M32D2NP-046 WT:E
2. K4U6E3S4AA-MGCR
3. H9HCNNNCPMMLXR-NEE
4. K4UBE3D4AA-MGCR

BUG=b:157862308, b:157732528

Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41989
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06 09:29:54 +00:00
Furquan Shaikh 4bd95295f1 util/spd_tools/intel/lp4x: Add a global list of LP4x memory parts
This change adds a JSON file (`global_lp4x_mem_parts.json.txt`)
containing global list of LP4x memory parts to live along with the spd
tools since the part information is not really any SoC or mainboard
dependent and comes directly from the part datasheet. It can be shared
by mainboards based on different platforms supported by the tools.

BUG=b:155239397,b:147321551

Change-Id: I9e2f98fc9c1c8a7f73c9a1bfab22c996de222a32
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41874
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06 09:27:59 +00:00
Furquan Shaikh 70001fe1f7 util: Add spd_tools to generate SPDs for TGL and JSL boards
Serial Presence Detect (SPD) data for memory modules is used by Memory
Reference Code (MRC) for training the memory. This SPD data is
typically obtained from part vendors but has to be massaged to format
it correctly as per JEDEC and MRC expectations. There have been
numerous times in the past where the SPD data used is not always
correct.

In order to reduce the manual effort of creating SPDs and generating
DRAM IDs, this change adds tools for generating SPD files for LPDDR4x
memory used in memory down configurations on Intel Tiger Lake (TGL)
and Jasper Lake (JSL) based platforms. These tools generate SPDs
following JESD209-4C specification and Intel recommendations (doc

Two tools are provided:
* gen_spd.go: Generates de-duplicated SPD files using a global memory
  part list provided by the mainboard in JSON format. Additionally,
  generates a SPD manifest file (in CSV format) with information about
  what memory part from the global list uses which of the generated
  SPD files.

* gen_part_id.go: Allocates DRAM strap IDs for different LPDDR4x
  memory parts used by the board. Takes as input list of memory parts
  used by the board (with one memory part on each line) and the SPD
  manifest file generated by gen_spd.go. Generates Makefile.inc for
  integrating the generated SPD files in the coreboot build.

BUG=b:155239397,b:147321551

Change-Id: Ia9b64d1d48371ccea1c01630a33a245d90f45214
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06 09:27:44 +00:00
Paul Fagerburg 6441ecceed util/mb/google: add templates for puff boards
Add template directory for the Puff reference board.

BUG=b:157701044
BRANCH=None
TEST=N/A

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: Ic81c663b92eeb1d39c2b425d331eb16812f58b7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
2020-06-04 15:52:45 +00:00
Patrick Georgi 3909908de8 util: Allow overriding gcc as default host compiler
BUG=chromium:1088209
TEST=emerge coreboot-utils (with patches to the ebuild) works

Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I25d237d048e417f4e412583031905ecf3614c431
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-06-04 08:11:48 +00:00
Duncan Laurie 47b7b3402b sconfig: Add support for firmware configuration
This change adds support to sconfig for generating the firmware
configuration field and option definitions in devicetree.cb.

In addition these fields and options can be used to probe for a device
and have that device be disabled if it is not found at boot time.

New tokens:
fw_config: top level token, table can be defined before chips
field: define field in the mask with the start and end bits
option: define option in a field with the value of the field
probe: indicate that a device should probe by field and option

Example:
fw_config
    field FEATURE 0 0
        option DISABLE 0
        option ENABLE 1
    end
end
chip drivers/generic/feature
    device generic 0 on
        probe FEATURE ENABLE
    end
end

Variants can add new fields and add new options to existing fields in
overridetree.cb but cannot redefine an existing option.

Devices can have multiple probe tokens, and the device will be considered
to be found if any of them return true.

The output from defining this field are:

1) the various fields and options will be added as macro constants to
static.h and can be used by fw_config for probing.
2) the probe entries will result in a list of fields/options to probe
that is added to the resulting struct device and handled by coreboot.

BUG=b:147462631

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I8aea63e577d933aea09e0d0b09470929cc96e0de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02 18:06:37 +00:00
Nico Huber 57bbcb3dff util/sconfig: Move default includes out of emit_chips()
This should make it easier to add more includes.

Change-Id: Ib4a25352901408c2b36de4972391df742a0d8037
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41744
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:20:43 +00:00
Nico Huber d09459fe30 util/sconfig: Refactor and fix add_register()
add_register() contained a duplicate check but only compared the new
key to the first (smallest in order) list member. Fix that and factor
the list handling out so it can be used by other functions.

Change-Id: I5a8346f36fa024351e1282c9681868ecf451b283
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41743
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02 07:20:12 +00:00
Paul Fagerburg af983db3f4 util/mb/google: add templates for dedede boards
Add template directories for the Waddledee and Waddledoo reference
boards of the Dedede baseboard.

BUG=b:157183582
BRANCH=None
TEST=N/A

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: Ida70a44097334991a93fec8f4933d7f6e39a187b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-02 03:30:26 +00:00
Patrick Georgi 95226b3e74 testing: Add unit tests to what-jenkins-does procedure
They're not added as a dependency, even though that should be possible,
because we want the build tests to run even when the unit tests fail.

Change-Id: Ia3391d7b289160178fa773dfd7b7c51c6ef77805
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28 09:47:56 +00:00
Paul Fagerburg c351f57dcc util/mb/google: remove zork template
The templates for the zork reference boards are still being actively
worked on in the trembyle-bringup branch. Remove the zork template
from the main branch to avoid confusion when trembyle-bringup is
merged.

BUG=b:157099580
BRANCH=none
TEST=N/A

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I0ff9de959c7b2646b90e68df05f0b2e9bdd60cf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-28 09:40:56 +00:00
Jacob Garber d2fea1ab21 util/lint: Check for SPDX identifiers by default
The majority of the codebase has been converted to use SPDX identifiers
now, so let's enforce those by default. The only exceptions are
src/include and src/lib, which are not being checked since many of the
files there do not have license headers at all. Files with custom
licenses that aren't covered by SPDX can be listed as exceptions at the
top of lint-000-license-headers.

Change-Id: Ie6642153793d5735c74c5950bc9e27ee7eecacbc
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41602
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28 09:38:03 +00:00
Patrick Georgi 02a1344921 docker/coreboot-jenkins-node: Add meson and ninja
Our jenkins instance is also used for flashrom, which can be built with
meson, a mode that we want to be able to test, so add that.

ninja can be used as a backend to both meson and cmake (which coreboot
will use to build cmocka for its unit tests) and may provide some
additional coverage. Plus it's tiny but fast.

Change-Id: If454164852303144eaa72c4071c03ee89e863318
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-28 05:41:30 +00:00
Raul E Rangel 030d214738 util/apcb: Use python3 for apcb_edit.py
The code was written on a workstation that has python
pointing to python3.

BUG=b:157140753
TEST=Built trembyle and was able to boot to the OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I181d87aad1ffb10e12f8ffd7513318f6d6bcbc3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41739
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27 19:19:12 +00:00
Jacob Garber 10999ea628 drivers: Use SPDX identifiers
Convert the remaining files in src/drivers to use SPDX identifiers.

int15.h and default_brightness_levels.asl did not have license headers,
but they were both copied from other GPL2 files, so they should be under
the GPL2 as well.

ne2k.c and drm_dp_helper.h are licensed under custom BSD-like licenses
that do not have an SPDX equivalent, so they are added as exceptions
to the license header lint.

Change-Id: I87fb1c637b8d11b0463f7c19f70b847413e14aed
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-25 22:19:21 +00:00
Rob Barnes 30ce0f383f util/amdfwtool: Fix MAX_PSP_ENTRIES value
Had to increase MAX_PSP_ENTRIES to accommodate the 16 APCBs we have
the ability to add.

BUG=b:150862063
TEST=Boot Trembyle
BRANCH=None

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I64eccfa28839768788f53327caf187a564842162
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2090323
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41580
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21 22:30:27 +00:00
Rob Barnes f836a234e2 util/apcb: Add apcb_edit tool
On the Picasso architecture, the PSP is responsible for setting up DRAM
before releasing the x86. The APCB (AGESA PSP Configuration Block)
contains multiple SPDs and the GPIO numbers used to select the correct
SPD. Since the source to build the APCBs is not public, it can't be
built as part of the coreboot build. To work around this problem, we use
a template APCB and inject the relevant information.

BUG=b:147042464

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I88a09743f8e8a184c47071ee5e417f5b6bdb7467
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2123799
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-18 07:40:47 +00:00
Philipp Bartsch 7f5f9331d1 util/cbfstool: fix buffer over-read
Fix unterminated array.

When looking for a type not specified in filetypes (cbfs.h:204), the
loop in lookup_name_by_type (cbfs_image.c:60) will run into a buffer
over-read.

Found-by: AFL++ 2.64d rev 1317433
Signed-off-by: Philipp Bartsch <phil@grmr.de>
Change-Id: Ib82bb92e82b09fa1e26b9ca34529ec7b98e8f7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41421
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:32:16 +00:00
Elyes HAOUAS 0aad0531dc util/autoport/bd82x6x.go: Drop unused includes
Change-Id: Ifc0bf18dedc112e346062e0e0e988ac102991bb8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40826
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:11:47 +00:00
Patrick Georgi 81a30ec3a7 util/release: Check that HEAD isn't used as reference
genrelnotes moves the tree between commits and so a relative location
like HEAD isn't stable. Since I ran into the HEAD issue while preparing
for two consecutive releases, let's guard against it.

Change-Id: I70c6812cdfe0d0671b3d653744a062d9920a2394
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41339
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:06:42 +00:00
Patrick Georgi d906b21e2e util/release: Improve reporting of required tools
genrelnotes checks for cloc, git and rename but only reported about
needing the first two, so mention `rename` in missing message.

Change-Id: If91d759fc68760fd89b98756ac5b19ac3589c197
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-18 07:06:22 +00:00
Raul E Rangel 3f3f53cd5e util/sconfig: Add LPC and ESPI buses
Picasso has an LPC and eSPI bridge on the same PCI DEVFN. They can both
be active at the same time. This adds a way to specify which devices
belong on which bus.

i.e.,
device pci 14.3 on  # - D14F3 bridge
	device espi 0 on
		chip ec/google/chromeec
			device pnp 0c09.0 on end
		end
	end
	device lpc 0 on
	end
end

BUG=b:154445472
TEST=Built trembyle and saw static.c contained the espi bus.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-12 20:12:17 +00:00
Iru Cai e6fb1344ed inteltool: fix dumping of Lynx Point LP and Wildcat Point PM registers
Currently inteltool uses the addresses and names of the PCH of
previous generations. It's wrong for Lynx Point LP and Wildcat Point.

The addresses and names of the I/O registers can be found in "Mobile
4th Generation Intel Core Processor Family I/O Datasheet" (Document
Number: 329003-003) for Lynx Point LP and "Mobile 5th Generation Intel
Core Processor Family I/O, Intel Core M Processor Family I/O, Mobile
Intel Pentium Processor Family I/O, and Mobile Intel Celeron Processor
Family I/O Datasheet" (Document Number: 330837-004) for Wildcat Point.

Change-Id: If6ba718ccff077aa89affec89018bd7923527466
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40273
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12 19:42:50 +00:00
Patrick Georgi 13c13623cf util/nvramtool: Remove license boiler plate from DISCLAIMER file, too
Change-Id: I7ce0f08efaddb07a5d5f484d313068e5db3c7e2e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41220
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11 19:40:01 +00:00