Introduce DDR One-Time-Training Support
Device reboots without training from second iteration
and also DDR training data is 32kb size, hence update
required in memlayout and to sync with upstream changes
the Fmap size even got bumped up.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4
Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
It supports the clock consumers for QUP, SDCC, PCIE, Display to be able
to configure & enable the desired clocks.
The clock driver also supports reset of subsystems like AOP and SHRM.
Also add support for Zonda PLL enable for CPU in common clock driver.
Refactor the SC7280 clock driver to use the common clock driver APIs.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50580
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set power limit values dynamically based on CPU TDP and PCI ID of SKU.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57035
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Get tdp value of CPU for different SKUs based on PKG POWER MSR.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I9fba0a64da2f1d79d633054dddd9fdf1d3d8e258
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Add GPIO IOMUX defines for the pins that are used in the mainboard code
which enables using the PAD_GPI and PAD_GPO macros.
TEST=Timeless build for APU2/3/4/5 results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie32df9ed2cb6a5670a29cff91e085a3585c8bcf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
southbridge/amd/pi/hudson uses the common GPIO bank access code from
soc/amd, but doesn't provide all functionality that would be needed to
use the full functionality. Add a Kconfig option that switches off some
functionality in the common SoC GPIO access code, so that more of the
functionality proviced by the common SoC GPIO code can be used in the
AMD binaryPI chipset and board code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56783
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mapping of the package GPIO numbers to the GPIO numbers on the GPIO
controller isn't a 1:1 one, so add a comment about that to avoid
confusion. Also change the comment style to match the style guide.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie30bf5483ea2e2516d7e3fdd21ea9338362e526e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Also remove the unused amdblocks/acpimmio.h include in gpio_ftns.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: If121941c8a6ba88913653192740997aeef426548
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56784
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Override DdiPortAConfig as MIPI DSI
BUG=b:192521391
BRANCH=None
TEST=Built test coreboot image and boot on bugzzy board
Change-Id: If308f9d69fea56176527e7b67f36b29c43adb525
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Make adding the FSP-T file to CBFS depend on both ADD_FSP_BINARIES and
FSP_CAR Kconfig options being set. The FSP_T_FILE Kconfig option depends
on both, so also check if both are selected in the Makefile where it
tries to add the FSP-T to the CBFS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id347336f2751c6d871f31d89c30a1222037c2d69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The clock driver supports configuring the general purpose PLLs,
configuring the root clock generator (RCG), enable clock branch, enable
gdsc and also the block resets.
The common clock driver exposes PLL configuration functions and also
different Agera PLL enable functions for the CPU PLLs.
While at it, the common driver also supports reset of subsystems like
AOP and SHRM.
SC7180 clock driver is also refactored to use the common clock
driver APIs.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
As we move to use the common clock driver, the sc7180 clock driver,
watchdog and display drivers requires few cleanups, thus update the
impacted drivers.
Earlier the display client is expected to provide 2n divider value,
as the divider value in register is in form "2n-1".
mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0;
The older convention in the upcoming patches would be replaced with
the common macro of QCOM_CLOCK_DIV, thus need the divider needs to
be updated.
mdss_clk_cfg.div = half_divider ? QCOM_CLOCK_DIV(half_divider) : 0;
To accommodate impacting the functionality, the half_divider is taken
care in the clock driver.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 development board
Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
CONFIG_DRIVERS_INTEL_MIPI_CAMERA and CONFIG_SOC_INTEL_COMMON_BLOCK_IPU
are getting selected for all ADLRVPs irrespective of ADL-P and ADL-M
(internal and external EC SKUs) hence, select those Kconfigs from
mainboard Kconfig rather Kconfig.name.
Also, select DRIVERS_INTEL_SOUNDWIRE as per alphabetical order.
TEST=No changes are seen while the .config file is getting auto
generated.
Change-Id: I62d5ec19c3364da79ebe7287b1b3d6eb2a0efca0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Set the `UserBd` FSP-M UPD to `BOARD_TYPE_DESKTOP` by default on PCH-H.
Remove now-redundant mainboard code to set the `UserBd` UPD.
Change-Id: I349abe5d89f562c158ce9baadbca2b2f56695846
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57261
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `DIMM_MAX` Kconfig symbol once.
Change-Id: I2e86baaa8bd50c7b82c399fde5dcea05da6b4307
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once.
Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
variant_has_pcie_wwan() was always coming back as disabled because
find_dev_nested_path() couldn't find the device until the domain was
added to the array.
BUG=b:193036827
TEST=Boot guybrush with PCIe & USB WWAN devices.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Id94fa0b0ff5c29fa447e869220d27ccfe61438c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The RW_MRC_CACHE only needs to be 64K for Brya.
BUG=none
TEST="emerge-brya coreboot chromeos-bootimage", flash and boot
brya0 to kernel.
Change-Id: I74365b795e184b92f483ae2bf862791e235c5362
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56989
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for DSM methods as per the connectivity document
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:191720858
TEST=Check the generated SSDT tables for DSM methods
Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add support for the WTAS ACPI BIOS configuration table as per the
connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:193665559
TEST=Generated SAR file with the WTAS related configuration values and
verified that the SSDT has the WTAS ACPI table.
Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add support for the PPAG ACPI BIOS configuration table as per the
connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:193665559
TEST=Generated SAR file with the PPAG related configuration values and
verified that the SSDT has the PPAG ACPI table.
Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Existing SAR infrastructure supports only revision 0 of the SAR tables.
This patch modifies it to extend support for intel wifi 6 and wifi 6e
configurations as per the connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
The SAR table and WGDS configuration block sizes were static in the
legacy SAR file format. Following is the format of the new binary file.
+------------------------------------------------------------+
| Field | Size | Description |
+------------------------------------------------------------+
| Marker | 4 bytes | "$SAR" |
+------------------------------------------------------------+
| Version | 1 byte | Current version = 1 |
+------------------------------------------------------------+
| SAR table | 2 bytes | Offset of SAR table from start of |
| offset | | the header |
+------------------------------------------------------------+
| WGDS | 2 bytes | Offset of WGDS table from start of |
| offset | | the header |
+------------------------------------------------------------+
| Data | n bytes | Data for the different tables |
+------------------------------------------------------------+
This change supports both the legacy and the new format of SAR file
BUG=b:193665559
TEST=Checked the SSDT entries for WRDS, EWRD and WGDS with different
binaries generated by setting different versions in the config.star
Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
GPIO PM was disabled for brya to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. All devices currently tested on brya support 4us
long pulses. This change drops the GPIO PM override and re-enables
dynamic GPIO PM.
TEST=Boot brya to OS, ensure no TPM errors.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0c7b66b5514d8b80775ab7578ce7b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56926
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It doesn't make sense to store the orientation field directly in the
panel information structure, which is supposed to be reuseable between
different boards. The thing that determines orientation is how that
panel is built into the board in question, which only the board itself
can know. The same portrait panel could be rotated left to be used as
landscape in one board and rotated right to be used as landscape in
another. This patch moves the orientation field out of the panel
structure back into the mainboards to reflect this.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If2b716aa4dae036515730c12961fdd8a9ac34753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57324
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Windows will write to the century byte (0x32), causing the option table
checksum to be invalid and reset all options to their default values.
Move options and checksum to start after the century byte.
Change-Id: Ia395acacda1e251251c880587bbf61d7ee81ba3d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
It turns out that putting a device ref in an overridetree at a different
point in the tree will generate a duplicate device definition, such that
the change introducing this support was ignoring the device presence
specified by overridetree.cb and only using the baseboard configuration.
I believe testing of that change was not redone after the baseboard was
changed to disable the MST, so that conflicting behavior was not
noticed.
The incorrect behavior generated a disabled device for the MST at the
location specified by the baseboard, and one with the probe as a child
of the soc. At runtime this did a fw_config probe of the "I2C 00:4a"
device, and later probed a different "I2C 00:4a" which was already
disabled. As the disabled one came later, it seems to have completely
disabled the MST, discarding the results of the variant-specific probe.
BUG=b:185862297
TEST=10EC2141 device is now present on a Dali berknip
BRANCH=zork
Change-Id: I2a8feb544f3fc198fe6313b226ad8995aad31c3e
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57298
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch is to fix "Not a usable UEFI firmware volume" issue when
creating CBFS/flash image. This issue is caused by adding FvNameGuid
in UefiPayloadEntry.fdf in EDKII. There is an ext header between header
of Fv and header of PayloadEntry in Fv with FvNameGuid. The ext header
causes the UefiPayloadEntry to be found incorrectly when parsing Fv.
Commit in EDKII: 4bac086e8e007c7143e33f87bb96238326d1d6ba
Bugzila: https://bugzilla.tianocore.org/show_bug.cgi?id=3585
Signed-off-by: Dun Tan <dun.tan@intel.com>
Change-Id: Id063efb1c8e6c7a96ec2182e87b71c7e8b7b6423
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57296
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds test case for lib/cbfs verification mechanisms.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I1d8cbb1c2d0a9db3236de065428b70a9c2a66330
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56601
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The new CBFS stack was written to try to isolate cases of single file
corruption as far as possible and still make other files avaialble (at
least as long as verification is disabled and they can still be found at
all). For most cases of header corruption, it will just continue trying
to parse the next file. However, in cases where parts of the file extend
beyond the end of the rdev, we have been relying on the range checking
of the rdev API rather than doing it explicitly.
This is fine in general, but it causes the problem that these errors
cannot be distinguished from I/O errors, and I/O errors always make the
whole cbfs_walk() fail. That means we will not return a successful
result from cbfs_mcache_build(), and leads to an odd discrepancy in how
certain kinds of corrupted CBFSes are treated with and without mcache.
This patch adds an explicit range check to make the behavior consistent.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ice2b6960284bd0c19be35b0607e5e32791e7a64c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
When running multiple tests, e.g. by using unit-tests target, it is hard
to differentiate, which output comes from which file and/or
configuration. This patch makes the output easier to analyze and
understand by using new wrapper macro cb_run_group_tests(). This macro
uses __TEST_NAME__ value (containing test path and Makefile test name)
as a group name when calling cmocka group runner.
Example:
Test path: tests/lib/
Makefile test name: cbmem_stage_cache-test
Test group array name: tests
Result: tests/lib/cbmem_stage_cache-test(tests)
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I4fd936d00d77cbe2637b857ba03b4a208428ea0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
On mainboards with Cezanne SOC, serial enabled FSP_M binary size is
greater than the size allocated in DRAM. Increase the allocated size for
FSP_M binary in DRAM to handle both debug and release FSP_M binaries.
Also adjust the verstage load address accordingly.
BUG=None
TEST=Build and boot to OS in guybrush with both debug and release FSP_M.
Perform warm, cold reboot and suspend/resume cycling for 10 iterations.
Change-Id: Ic6f90041e258039e691cbdb3a978cfe1f782642a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57293
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before this patch EXTRA_CFLAGS were placed before many other options.
This made overriding impossible even, when necessary. This patch moves
EXTRA_CFLAGS to be placed after original CFLAGS, thus making option
overriding possible.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: If8394b151696eee4bd736d2fb1ad340209e05fbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57181
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable this feature, and it can use the probe statement in devicetree
to cache of fw_config field as oem string.
BUG=b:191931762
TEST=With CBI FW_CONFIG field set to 0x8,
set probe AUDIO MAX98390_ALC5682I_I2S_4SPK in devicetree
dmidecode -t 11
OEM Strings
AUDIO-MAX98390_ALC5682I_I2S_4SPK
Change-Id: I93cd9ef2d1ad963e66c422cff17b083abf731046
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When the override functionality looks for device match, check that
the probe list for both the devices matches exactly if probe list
exists for the base device. This ensures that if there are two devices
with same identity (e.g. I2C address or USB port #) but using
different properties (registers) controlled by different probe
statements, then the two devices are not incorrectly matched as the
same device.
The check for base device having a probe list is performed before
comparing the probe lists because a base device might not really have
any probe requirements at all. So, when overriding such a device,
there is no need to check for the probe list match.
BUG=b:187193527
TEST=Verified by adding two I2C devices in the override tree with the
same I2C address and chip but different probe statements and confirmed
that both the devices are present in generated static.c file.
Change-Id: Ib18868b336cf4ffc9aa38aee7c6f333a35d32fce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change moves the hda device enabling from baseboard device tree
to override tree for the variants that did not provide any hda
specific nodes. This ensures that the probe statements are correctly
selected by the variant depending upon the configurations it
supports.
Change-Id: Ib7b36468f17fbd65eb3d7d9355fcf78148aeb44a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57123
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
volteer baseboard was currently enabling TBT(USB4) devices in
baseboard devicetree and also selecting the Kconfigs required for
resource allocation above 4G for the USB4 controllers. However, not
all volteer devices have USB4 support. This change fixes USB4 enabling
for volteer family by making the following udpates:
1. TBT devices are moved from baseboard devicetree to individual
override trees for the variants that actually support USB4.
2. When moving TBT devices to override tree, tbt_pcie_rp0 is marked as
on instead of hidden for all variants other than volteer
reference. This is because volteer reference is the only device that
has an asymmetric support for USB4 (i.e. does not support USB4 on C0
port).
3. Kconfig selection for PCIEXP_HOTPLUG is moved to Kconfig.name for
these variants.
Change-Id: If380dcb1ea1633b3a1d6932e769cb6ed0a2761c7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57112
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Processor hang is observed while hot plug unplug of TBT device. BIOS
should execute TBT PCIe RP RTD3 flow based on the value of
TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if
BIT30 in TBT FW version is not set.
BUG=b:194880254
Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56503
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It would be easier for people to find the defined variables.
Change-Id: I6d181f6602aa5d55019ea2110b2d8e1fa7e0159c
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
On Braswell this is done in the bootblock before C code is executed.
Change-Id: I72c7b821e04169ae237d8adb6a8348f06e87b047
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
In CB:56884 we discussed changing the default fast_read speed from
66MHz, which some platforms may not be capable of running, to 33MHz,
which should be generally suitable for all platforms. This same
change has been applied to the default for all SPI speeds.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibf926df6829ffdcbae947aaa245356f219615ce8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57148
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ravi Kumar Bokka