Commit Graph

39319 Commits

Author SHA1 Message Date
Michael Niewöhner c1d1dddbcc mb/supermicro/x11-lga1151-series: rework gpio setup to not use headers
Rework gpio setup for the board series to not use headers but
stage-specific compilation units.

Tested successfully on X11SSM-F.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ic62ce4335af605c081ef288e892441585ff2bd3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-11-29 07:28:56 +00:00
Michael Niewöhner e88dacfa43 mb/supermicro/x11-lga1151-series: switch from dev.init to mb_ops.init
GPIO needs to be initialized before the IPMI device gets initialized,
so the GPIOs can be read/set by the code in CB:48096 and CB:48094. Thus,
use mainboard_ops.init for GPIO configuration instead of using the
indirection via a mainboard_enable function.

To make it more visible, that we use chip.init, rename `mainboard_init`
to `mainboard_chip_init`.

Tested successfully on X11SSM-F including the IPMI changes.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I192e69a34fa262b38bc40a95fb11c22a4041d0ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-29 07:27:47 +00:00
Michael Niewöhner dc811c9ea3 mb/supermicro/x11ssm-f: drop unneeded ITSS override
The ITSS override is not needed for LPC_CLKOUT* pads. Drop it.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I3dbbc8944751779151dcd4f92fb870d937801d69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48084
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-28 12:59:03 +00:00
Michael Niewöhner 1b0d751777 mb/supermicro/x11-lga1151-series: configure gpios in mainboard init
Move gpio configuration from the Fsp callback to mainboard init.

Tested successfully on X11SSM-F.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: If2a54c75c5243d94cdc025c597ee347820b35d32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48086
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-28 12:58:28 +00:00
Michael Niewöhner ddd44f4fe9 mb/supermicro/x11-lga1151-series: restructure and clean up devicetree
Drop zero-value devicetree options and move PcieRpEnable options down to
the corresponding devices.

Test: built with TIMELESS=1; binaries remain identical

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9285d786e973621a732e2627c734adc930e54207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-28 12:57:51 +00:00
Michael Niewöhner 84fde762e7 soc/intel/skl: correct OC pin skip value for disabled usb ports
Commit 056d552 introduced a bug where 0xFF gets set as OC pin value to
supposedly skip programming an OC pin for a disabled USB port. While the
value is correct for the other platforms, Skylake uses 0x08 for this
purpose. Correct this by using the enum value OC_SKIP (0x08) instead.

Change-Id: I41a8df3dce3712b4ab27c4e6e10160b2207406d1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-11-28 12:57:08 +00:00
Michael Niewöhner 43dd2e458f docs/mb/supermicro/x11-lga-series: Update documentation
- Drop issue about non-working TianoCore with Aspeed NGI. see CB:35726
- Add missing reference to X11SSH-F
- Drop TODO reference; there are no TODOs left

Change-Id: I5becfa9ea01a0d9d651c6b51b30ebfcedb6412a5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48101
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-27 20:49:16 +00:00
Michael Niewöhner 4c56d79ba6 {docs/,}mb/supermicro/x11ssh-tf: drop TODO section
Drop the TODO comment, since there is no TODO left. Also drop the now
obsolete TODO section from the board documentation.

Change-Id: I4192aaedc1429c8ff1bd7c52baa4741e1df0d0c5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-11-27 20:49:04 +00:00
Michael Niewöhner ce04a42db9 docs/mb/supermicro/x11ssm-f: Update board documentation
- Drop vanished issue on PCIe warning
- Drop TODO section, since the TODOs are done
- Document the jumper J6, that was not documented by the vendor. Its
  function has been determined by dissecting a dead board.
- The flash is not socketed anymore. Drop that note and compress the
  whole paragraph. Also add a note about flashing via the BMC web
  interface.

Change-Id: I2b5a08a6b6d80717621d6a30f31829fe4b84891a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-11-27 20:48:55 +00:00
Arthur Heymans 0f34054964 Makefile.inc: Move adding mcu FIT entries
This can be done using in the INTERMEDIATE target in the proper place.

Change-Id: I28a7764205e0510be89c131058ec56861a479699
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46453
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-27 09:18:20 +00:00
Meera Ravindranath f71572605a soc/intel/jasperlake: Enable VT-d and generate DMAR Table
Update UPDs required for the creation of DMAR table.

By default coreboot was not generating DMAR table for IOMMU which
was resulting in below error message in kernel:
DMAR: [Firmware Bug]: No DRHD structure found in DMAR table
DMAR: No DMAR devices found
These changes will publish DMAR table through ACPI and will not
result in the above error.

BUG=b:170261791
BRANCH=dedede
TEST=Build Dedede, boot to kernel and check dmesg if DMAR
     table exists.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I97a9f2df185002a4e58eaa910f867acd0b97ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-11-27 05:10:12 +00:00
Idwer Vollering 99eed832ae util/inteltool: drop OS-specific rdmsr/wrmsr prototypes
The previous commit (that was not touching inteltool.h)
marking internal functions as static is commit 6faccd1f00

Tested on: FreeBSD 13.0-CURRENT r355582

Change-Id: I4aba72f39b528fd70451a4656fd6c835ff766e49
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-26 23:31:46 +00:00
Michael Niewöhner 3044d708f8 drivers/intel/fsp2_0: move the FSP FD PATH option down in menuconfig
Move the FSP FD PATH option down, so it gets shown in place of the split
FD files, when the users chooses to use a full FD binary.

Change-Id: Ie03a418fab30a908d020abf94becbaedf54fbb99
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-26 21:57:44 +00:00
Michael Niewöhner 59f06ada68 drivers/intel/fsp2_0: introduce possibility of using a full FD binary
Currently, setting a custom FSP binary is only possible by using split
FSP-T/M/S FD files. This change introduces the possibility to pass a
combined FD file (the "standard" FSP format).

This is done by adding a new boolean Kconfig FSP_FULL_FD, specifying
that the FSP is a single FD file instead of split FSP-T/M/S FD files,
and making FSP_FD_PATH user-visible when the option is chosen. In this
case, the other options for split files get hidden.

When the user chooses to use a full FD file instead of the split ones,
the FD file gets split during build, just like it is done when selecting
the Github FSP repo (FSP_USE_REPO).

Test: Supermicro X11SSM-F builds and boots fine with custom FSP FD set.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I1cb98c1ff319823a2a8a95444c9b4f3d96162a02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-26 21:57:33 +00:00
Subrata Banik 905939b3c8 vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1483_11
List of changes:
1. FSP-M Header:
- Adjust UPD Offset for Reservedxx
- Rename UPD Offset UnusedUpdSpace32 -> UnusedUpdSpace29
2. FSP-S Header:
- Rename UPD Offset UnusedUpdSpace46 -> UnusedUpdSpace44

Change-Id: Ia1ef59e4cf6ccce8f48908af51535aea761cd972
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47901
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-26 18:10:47 +00:00
FrankChu 8b0c1c8027 mb/google/dedede: Create galtic variant
Create the galtic variant of the waddledee reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.3.1).

BUG=b:170913840
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_GALTIC

Signed-off-by: FrankChu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ie7534d56bc67aca4484f40af1221d669addc01fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47900
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25 21:29:46 +00:00
Nick Chen 1856effaf2 mb/google/volteer: Update Eldrid USB2 port settings in overridetree
1. Disable M.2 WWAN and Type-A Port A1
2. Change register 4 to 3 and tuning USB2 Port1 eye diagram
3. Lower camera driving

BUG=b:169105751
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I6b8a5c0d5e814de232d79a43354f5ec0220fc5ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-25 18:40:24 +00:00
Patrick Georgi 2f1d686ba6 Update vboot submodule to upstream master
Updating from commit id 9d4053d:
2020-11-20 01:51:08 +0000 - (Revert "Reland: Clean up implicit fall through.")

to commit id 48195e5:
2020-11-24 10:23:45 +0000 - (Makefile: Test for warning flags before using them)

This brings in 3 new commits.

Change-Id: I64f27f346df264cb6eeeb4e3203fcca7d35f7e83
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2020-11-25 16:26:48 +00:00
Idwer Vollering 5190f42306 util/crossgcc: ensure curl writes downloaded bytes to a file
Commit 82a30a134c (util/crossgcc: Retry package downloads on failure) caused a regression for curl users.

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I0d946b86baad3f6409a5042701808da307e5bcb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-25 16:03:30 +00:00
Tim Chu 9b7dc7645d mb/ocp/deltalake: Define SMBIOS type 16 error correction type by
RasModesEnabled

Use RasModesEnabled from SystemMemoryMapHob to define SMBIOS type
16 error correction type

Tested=Execute "dmidecode -t 16" to check if error correction type
is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I3636fcc4a874261cf484c10e2db15015ac5d7e68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-11-25 09:18:25 +00:00
Tim Chu a96eaf8700 arch/x86/smbios: Update SMBIOS type 16 error correction type
Add weak function for SMBIOS type 16 error correction type.

Tested=Execute "dmidecode -t 16" to check if error correction type
is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I85b37e9cfd22a78544d03e5506ff92b1f2404f8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47508
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25 09:18:04 +00:00
Matt DeVillier f7cdb8e3c6 mb/google/hatch: select SOC_INTEL_CSE_LITE_SKU only if CHROMEOS
Selecting SOC_INTEL_CSE_LITE_SKU without conditioning on CHROMEOS
force-selects CHROMEOS, per src/soc/intel/common/block/cse/Kconfig.

Conditioning on CHROMEOS allows for non-ChromeOS targets to be built.

Test: build wyvern variant with CONFIG_CHROMEOS=n

Change-Id: I61c9c78a3b02d64bab2813b7a80915b7ecf7f934
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-25 09:17:21 +00:00
Julius Werner 105cdf5625 cbfstool: Don't add compression attribute for uncompressed files
Our current cbfstool has always added a compression attribute to the
CBFS file header for all files that used the cbfstool_convert_raw()
function (basically anything other than a stage or payload), even if the
compression type was NONE. This was likely some sort of oversight, since
coreboot CBFS reading code has always accepted the absence of a
compression attribute to mean "no compression". This patch fixes the
behavior to avoid adding the attribute in these cases.

Change-Id: Ic4a41152db9df66376fa26096d6f3a53baea51de
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-11-25 09:16:45 +00:00
Angel Pons d87a84830e soc/intel/{broadwell,quark}: Drop `PEI_DATA` typedef
It is not used.

Change-Id: I3ef0878811bf2ec406ded03aac6c5dfeb5bf45a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47001
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25 09:15:36 +00:00
Elyes HAOUAS 794a9b7b9c crossgcc: Upgrade binutils to 2.35.1
Change-Id: I8694a154d48c5a718b27d4beb858942db0feb997
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-25 09:14:50 +00:00
Elyes HAOUAS f106b3b430 crossgcc: Upgrade LLVM to version 11.0.0
Change-Id: I1cc02355e3fea7eb9ad98be6396a492dbbdc47b2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-25 09:14:37 +00:00
Stanley Wu 64f7bdf19a mb/google/volteer/variant/lindar: change speaker smart amplifier to ALC1011
Lindar change amp to ALC1011
Add ALC1011 amp acpi info to devicetree

BUG=b:171771736
BRANCH=firmware-volteer-13521.B
TEST=build and verify ALC1011 can be recognized.

Change-Id: I4d83a19b3baa87cc926bb7c3a2cb96bf3165d2f4
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-25 09:14:28 +00:00
Jakub Czapiga ea378ccc8f tests: Add lib/list-test test case
Change-Id: If74f241b2bb788b3e2fd1b9062fc74819f7be31e
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-11-25 09:14:07 +00:00
Felix Singer 5a41b0db20 MAINTAINERS: Add maintainers for kontron/mal10
Add Maxim Polyakov, Nico Huber and Felix Singer as maintainers for
kontron/mal10.

Change-Id: I2f4200708e4aec6d74916fb5e63efe2f20594882
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47889
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25 09:13:55 +00:00
Nikolai Vyssotski 6f32d80e18 mb/amd/mandolin: Add decode range for LPC debug card
Some LPC debug boards hard strap SIO address to be at
0x164e/0x164d vs 0x4e/0x4d. Add support for configurable
SIO address to support these cards.

BUG=b:159933344
TEST=boot with LPC debug card, verify serial output

Change-Id: I103c61f21f13970dfa3b9a788b29964e478fb84c
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-25 09:13:41 +00:00
Wisley Chen eb8036b591 mb/google/volteer/var/elemi: Add H5ANAG6NCJR-XNC
Add H5ANAG6NCJR-XNC.

BUG=b:165461530
BRANCH=volteer
TEST=emerge-volteer coreboot

Change-Id: I827158ce0abe764f1e3b5de46abf50dc148a6ff0
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-25 09:13:29 +00:00
Angel Pons ec5cf1504e nb/amd: Deduplicate nb_common.h
Save for the IO_APIC2_ADDR definition, they are equivalent.

Change-Id: I14da3d9aeefcc725428957ce0c9ac164eabacec6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47408
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25 09:11:58 +00:00
Angel Pons c19cbeeb6b device: Drop unused HyperTransport code
Only two definitions are actually used somewhere, the rest is unused.

Change-Id: Iec52d0d47fce6a1ec5455b670824b995a7a34a4c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47407
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25 09:11:46 +00:00
Felix Singer ec8f5c79a5 mb/clevo/kbl-u: Configure GPIOs using mainboard_ops
Hook up the mainboard_ops driver and configure the GPIOs using .init,
since mainboard_silicon_init_params() is meant for the configuration of
the FSP, not the GPIOs.

Change-Id: I82f1eaf6693d9b117fb211776047058cdc787288
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-24 22:43:23 +00:00
Felix Singer 12e5fda496 mb/kontron/bsl6: Move GPIO configuration to C file
Change-Id: I008de1bf91ba97ee5eefbde11947c73059fff5f7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-24 21:41:40 +00:00
Felix Singer f84e304ea1 mb/kontron/bsl6: Use include folder for header files
Change-Id: Id73a7385f7701920efebaa3e293ac50a6ba93272
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47849
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 20:22:29 +00:00
Felix Singer 4ea08f9f56 sb/intel/lynxpoint: Replace hard-coded IDs with defines
Replace hard-coded IDs with defines introduced in CB:47807.

Used documents:
- 328904-003
- 329003-003

Built lenovo/t440p with BUILD_TIMELESS=1, coreboot.rom remains
identical.

Change-Id: I910ab356dd8728c316018989bfb2689d4c67c2dc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47808
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 18:37:58 +00:00
Felix Singer d5f1c08816 include/device/pci_ids.h: Add PCI IDs used in Lynxpoint chipsets
Used documents:
- 328904-003
- 329003-003

Change-Id: I95790cda6f7c42a9de57bf5e92eb829ee1807dbe
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47807
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 18:37:46 +00:00
Angel Pons de50d399a1 mb/**/cmos.layout: Drop copy-pasted `volume` entries
This option only applies to boards using the Lenovo H8 EC code.

Change-Id: I3b16a61a0aa9f51a4061b1b5e58fc276e7383415
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47150
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 17:47:29 +00:00
Angel Pons 8e021d96b3 mb/**/cmos.layout: Drop copy-pasted SNB entries on non-SNB
Only Sandy Bridge MRC stores scrambler seeds in CMOS. Non-Sandybridge
boards ended up with these entries because of copy-paste programming.

Change-Id: I5a5bda6ea4e63ba03a4219bb2a6aa546bb6ecd7a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47149
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 17:47:15 +00:00
Sheng-Liang Pan c5395bc95d mb/google/volteer/var/voxel: Update DPTF parameters
update the DPTF parameters received from the thermal team.

BUG=b:167523658
TEST=emerge-volteer coreboot

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Iafc3fb389ade5cfec79a816a28880262bdce7c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47858
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 16:24:20 +00:00
Rocky Phagura 17a798b68c soc/intel/xeon_sp: Enable SMI handler
SMI handler was not installed for Xeon_sp platforms. This enables SMM
relocation and SMI handling.

TESTED:
- SMRR are correctly set
- The save state revision is correct (0x00030101)
- SMI's are properly generated and handled
- SMM MSR save state are not supported, so relocate SMM on all cores
in series
- Verified on OCP/Deltalake mainboard.

NOTE:
- Code for accessing a CPU save state is not working for SMMLOADERV2,
so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS
pointer are not supported.
- This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS
is broken and needs to be fixed separately. It is unknown if TCO is
supported. This might require a cleanup in the future.

Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 12:44:28 +00:00
Arthur Heymans f4721246db soc/intel/xeon_sp: Select INTEL_COMMON_BLOCK_TCO
TCO is configured by FSP. This mostly makes it possible to report TCO
events in SMM if enabled.

Change-Id: I4f81c7888e45ed01ee68b1d6e6a9986a4d735467
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47764
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 12:02:06 +00:00
Arthur Heymans f4f332dba9 soc/intel/xeon_sp: Hook up the PMC driver
The soc code was already there but it was never linked.

Change-Id: I75ee08dab524bc40f1630612f93cbd42025b6d4e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47763
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 12:01:52 +00:00
Zhuohao Lee b3b4ccfb26 mb/google/volteer: fw_config: Add setting for new sd readers
This patch adds three settings for the new sd readers.
The new assigned values are:
1. RTS5227S: 3
2. L9750: 4
3. SD_OZ711LV2LN: 5

BUG=b:173676531
BRANCH=volteer
TEST=abuild -t google/volteer

Change-Id: I595695f99d3298f146fcdb7c2b942ce007ae9327
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-24 09:42:49 +00:00
Benjamin Doron eecaf360de soc/intel/skylake: Support NHLT 1ch DMIC
Allows advertising support for a 1ch array DMIC in the NHLT table.
Boards use the NHLT if a microphone is connected to the DSP.

Tested on an Acer Aspire VN7-572G (Skylake-U) on Windows 10.
A custom ALSA topology will be required for Linux.

Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-24 09:42:23 +00:00
Benjamin Doron 9ee1b82db4 soc/intel/skylake: Use correct NHLT_PDM_DEV definition
According to the NHLT specification[1], PDM_DEV is defined as "1" on
Kabylake based platforms. coreboot currently sets it to "0" on
all platforms. Add an entry to the enum and use it to define
NHLT_PDM_DEV for Kabylake.

"Device Type" will resume from "2" on all platforms, but entries are
currently reserved.

Tested on an Acer Aspire VN7-572G (Skylake-U), which has a 1ch array
DMIC, on Windows 10.

1. https://01.org/sites/default/files/595976_intel_sst_nhlt.pdf

Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45010
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24 09:42:14 +00:00
Mike Banon 1e6a227f10 nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices
Follow the example of newer AMD code for Stoneyridge and Picasso.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I9c17d4cb4953b28a47483f5d7db308ccc89e9281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-23 19:18:03 +00:00
Mike Banon 58d0336ef3 nb/amd/agesa/family15tn: define macro for internal HDMI audio controller
Following the example of CB:7630 done for family16kb boards
(git commit 3ff4f85ccd).

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ic48c7475ceadb60f825ca9e3c3427c8a7525a266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-23 16:46:55 +00:00
Kevin Chiu de20b28fe4 mb/google/zork: correct USB2 phy TXVREFTUNE0 parameter name
From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0".
correct rx_vref_tune -> tx_vref_tune

BUG=None
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-23 16:44:59 +00:00