Commit Graph

22297 Commits

Author SHA1 Message Date
Matt DeVillier 6781648054 ec/quanta/it8518: correct ACPI battery data fed into ToString()
ToString() requires the input buffer data to be null-terminated,
but the data returned by the EC is not, leading Windows to fail
to report any battery data at all.  Correct this by concatenating
a null terminator (0x00) to the end of the buffer data before
inputting to ToString() where needed

TEST: boot Windows on google/stout, observe battery data
reported correctly.

Change-Id: I974afcd6ff1c617301d0897d6bd1fe14200aa3b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-19 14:11:20 +00:00
Matt DeVillier f11d0c3414 ec/purism/librem: fix battery present rate
EC ACPI code is calculating the drain rate, but does not store it
in the battery status package before returning it.  Correct this
omission, and set the drain rate to a preset minimum if calculated
value is less.  Taken from vendor firmware ACPI dump.

Change-Id: I52837d5879112ab3103976bda28906fac8f880ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-19 14:11:07 +00:00
Nathaniel Roach d7e0cb93ae sb/intel/bd82x6x: Add awareness of ME's Alt Disable Mode
me_cleaner now allows setting a bit in the PCH straps - AltMeDisable
tells the ME to stop execution after BUP - disabling the 30 minute
watchdog - but also "breaking" the ME. The ME reports opmode = 2.

This means the ME will not respond when we wait for an acknowledgement
about the DRAM being ready. The current code waits 5 seconds for a
response, that in this case, never comes.

If the ME is reporting opmode 2, don't delay or wait for a response
from the ME.

Tested on my X220, this patch fixed the five seconds before the payload
executed. Verified using the timestamp patch.

Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/21466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-19 01:27:17 +00:00
Marshall Dawson 2fd9651b23 amd/stoneyridge: Add northbridge definitions
Begin adding D18F1 definitions to northbridge.h.

Change-Id: I4fa2f9a4af8fbb3c2919ffb5dca34cbe333bc958
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-19 01:22:18 +00:00
Bill XIE 612ec0ed0a ifdtool: Refactor some code
Add find_fcba(), find_frba(), find_fmba(), find_fpsba()
and find_fmsba() to replace those copy-pasted addressings.

This commit is one separated from the original I6d05418c.

Change-Id: I98965711e4cb9792e5cc86cc4c1035559e0274f5
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-17 21:31:22 +00:00
Bill XIE 4651d4501c ifdtool: redesign some structures
Redesign some array-like structures as true arrays,
and rewrite functions to dump them as loops.

This commit is one separated from the original I6d05418c.

Change-Id: I161c9a2ae83d26e658d67d0804e943fff95fe076
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-17 21:29:57 +00:00
Bill XIE 1bf6506e97 ifdtool: merge region_filenames with region_name(s)
There is no reason to keep a separate region_filenames array,
so I merge it into region_name(s).

This commit is one separated from the original I6d05418c.

Change-Id: I38489c6d3b3c161e9b0281188e6cdd0b62e38335
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21509
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-17 21:27:55 +00:00
Bill XIE fa5f99430d ifdtool: Const-correct and redesign some functions
Const-correct some functions which do not write back,
and use pointers to access existing region_t variables.

The last changeset is dismantled this time.

This commit is only focused on const-correctness.

Change-Id: I6d05418c8b32fa31dcd038a3e56f9aefe13fa9c4
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21288
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-17 21:27:05 +00:00
David Hendricks c863be7ba4 board_status: Add option to set cbmem path
This allows the user to specify a custom path for cbmem on the DUT.

Change-Id: I2c28737d6efaae238fd6831cd3d00b2142b39a4c
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/21565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-17 01:13:23 +00:00
Damien Zammit 693315160e cpu/x86/sipi_vector.S: Use correct op suffix
clang wont compile `cmp` asm opcode because it's ambiguous,
use the correct op suffix `cmpl`

Change-Id: I82da5a9065b382e182dc7d502c7dca2fc717543b
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-17 00:40:36 +00:00
Damien Zammit 590cfc5d63 via/cn700: Fix clang error with missing main
According to clang, main has no prototype for bcom/winnetp680
so add it into corresponding raminit.h

Change-Id: I8a55267901986757a4fa88ee13460ffbed3eeadc
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-17 00:39:47 +00:00
V Sowmya 79f8f22499 mb/google/poppy: Add lens_focus property for OV13858 camera module
Add lens_focus property with reference to VCM device for OV13858
camera module to register the corresponding v4l2 sub-device
asynchronously.

BUG=b:64133998
BRANCH=none
TEST=Build and boot soraka. Dump DSDT and verified that it has the
required entries and verified the camera functionality.

Change-Id: Ib22403f668dd07d6b9226fe2c22b533223b69473
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21512
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-16 22:40:45 +00:00
Matt DeVillier a21d0a1073 google/lulu,gandof: set kb backlight on boot
Set keyboard backlight to 75% on boot, except when resuming
from S3.  This enables the backlight at a reasonable level
prior to the OS driver taking over, providing early proof-of-life
and enhanced usability in grub etc.

Uses same method as other google boards with a keyboard backlight
(chell, link, samus).  75% value determined based on user feedback.

TEST: boot google/lulu,gandof boards, observe keyboard backlight
enabled in pre-OS environment.

Change-Id: I7ed59289419af21764b1b5bd0a534d3b630c6c6b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16 22:34:11 +00:00
Jonathan Neuschäfer 6a878a1f24 soc/intel/common: smm.h: Fix copyright year
Intel obviously didn't exist in 201 :-)

Change-Id: I230d3b92ec6832fcea056fd3d099147002274d73
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16 22:33:53 +00:00
Jonathan Neuschäfer a1c42cca00 payloads/external: Clone GRUB2 over HTTPS
Since the git:// protocol is unencrypted and unauthenticated, there's a
security risk associated with using it: A man-in-the-middle attacker
could replace e.g. the master branch with malicious code.

Mitigate this risk somewhat by cloning GRUB2 via HTTPS.

Change-Id: Ice8f8d108e7dfa1a1ecd58d9735944fa9570ace8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-09-16 22:33:29 +00:00
Matt DeVillier 602d0a42d4 google/reks: add new board as variant of cyan baseboard
Add support for google/reks (Lenovo Chromebook N22/N42) as
a variant of the cyan Braswell basebaseboard.

- Add board-specific code as the new reks variant
- Add new I2C touchscreen device and SPD files to the baseboard
for potential reuse by other variants

Sourced from Chromium branch firmware-reks-7287.133.B,
commit 7d812d4: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""

Change-Id: Iac9e2b5661aa33e12927f4cb84ebaee36522a385
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16 22:32:33 +00:00
Matt DeVillier 4f20a4ae47 google/edgar: add new board as variant of cyan baseboard
Add support for google/edgar (Acer Chromebook 14 CB3-431) as
a variant of the cyan Braswell basebaseboard.

- Add board-specific code as the new edgar variant
- Add common code to the baseboard which will apply to all
  variants other than cyan

Sourced from Chromium branch firmware-edgar-7287.167.B,
commit 2319742: Edgar: Add Micron MT52L256M32D1PF-107 SPD data

Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16 22:31:32 +00:00
Hannah Williams 7427abce07 mainboard/intel/glkrvp: Add support for audio
This patch adds the below:
1) Add correct SSP endpoint config for spk and headset
2) Update GPIO config for jack detection
3) Update GPIO config for I2S pins

TEST=sound card binds
TEST=cross checked SSDT entries from
          /sys/firmware/acpi/tables/
TEST=Jack interrupt works

Change-Id: I32022ddacd79917730080889c040f842e0c9e6b9
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/19799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-16 22:30:33 +00:00
Hannah Williams 1d4d3f3f73 soc/intel/apollolake: Leave Hda enabled for GLK
Audio was disabled during initial stages, this patch enables back.
It was disabled to unblock other validation tests.

TEST=lspci lists audio controller

Change-Id: I5d3872e86623763e20ee6464897f47792c731642
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/21529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-16 22:29:14 +00:00
Arthur Heymans 4ea66e6b6f device/dram/ddr2: Fix decoding tRR
Bit 7 is set on all options so only the default option in the switch
statement is returned.

Change-Id: I6a698ec9c15a2611a34c5965edf93638553775f0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16 16:23:44 +00:00
Lijian Zhao 18f8f622d5 mainboard/intel/cannonlake: Add ec entry into flashmap
Add EC entries into chromeos.fmd file.

BRANCH=None
BUG=None
TEST=Flash image and confirm system can get out of reset successfully.
System will not be able to reach reset vector if flash map described in 
coreboot does not match intel flash map generated from fit.

Change-Id: Ic18ce59941b4ff8171fe661d332e3e521d988341
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21526
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-15 21:36:14 +00:00
Patrick Georgi 77343fd668 util/scripts/cross-repo-cherrypick: improve cros-side rewrite
Sometimes the BUG/BRANCH/TEST metadata isn't separated by a newline
from the later git/gerrit metadata, which messes up further processing.

Add that newline to minimize the amount of human intervention required.

Change-Id: I37171bf6764b64e0ab0e81297a03f4d8b7744256
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-15 20:57:57 +00:00
Richard Spiegel c661c8eab1 soc/amd/stoneyridge: Improve code quality
Remove empty functions. In function pointer structure
"device_operations", replace the 0 equality by NULL equality.
Files: hda.c, sata.c and usb.c

Change-Id: I9f8dc7681ab2e651872e69a8b2e990e59ebe80c9
Signed-off-by: Richard Spiegel <richard.spiegel@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/21522
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-15 19:28:11 +00:00
Rizwan Qureshi ea4649f65f mb/google/poppy: enable AER for PCIe root port 0
Enable PCIe Advanced Error Reporting for PCIe root port 0.

BUG=b:64798078
TEST="lspci" shows that AER is enabled in the capabilities list.

Change-Id: I8a818a9539b8d4f103d551ffd59713c9bbbc13ce
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21425
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-15 18:20:42 +00:00
Pratik Prajapati 6a051f2b49 soc/intel/skylake: Move UNCORE PRMRR base and mask defines.
UNCORE PRMRR BASE and MASK MSRs are not common, so move to
SOC specific header file and rename the #define to start with MSR_*

Change-Id: I799c43f0b7a9eec5b3b69ab0f5100935c7f3f170
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15 16:21:29 +00:00
Pratik Prajapati 57c5af30dd soc/intel/common/sgx: use SOC specific API to get PRMRR base and mask
Use soc_get_uncore_prmmr_base_and_mask() API to get PRMRR base and mask.

Change-Id: I2fd96607c4f5fed97e38087b60d47d6daacc7646
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21246
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-15 16:21:17 +00:00
Pratik Prajapati b45b22f6b2 soc/intel/common/sgx: Define and use soc_fill_sgx_param()
To remove chip.h dependency from SGX common code
- Create API soc_fill_sgx_param() and use it in sgx.c
- Implement same API for skylake/kabylake
- define sgx_param structure

Also include intelblocks/sgx.h instead of soc/msr.h

Change-Id: I358f0817bec5dd6cd147a645675b5688969a04e0
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15 16:21:11 +00:00
Sumeet Pawnikar 1638a85b49 MAINTAINERS: Remove extra unnecessary space
Remove extra unnecessary space at end of line.

Change-Id: I27688c3b8df71b875f1dc1020465d838756362be
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/21521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15 04:29:29 +00:00
Julius Werner 848f5db345 MAINTAINERS: Add Julius as LZ4 maintainer
I imported the LZ4 compression code and want to keep an eye on it to
ensure that our sources stay in sync with upstream.

Change-Id: I249ce24f6630d66d451d993198cd267478e5743e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/21488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-15 02:51:55 +00:00
Mariusz Szafranski 025d819ee1 MAINTAINERS: Add INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB
Add Intel FSP Atom C3000 SoC ("Denverton" and "Denverton-NS")
and Harcuvar CRB to the list.

Change-Id: I1c4bfd0900e8d425b95b5ef6c541b1e988846667
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/21515
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-09-15 02:42:07 +00:00
Matt DeVillier e69a9c7581 google/cyan: convert to variant configuration
Setup cyan to be the baseboard for other Google Braswell
boards, to be added in subsequent commits:

- Keep code common to all Google Braswell boards in the baseboard,
and separate out the board-specific bits into the new cyan variant.

- Define the I2C ACPI devices such that they can be easily reused for
other variants.

- Switch the trackpad/touchscreen interrupts from edge to level,
for better performance/compatibility, as was done with all previous
Google boards.

- Add code to the baseboard to allow optional variant-specific
parameters to be used for both memory and silicon init.

- Remove superfluous includes, replace some hardcoded values with
variables, and correct typos/formatting errors.

Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15 02:36:13 +00:00
Pratik Prajapati 982688a41a mainboard/intel/cannonlake_rvp-u: Configure USB ports
Configure USB2, USB3 and Type-C ports for CannonLake-U RVP

Change-Id: Id875063721ccb62ad4b5187c81f6abf44bf93f74
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14 21:11:02 +00:00
Pratik Prajapati b2d6902086 mainboard/intel/cannonlake_rvp-y: Configure USB ports
Configure USB2, USB3 and Type-C ports for CannonLake-Y RVP

Change-Id: Ic3b6b481cb33bfefb267910a5e649877d900d109
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14 21:10:57 +00:00
Pratik Prajapati c82e1fbcab src/soc/intel/cannonlake: Define USB configuration params
Define USB2, USB3 and Type-C configuration for CannonLake.

Change-Id: I42243950366d672e886158eb1934350f47b4ff1f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14 21:10:53 +00:00
Werner Zeh efd0eb35af siemens/mc_apl1: Add delay to wait for legacy devices
There are old legacy onboard devices which are too slow for a coreboot
boot with log level BIOS_ERR. In this case coreboot is so fast that these
devices do not have enough time to become visible on the PCI bus and
this in turn leads to missing resource allocation for this devices. The
most generic way to work around this problem on existing hardware is to
introduce a delay right before the PCI enumeration starts. The needed
delay time depends on the hardware and will therefore be get from
hwinfo.

Change-Id: Ia91babc81e3a347bbc498c3def97b2ea70e10922
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-09-14 18:12:49 +00:00
Werner Zeh 35cceb861c timestamp: Add function to get time since boot
Add a function to retrieve the elapsed time since boot. For that purpose
use the base time in the timestamp table among with the current
timestamp at call time of the function. So more precise the returned
time is the elapsed time since the timestamp was initialized scaled
in microseconds. This was chosen to get a reliable value even on
platforms where the TSC might not be reset on software reset or warm
start.

Change-Id: Ib93ad89078645c0ebe256048cb48f9622c90451f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14 18:12:39 +00:00
Pratik Prajapati 653f019d0d soc/intel/skylake: Implement UNCORE PRMRR get base and mask API
Implement soc_get_uncore_prmmr_base_and_mask() API for SKL/KBL

Change-Id: I880d3d88138809cdf030507877079cbea52a0d97
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21245
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-14 14:58:49 +00:00
Pratik Prajapati 738414586d soc/intel/apollolake: Implement UNCORE PRMRR get base and mask API
Implement soc_get_uncore_prmmr_base_and_mask() API for APL/GLK

Change-Id: I57df1f0e8ff984f32de4efdc6ebd68be501b4799
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14 14:58:33 +00:00
Pratik Prajapati 82cdfa73d5 intel/common/systemagent: Add API to get SOC specific PRMRR base and mask
Implement weak definition and SOC specific code would implement
actual definition.

Change-Id: I5e787a2603aaa475cb5c61558cc31ec0afcb4a8b
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14 14:57:47 +00:00
Aaron Durbin aa090cb6ea device: acpi_name() should take a const struct device
There's no reason to mutate the struct device when determining
the ACPI name for a device. Adjust the function pointer
signature and the respective implementations to use const
struct device.

Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-14 14:34:27 +00:00
Kyösti Mälkki d07f377872 usbdebug: Fix init and add support for postcar
It was originally designed such that if usbdebug_init() was called
before cbmem_initialize(), it would fetch the already-initialized
state from CBMEM. This changed when cbmem_find() behaviour changed
to require cbmem_initialize() to be called first. As a result,
ramstage had to reinitialize all of the EHCI controller and USB
endpoints on entry. This was slow, specially with AMD hardware
where one can scan USB ports to probe for the debug dongle.

For postcar and ramstage, move usbdebug entry such that it is
triggered from CBMEM_INIT_HOOK instead of console_init().
Side-effect of this is usbdebug console shows 'coreboot-xxx ...
starting...' line only for romstage.

Initialisation for usbdebug is never done in postcar. If you have
USBDEBUG_IN_ROMSTAGE=n, postcar will not have console output on
usb either.

While at it, fix also some other __PRE_RAM__ cases to ENV_ROMSTAGE
and alike.

Change-Id: If8ab973321a801abc5529f3ff68c5dccae9512ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14 12:26:18 +00:00
Lijian Zhao 0823183323 soc/intel/cannonlake: Add serialio device config
Add SerialIO device mode configuration, device mode definition mirrored
from FSP.

Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21411
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-13 22:56:09 +00:00
Kyösti Mälkki 1210026bda AGESA buildsystem: Reduce include path exposure
Remove AGESA_AUTOINCLUDES -list from coreboot proper CPPFLAGS.
Couple individual directories are now manually added to
complete builds.

Change-Id: I2595b87641c70e34e49fedf11b42f4961b0842dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13 22:52:13 +00:00
Kyösti Mälkki d136b8ef21 AGESA vendorcode: Remove AGESA_ENTRY_INIT_RECOVERY
Deprecated and not used in our builds.

Change-Id: I01773bb62b1599d18ad51d6f444abec46faec942
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13 22:51:57 +00:00
Kyösti Mälkki c8e4742f91 AGESA vendorcode: Move PlatformInstall.h
All thse Option.*Install.h files are about configuring
what eventually is referenced in the final libagesa
build. It's self-contained so isolate these together
with PlatformInstall.h to hide them from rest of
the build.

Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13 22:51:15 +00:00
Wisley Chen f7d0f02b36 mb/google/soraka: Update DPTF parameters
Cloned from baseboard/dptf.asl and update the parameters for soraka.

1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
   CPU: passive point:85, critial point:100
   TSR0: passive point:55, critial point:65
   TSR1: passive point:58, critial point:70
   TSR2: passive point:60, critial point:75
   TSR3: passive point:60, critial point:75

2. Set PL1 Max to 7W, and PL1 Min 4.5W

3. Change sampling period of thermal relationship table (TRT) setting
   CPU: 5 seconds
   TSR0: 30 seconds
   TSR1: 30 seconds
   TSR2: 8 seconds
   TSR3: 8 Seconds

BUG=b:65467566
TEST=build, boot on soraka, and verified by thermal team.
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>

Change-Id: I6af93fa358a037df2088213ee4df5e2cfd047590
Reviewed-on: https://review.coreboot.org/21453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-13 19:31:26 +00:00
Damien Zammit b92f6d36df agesa/f15tn: Remove unnecessary logic op
One liner that fixes a warning with clang

Change-Id: I4d7dfaa5fcf0e95acd650e4c129e0899b5d68f09
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-13 19:25:42 +00:00
Damien Zammit 0025247171 rmodtool: Increase limit on number of symbols
An internal index `i` was previously allocated as
Elf64_Half which is uint16_t.  Bumping to uint64_t
increases the number of allowed symbols and prevents
a segfault in processing a larger ramstage.debug file.
Also introduce a separate counter for the number of sections.

Change-Id: I9ad2f64c452cef2e7bf957f766600891cb5ae798
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-13 19:25:14 +00:00
Marshall Dawson 7bc0e42749 amd/stoneyridge: Remove duplicate PCI definitions
There were two copies of the same definitions in the file.

Change-Id: Iafb10476f32505f6b4ad7b5ba6fa5de2c4648836
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-13 19:20:22 +00:00
Damien Zammit f796dd86a7 fsp1_0/fsp_util: Rename global symbol find_fsp
To avoid error with symbol redefinition (using clang):
src/drivers/intel/fsp1_0/fsp_util.c:111:22: error: invalid symbol redefinition
                ".global find_fsp\n\t"
Rename the asm global symbol to find_fsp_bypass_prologue and fix jmp.

Change-Id: I84c152f9a580fdfc40e9f6e998d2d6484b7f47df
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13 19:18:08 +00:00