a7b3cfff27
added SMBUS stuff.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-24 03:30:48 +00:00
39b8077ad5
Simply typo in 'target' if directory does not exist
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-24 03:12:14 +00:00
7edf2ca6ff
fix non-portable syntax.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-24 03:08:57 +00:00
06a927dd68
Syntax fixes.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-23 23:52:15 +00:00
826def7e1d
New option stuff.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-23 16:54:12 +00:00
9cf8c2efdd
_RAMBASE used by linuxbios_c.ld
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-23 05:00:08 +00:00
5808bac568
Sandpoint configuration file.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-23 01:02:54 +00:00
4890a666a9
Global options file
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-23 01:01:17 +00:00
a946e4a596
tool for building roms, to eliminate icky shell scripts.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-20 16:46:48 +00:00
153ea3548f
- Implement goto support
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- Register allocator bug fixes.
* coalesce_live_ranges now also updates the interference graph of live instructions
* resolve_tangle now avoids copies to phi
* correct_tangles is now called in a loop so that all tangles get fixed
- Bug the version of romcc to 0.30
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-20 14:43:20 +00:00
f7a0ba84dc
- Update the romcc version.
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- Add an additional consistency check to romcc and fix the more obvious problems it has uncovered
With this update there are no known silent failures in romcc.
- Update the memory initialization code to setup all 3 of the memory sizing registers properly
- In auto.c test our dynamic maximum amount of ram.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-19 15:14:52 +00:00
9dbd460776
- Remove bogus #if CONFIG_SMP test
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-19 03:34:54 +00:00
d3283ec05f
- A new test case for romcc
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- Minor romcc fixes
- In smbus_wail_until_done a romcc glitch with || in romcc where it likes
to run out of registers. Use | to be explicit that I don't need the short
circuiting behavior.
- Remove unused #defines from coherent_ht.c
- Update the test in auto.c to 512M
- Add definition of log2 to romcc_io.h
- Implement SPD memory sizing in raminit.c
- Reduce the number of memory devices back 2 to for the SOLO board.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-18 11:03:18 +00:00
99acb49cf7
added config and other test files.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-17 16:51:06 +00:00
667393676b
new config file testing the update stuff.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-17 16:48:07 +00:00
8d9c123812
- Minor mod to reset16.inc to work with newer binutils hopefully this works with older ones...
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- Update apic.h to include the APIC_TASK_PRI register definition
- Update mptable.c to have a reasonable board OEM and productid
- Additional testfiles for romcc.
- Split out auto.c and early failover.c moving their generic bits elsewere
- Enable cache of the rom
- Fixes to amd8111_lpc.c so that we successfully setup virtual wire mode on the ioapic
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-17 08:42:17 +00:00
f96a810f11
- Reduce the algorithmic complexity of parts of the register allocator
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so the worst case runtime of romcc is much more predictable
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-16 16:57:34 +00:00
d3e377a520
new config tool
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-14 15:07:02 +00:00
f7092040fd
More FB2 stuff
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-13 22:07:53 +00:00
26ba0f5f9b
Freebios2
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-13 17:21:10 +00:00
64b2e474b1
Updated.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-13 17:16:36 +00:00
8cff29d63e
Added tables.c
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-13 17:09:26 +00:00
c055fbb274
Fixes.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-13 17:02:57 +00:00
88e467f38e
PPC cpu stuff
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-13 16:54:40 +00:00
93247c0428
IDE stuff
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-13 16:25:21 +00:00
0d796734a6
IDE stream driver
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-13 16:17:17 +00:00
7a5416af95
- Modify the freebios tree so the pci config space api is mostly in sync between
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code that runs without ram and code that runs with ram.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-12 19:23:51 +00:00
540ae01cd3
- Changes to the pci config routines moving them closer to the non romcc API
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The goal is to have the same interface with or without romcc.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-12 17:55:54 +00:00
05f26fcb57
- Factoring of auto.c
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- Implementation of fallback/normal support for the amd solo board
- Minor bugfix in romcc
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-11 21:55:00 +00:00
c927b022c2
- Update romcc to version 0.27
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-10 21:25:29 +00:00
6aa31cc754
- Update romcc to version 0.27 and add more tests.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-10 21:22:07 +00:00
dc18ef018d
Moved from freebios
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-09 22:08:08 +00:00
f655bf7f3e
Moved from freebios
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-09 21:59:27 +00:00
0322115932
Moved from freebios
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-09 21:29:23 +00:00
fd958cea68
more specs.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-06 14:35:36 +00:00
a05b6ddb15
- Add pci_def.h so romcc compiled files can also get at the
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pci definitions
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-05-21 16:14:51 +00:00
526855741b
- Cleanups on the romcc side including a pci interface that uses
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fewer registers, and is easier to hardcode.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-05-19 19:16:21 +00:00
49cf5967ce
descriptor for chips
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-05-16 23:33:13 +00:00
302763831d
- Fix ? expressions previously they were reversed.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-05-16 20:47:48 +00:00
da55d3e258
- Intermediate fix to allow register allocator failure
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-05-13 21:02:26 +00:00
a96d6a9dab
- Add a test to make certain romcc is properly allocating registers.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-05-13 20:45:19 +00:00
0babc1c116
- Implement support for structures, typedefs, and __builtin_rdmsr, __builtin_wrmsr in romcc
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-05-09 02:39:00 +00:00
ba8c25affb
- Update the test cases for romcc
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-05-08 00:31:34 +00:00
ab2ea6b474
- misc minor fixes
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-26 03:20:53 +00:00
2c791ce2c1
- Minor bug fixes
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-26 02:14:06 +00:00
501eb25247
- Almost implement failover booting on the solo.
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I need a very early Hypertransport setup to get anything more going.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-25 03:02:13 +00:00
eb00fa5c11
- Commit a working pirq table for the AMD solo
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-25 02:02:25 +00:00
825dd3361b
- simple bug fixes
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-24 23:25:29 +00:00
497eb85441
- irq routing table generated by getpir
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-24 06:57:32 +00:00
8cd55d7f4a
- More attempts to leave irqs in a working state.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-24 06:56:37 +00:00
Ronald G. Minnich