If AGESA is added as a raw binary (and not a stage), then cbfstool
does not perform relocation. In this case, it should be added only to
COREBOOT (i.e. default) CBFS since the binary needs to be present only
in one specific location that is present in the default CBFS.
Change-Id: I7a7edc217663f9d1d36b05308bbd35f56a28b9b1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
coreboot might not store wifi SAR values in VPD and may store it in
CBFS. Logging the message with 'error' severity may interfere
with automated test tool.
Lowering severity to BIOS_DEBUG avoids this issue.
BUG=b:171931401
BRANCH=None
TEST=Severity of message is reduced and we don't see it as an error
Change-Id: I5c122a57cfe92b27e0291933618ca13d8e1889ba
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
SystemMemoryMapHob
This field from SystemMemoryMapHob can be used to define error
correction type in SMBIOS type 16.
Tested=On OCP Delta Lake, the value is expected.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47505
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The headers added are generated as per FSP v2385_02.
Previous FSP version was 2376.
Changes Include:
- add VtdIopEnable, VtdIgdEnable, and VtdIpuEnable UPDs in Fspm.h
TEST=Build and boot JSLRVP
Change-Id: I268eca1bcbbf26d4dc4ecf54d432cdb6ad49b4eb
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47500
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was supposed to return true for both S2 and S3, but
level S2 was never stored in acpi_slp_type or otherwise
implemented.
Change-Id: Ida0165e647545069c0d42d38b9f45a95e78dacbe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested=On OCP Delta Lake, verify the memory map hob data are correct.
Change-Id: I86bd809e21270395c4115788e5521606e9dcc2fb
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update FSP headers for Tiger Lake platform generated based on FSP
version 3444. Previous version was 3425.
BUG=b:173160613
BRANCH=none
TEST=build and boot delbin
Cq-Depend:chrome-internal:3403586, chrome-internal:3403392
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I9e5de1617d00cd7543d4de1660f448e2fe220b0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47555
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel CPX-SP FSP ww45 release annotates default values for FSP-M UPD
variables.
FSPM MemRefreshWatermark option support is present in FB's CPX-SP
FSP binary, but not in Intel's CPX-SP FSP binary. In FB's CPX-SP
FSP binary, this option takes the space of UnusedUpdSpace0[0].
For DeltaLake mainboard, if corresponding VPD variable is set, use it
to control the behavior. Such control is effective when FB's CPX-SP
FSP binary is used.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I57ad01f33b92bf61a6a2725dd1cdbbc99c02405d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Replace the initial bl_errorcodes_public.h (a temporary, minimal
version) with the full version released by AMD.
BUG=None
TEST=Build
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I82585c74d74139a96419b9bffe1df3b8c344eb5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Remove all typedefs and cleanup references to all structs and enums.
BUG=b:159061802
TEST=Boot morphius to shell.
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
No recent Chromebooks have used I2C for TPM communication, and as a
result, a bug has crept in. The ability to extract Cr50 firmware string
is only supported via SPI, yet code in mainboard and vendorcode attempt
to do so unconditionally.
This CL makes it such that the code also compiles for future designs
using I2C. (Whether we want to enhance the I2C protocol to be able to
provide the version string, and then implement the support is a separate
question.)
This effort is prompted by the desire to use reworked Volteer EVT
devices for validating the new Ti50/Dauntless TPM. Dauntless will
primarily be using I2C in upcoming designs.
BRANCH=volteer
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
Change-Id: Ida1d732e486b19bdff6d95062a3ac1a7c4b58b45
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
The passive clause is constructed with the past participle, which is
*defined* in this case. Fix all occurrences in AMD vendor code with the
command below.
$ git grep -l "is define at" src/vendorcode/amd/ | xargs sed -i 's/is define at/is defined at/'
Change-Id: Ia26c87aecb484dcb55737e417367757d38ce3b56
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
DRAM part number may not be provisioned in CBI during early stages of
development. Logging the debug statement with error severity interferes
with some of the test tools. Lower the severity of debug statement to
BIOS_DEBUG.
BUG=b:170529094
TEST=Build and boot to ChromeOS in Drawlat.
Change-Id: Ib0c707ec6478060d6e18ea01cc467dfda00a6d42
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update FSP headers for Tiger Lake platform generated based on FSP
version 3373. Previous version was 3333.
Changes include below UPDs:
ITbtPcieTunnelingForUsb4
SlowSlewRate
FastPkgCRampDisable
BUG=b:169759177
BRANCH=none
TEST=build and boot delbin/tglrvp
Cq-Depend:chrome-internal:3308203, chrome-internal:3308204
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45630
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The fields from SystemMemoryMapHob can be used to generate SMBIOS type 17.
Tested=On OCP Delta Lake, verify the values are expected.
Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45797
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PSP bootloader version 0.08.0B.7B added support for the Mod Exp
svc call.
BUG=b:169157796
TEST=Build
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I1ce69c80cec77e1692cf9713a739cc4da4677da6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45942
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CHROMEOS_DRAM_PART_NUMBER_IN_CBI Kconfig option to declare whether
the SPD Module Part Number (memory part name) is stored in the CBI.
Move mainboard_get_dram_part_num() into src/vendor/google/chromeos
to allow mainboards to use it without having to duplicate that code
by enabling the CHROMEOS_DRAM_PART_NUMBER_IN_CBI config option.
BUG=b:169789558, b:168724473
TEST="emerge-volteer coreboot && emerge-hatch coreboot &&
emerge-dedede coreboot && emerge-nocturne coreboot" and verify it
builds.
Change-Id: I0d393efd0fc731daa70d3990e5b69865be99b78b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Intel CPX-SP FSP ww38 release made some changes to FSP-M header
file. Those changes do not need corresponding soc code change.
TESTED=built image with ww38 FSP RELEASE binary, booted DeltaLake
DVT to target OS.
Change-Id: I320c4a674f9f4d37c30ce6df510f18ad1ae057eb
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This adds eMMC preset settings.
It also fixes some formatting and a comment.
BUG=b:159823235
TEST=Build test
Cq-Depend: chrome-internal:3251807
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic5caff594157e03d792b999ca60274cf53c708e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45096
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PREV_BOOT_ERR_SRC_HOB is generated by CPX-SP FSP by interrogating
error status registered (such as MCA MSRs) to list fatal errors happened
during the previous boot session.
The header file supports 3 different error source types. CPX-SP FSP
supports only McBankType.
Change-Id: I9b88af17075b98e88c7e94e55fea37627ec03cd0
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44973
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use one tab instead of 8 spaces at the beginning of the lines added in
commit 39a8040ddc.
Change-Id: I8d7553e1b41dbbbdabd7392028a51e3a0f79c97a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Most of them are needed for SMBIOS type 17 creation.
Tested=With FSP WW36 verified the printed hob values match
with FSP hob data.
Change-Id: I02f4600f1be39e2576d7c84a5a6b6672ebb7034b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PSTACK2 (IOU3) should be stack number 4, mainboard uses stack number as
the index to access the bus number array read by get_stack_busnos().
Without the fix it would get the wrong bus number (0xb1).
Tested=On OCP Delta Lake, dmidecode -t 9 to verify slots bus number on
IOU3 are correct (0xb2).
Change-Id: I1c9e49bbc9a00de82d1fc67b3b4ed47e03eacdda
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update FSP headers for Tiger Lake platform generated based FSP
version 3333. Previous version was 3313.
Changes Include:
1. Update comments
2. Add new UPD for Gpio Override support
BUG=b:166790597
BRANCH=none
TEST=build and boot volteer proto2
Cq-Depend:chromium-internal:3240396,chromium-internal:2870145
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie3f0688143eef532946c7a2141909c1ac173fc2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44912
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel CPX-SP FSP ww34 release added some features:
a. change DDR frequency limit.
b. define MRC debug message verbosity level.
c. enable/disablee of PCH DCI.
In addition, there are some changes to HOB data structures.
Update UPD and HOB header files and adapt soc accordingly.
TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It seems that GCC's LTO doesn't like the way we implement
DECLARE_OPTIONAL_REGION(). This patch changes it so that rather than
having a normal DECLARE_REGION() in <symbols.h> and then an extra
DECLARE_OPTIONAL_REGION() in the C file using it, you just say
DECLARE_OPTIONAL_REGION() directly in <symbols.h> (in place and instead
of the usual DECLARE_REGION()). This basically looks the same way in the
resulting object file but somehow LTO seems to like it better.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6096207b311d70c8e9956cd9406bec45be04a4a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This unlocks 1866 MHz frequency for AMD boards of f15tn family.
Tested on ASUS A88XM-E with A10-6700 and Crucial BLT8G3D1869DT1TX0.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I547d7e9ca89524d66ee0ee307de41699d991f9fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40490
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Each variant WiFi SAR CBFS will be added with the default name
"wifi_sar_defaults.hex".
so we just need to look up the default CBFS file as the WiFi SAR
source.
BUG=b:159304570
BRANCH=zork
TEST=1. cros-workon-zork start coreboot-private-files-zork
2. emerge-zork chromeos-config coreboot-private-files-zork \
coreboot chromeos-bootimage
Change-Id: Idf859c7bdeb1f41b5144663ba1762e560dcfc789
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44672
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move a size of DDR3 SPD memory (always 256 bytes) to a common define.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Introduce FSPT_ARCH_UPD and FSPS_ARCH_UPD to support debug events
and multi-phase silicon initialization.
For backward compatibility the original structures are kept and
new ARCH_UPD structures will be included only when UPD header
revision equal or greater than 2.
ref:
- https://bugzilla.tianocore.org/show_bug.cgi?id=2781
BUG=b:162184827
BRANCH=None
TEST=Build and boot JSLRVP
Cq-Depend: chrome-internal:3221772
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I728aff1df3d361e21e4617647c4ec0e2d345a8c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
