Commit Graph

49756 Commits

Author SHA1 Message Date
Matt DeVillier adf21da264 mb/google/volteer: add VBTs for lindar variant
Add VBT data files, ensure secondary VBTs compiled in as needed,
select INTEL_GMA_HAVE_VBT.

TEST=build/boot lindar variant with FSP/GOP display init, edk2 payload

Change-Id: I81022670fabda7994e292d333c999b508e61b469
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20 14:35:26 +00:00
Matt DeVillier 6b650811e5 mb/google/dedede: add VBTs for drawcia, mangolor variants
Add VBT data files, ensure secondary VBTs compiled in as needed,
select INTEL_GMA_HAVE_VBT.

TEST=build/boot drawcia, mangolor variants with FSP/GOP display
init and edk2 payload

Change-Id: I58a2ed59bd858ce772e92f6659d341036823b11a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20 14:35:02 +00:00
Reka Norman 897f72a111 mb/google/nissa/var/nivviks: Change ISH name to adl_ish_lite.bin
The ISH build target used for nissa is called adl_ish_lite: CL:3925007,
and by default the binary is installed as
/lib/firmware/intel/adl_ish_lite.bin

We could change the installed name, but it's nicer to keep it consistent
with the build target, so change the name in coreboot instead.

BUG=b:234776154
TEST=Build and boot nirwen, check firmware name is updated in SSDT

Change-Id: I983a38d08e758cf5a12a3f91a601c7e57d42c0cb
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-10-20 14:34:48 +00:00
David Wu 6fb95d8558 mb/google/brask/var/kuldax: Set PL and PsysPL
1. Set the PL1, PL2 and PL4.
2. Set PsysPL2 and PsysPmax.

BUG=b:253380352 b:253542746
TEST=Compare the measured power from adapter with the value of 'psys'
     from the command 'dump_intel_rapl_consumption'.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I0a7ff64689b39e7754e0aed2f6869881a682fc93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68437
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-19 09:35:50 +00:00
Zanxi Chen 55d47bd1bf mb/google/dedede/var/storo: Disable PCIE RP8 and CLKSRC4
This change disables unused PCIE RP8 and CLKSRC4. Without this change
storo cannot enter into s0ix properly.

BUG=b:219376808
TEST=Built and verified in storo

Change-Id: I9867825ce53de72ef73920c153002bc3be4dbd2d
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Aamir Bohra <aamirbohra@google.com>
2022-10-18 23:10:37 +00:00
Felix Held 164c5eda27 soc/amd: factor out writing extended PM registers in FADT
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I59985f283f1694beeacb0999340111146fa3f39b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-18 23:07:37 +00:00
Fred Reitberger 13831223be soc/amd/*/i2c: Move reset_i2c_peripherals to i2c.c
Move i2c SoC related code from early_fch.c to i2c.c

TEST=build boards for each SoC

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I69d4b32cf95ce74586bd8971c7ee4b56c1c2fc04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-18 16:09:44 +00:00
Fred Reitberger f2b36036c7 soc/amd/morgana/gpio: Update gpio definitions for morgana
Update the GPIO definitions for morgana per PPR #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I7fa4aaf81b5487f7548f430cb35630aca8be732f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-18 16:08:45 +00:00
Gwendal Grignou 4ee037e8f0 mainboard/google: Remove ACPI ALS device
Remove the ACPI ALS device from the EC configuration for newer devices,
because some do not have light sensors, and those who do have their ALS
presented through the new EC sensor interface already.

Inspired from commit ("f13e2501525f ("UPSTREAM: mainboard/google/eve: Remove ACPI ALS device")

BUG=b:253967865
BRANCH=none
TEST=Boot a device and ensure that 'acpi-als' device is not present
in /sys/bus/iio/devices.

Change-Id: Ibcfa9e8c5a4679d557150998fd255789d3f8a272
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68493
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-18 16:08:10 +00:00
Teddy Shih 630fb54886 mb/google/dedede/var/beadrix: Update SoC gpio pin of USB camera
Update SoC GPIO setting of camera according to beadrix schematics.

GPP_D13 : NC -> PLTRST (EN_PP2800_CAMERA)

BRANCH=dedede
BUG=b:247178737,b:244120730
TEST=on beadrix, validated by beadrix seconds_system_resume < 500 ms.

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Id00cb85cdad900c03842ad69707966aa62410efd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
2022-10-18 13:13:25 +00:00
Matt DeVillier 10817c7d5a mb/google/glados: Fix WiFi SAR options
SAR-related Kconfigs are only used by ChromeOS, and should be guarded
properly as such (as most other boards do).

TEST=build glados w/o CONFIG_CHROMEOS, verify SAR-related Kconfigs not
selected.

Change-Id: Id8abf68ed2e9720b5580f7965208dbe36460af07
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68458
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-18 13:12:34 +00:00
Matt DeVillier ad60b7fb56 mb/google/reef: Fix WiFi SAR options
SAR-related Kconfigs are only used by ChromeOS, and should be guarded
properly as such (as most other boards do).

TEST=build reef w/o CONFIG_CHROMEOS, verify SAR-related Kconfigs not
selected.

Change-Id: I4fe3092e620bcbc33b0411ea69e55154fc118aa4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68457
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-18 13:12:00 +00:00
Matt DeVillier 856a3f4a3c mb/google/sarien: Fix WiFi SAR options
SAR-related Kconfigs are only used by ChromeOS, and should be guarded
properly as such (as most other boards do).

TEST=build sarien w/o CONFIG_CHROMEOS, verify SAR-related Kconfigs not
selected.

Change-Id: I424033e087bc37c651a922273718fc229b720448
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68456
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-18 13:11:50 +00:00
Amanda Huang c586e9a0a3 mb/google/skyrim/var/skyrim: Add supported memory parts
Add two memory parts and generate the associated DRAM part ID.

1) Hynix H58G66AK6BX070
2) Micron MT62F1G32D2DS-026 WT:B

BUG=b:251363645
TEST=none

Change-Id: Iceb31576533a5b29c5957170473152014fc7e9c8
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-10-18 03:23:09 +00:00
Yu-Ping Wu 3a1333da36 mb/google/corsola: Configure TPM IRQ as EDGE_FALLING
When the GSC is ready for the next transaction, it triggers a
GSC_AP_INT_ODL (active low) pulse with 100us duration to notify the AP.
Currently the TPM IRQ is configured as EDGE_RISING. Changing it to
EDGE_FALLING would speed up each register access by 100us. On Kingler,
this saves 20ms for the boot time (0.93s -> 0.91s).

BUG=b:235185547
TEST=emerge-corsola coreboot
TEST=Kingler booted without TPM errors
BRANCH=none

Change-Id: Id282e0f35694bd151781845cbd5aa4b389a30ddc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-10-18 03:01:16 +00:00
Martin Roth a2efadd1b4 MAINTAINERS: Create release team
To help make sure that future releases are done correctly and on time,
we are setting up a team with the shared responsibility for doing the
releases and maintaining the release notes, scripts, and documentation.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5ef5b10fce9b16241de548df225fd12c9a7e199f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-17 23:07:03 +00:00
Matt DeVillier 6cb30195ad mb/google/brya: Guard FMD selection with CHROMEOS
Allows brya boards to use coreboot-generated FMAP layout
when building for non-ChromeOS target.

TEST=build/boot brya/banshee with edk2 payload, non-ChromeOS build

Change-Id: I21c2247c034d9bdc49f66771a93abad542a1e1fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17 22:15:18 +00:00
Matt DeVillier 961f94d84e mb/google/dedede: Guard FMD selection with CHROMEOS
Allows dedede boards to use coreboot-generated FMAP layout
when building for non-ChromeOS target.

TEST=build/boot dedede with edk2 payload, non-ChromeOS build

Change-Id: Icb975455cde0d75a5af9130ba3e82a4fb0df5613
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17 22:15:06 +00:00
Christian Walter a8c10c8298 Makefile: Add targets to add and remove symlinks
When "make symlink" is run, it looks for symlink.txt files recursively
under site-local directory, and make symbolic links accordingly.

"make clean-symlink" removes the symbolic links made.

One application is for development of support for new processors and/or
new mainboards, where new directories are added, along with some common
code changes.

Change-Id: I3fa119675ecca1626d70375a61e8a71abec6a53b
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-17 14:00:46 +00:00
Michał Żygowski ccbb98880b Documentation/drivers/cbfs_smbios.md: Describe CBFS serial number
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6f0963417c7c580f903922ac88c95569c8782bdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-10-17 13:58:23 +00:00
Arthur Heymans d0b2aa1c5d nb/amd/agesa/fam16kb: Remove dead code
Setting up HT resource seems to be copied from the old native family10
code. It is however not used as no device has a child device below 18.0
in any of the fam15tn board device trees.

Setting up HT resources is therefore done by AGESA and resource
allocation mostly happens to work.

Change-Id: I7edf19f71095fb38161f19d511997cdc2fe0d76c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17 13:48:00 +00:00
Arthur Heymans 6fa6e11d78 nb/amd/agesa/fam15tn: Remove dead code
Setting up HT resource seems to be copied from the old native family10
code. It is however not used as no device has a child device below 18.0
in any of the fam15tn board device trees.

Setting up HT resources is therefore done by AGESA and resource
allocation mostly happens to work.

Change-Id: Id95e2dec4a6f3e70234fff1df67ee61e08731400
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68411
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17 13:47:48 +00:00
Zhixing Ma 42bb7df28c arch/x86/smbios.c: Fix Upgrade processor information in SMBIOS
The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed,
and upgrade (socket type). This patch implements upgrade function.
Refer to SMBIOS spec sheet for documentation on cpu socket values:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf

BUG=NONE
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that SMBIOS processor upgrade value is correct.

Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I5796d31fa2d31b17afa5eddde0799b0f68d69909
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68024
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-17 13:44:58 +00:00
Bill XIE 854c897eb8 mb/supermicro/x9sae: Add full NCT6776 support
X9SAE has a PS/2 controller for keyboard and mouse but its definition
in ACPI used to be missing, and X9SAE used to use a generic SuperIO
support initially generated by autoport, so the full NCT6776 support
is added here like x9scl.

Test result:
Log lines like

    i8042: PNP: No PS/2 controller found.
    i8042: Probing ports directly.
    serio: i8042 KBD port at 0x60,0x64 irq 1
    serio: i8042 AUX port at 0x60,0x64 irq 12
    mousedev: PS/2 mouse device common for all mice

become

    i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at
        0x60,0x64 irq 1,12
    serio: i8042 KBD port at 0x60,0x64 irq 1
    serio: i8042 AUX port at 0x60,0x64 irq 12
    mousedev: PS/2 mouse device common for all mice

and more sub-devices within SuperIO is handled by the PNP driver.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ie5e73e8c3fc4e57c6683d7a7ca70e96c64dd9366
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17 13:43:50 +00:00
Felix Held de10d5bf4d soc/amd: factor out common noncar bootblock
This code is identical for all non-CAR AMD SoCs, so factor it out to
soc/amd/common/block/cpu/noncar/bootblock.c to avoid code duplication.
Also integrate the bootblock.c improvement to include cpu/cpu.h which
provides cpuid_eax from commit 68eb439d80 ("soc/amd/picasso: Clean up
includes").

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I42e4aa85efd6312a3ab37f0323a35f6dd7acd8e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-17 13:43:25 +00:00
Fred Reitberger f73a3a5e08 soc/amd/*/smihandler: Make fch_apmc_smi_handler common
Rename soc/amd/common/block/cpu/smm/smi_ampc_helper.c to smi_apmc.c and
add the fch_apmc_smi_handler function.
Remove the duplicated function from picasso, cezanne, mendocino, and
morgana SoC.

The stoneyridge soc does not implement the APM_CNT_SMMINFO handler, so
give the handler a unique name that does not conflict with the common
handler name.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I2e6fb59a1ee15b075ee3bbb5f95debe884b66789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68441
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-17 13:42:46 +00:00
Elyes Haouas 9efe34a396 mb/ocp/deltalake: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If68ce4fef69a2466e76fc7fc504c00ee915e3e36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-10-17 13:42:01 +00:00
Fred Reitberger bc4b85f371 MAINTAINERS: Add AMD Morgana SoC and birman board
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Iae811c97aba15dd6c9c740aedd7c802e14f53788
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-17 13:41:33 +00:00
FrankChu 666f886ce7 mb/google/dedede/var/pirika: Add fw_config probe for ALC5682-VD & VS
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11)
for codec selection.

ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"

BUG=b:244620955
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ia6cb56e76bc4e245a32f29b19226fa4fae330c92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
2022-10-17 13:41:15 +00:00
Elyes Haouas c35f281934 mb/*/*/gpio.h: Remove unused <soc/gpe.h>
Change-Id: I9b03ccc1100307e3c24393903600d18f6cc9abdc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68378
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-10-17 13:40:55 +00:00
Martin Roth f4c97ea131 Documentation/security: Update list of boards supporting vboot
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ie6ecb3ed97ed0581300411962c3b1bba416e0224
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68242
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-16 20:14:31 +00:00
Martin Roth b6777d8235 Docs/releases: Add 4.19 relnotes template and update index
The 4.19 release is planned for January 2023.  Please add any updates to
the coreboot code that are should go into the notes between now and
then.  This helps in that you get to phrase the update the way you want,
and it lessens the load for the release managers.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ib5a7ddfc6cb1a8e0a485c1e1810631c86f4083c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-16 20:14:24 +00:00
Martin Roth f9c606901e Docs/releases: Update coreboot-4.18 release notes
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5cf38463e44f9abaadb4dc47dbf48ef0f0514bc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-16 20:14:18 +00:00
Sean Rhodes d8e35808ed mb/starlabs/lite/{glk,glkr}: Enable PMC
Enable PMC in devicetree so that resources are allocated properly
for it.

Tested on StarLite Mk III & IV, and both can power on correctly.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib4384b55751a9979e470dd04f6814d4ca170ff34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67409
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-15 22:34:40 +00:00
Sean Rhodes bed947368c mb/starlabs/lite: Reset XHCI before entering S5
Reset the XHCI controller prior to S5 to avoid XHCI preventing shutdown.
Linux needs to put the XHCI into D3 before shutting down but the
powerstate commands do not perform a reset.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3be70443eb85a7dff8055c9de0ca2fd89f4fc88d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67678
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-15 22:34:06 +00:00
Sean Rhodes d9ef02ce1d soc/intel/apollolake: Lock down Global SMI
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9377c3b65aa342f754c303148b0b8d826d05bb94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67662
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-15 22:33:54 +00:00
Sean Rhodes 4b966b57ed soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown
Configure FSP S UPDs to allow coreboot to handle the lockdown.

The main change here is setting `Write Protection Support` to 0,
as the default is Enabled, which shouldn't allow writes (even though
it seems to).

The UPDs are identical on APL and GLK, but all ones configured
in this patch have been there since their initial releases.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1f6e5344cab2af7aa6001b9ec0f07b043a9caa8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-15 22:00:42 +00:00
Felix Held 96fa2377e2 treewide: Use 'fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk'
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaecb83c3bc9c75dab427a3ca54da1e6a8f87cf9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-15 16:53:55 +00:00
Felix Held 769b6579da treewide: Use 'fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk'
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id3002dc976b82f71b1f60a6e32b16d60a7bbbead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-15 16:53:45 +00:00
Felix Held f0d62cefe8 mb/amd/padmelon: rename to pademelon
This AMD reference board is called Pademelon and not Padmelon, so fix
the name in coreboot. Also update the corresponding documentation.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id1c7331f5f3c34dc7ec4bc5a1f5fe3d12d503474
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-15 16:53:19 +00:00
Elyes Haouas 68eb439d80 soc/amd/picasso: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I4ed869627af11b607f910644b6f21898f7c7bba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-14 21:32:23 +00:00
Arthur Heymans 7f7b01d467 soc/amd/sata.c: Hook up directly in devicetree
Cezanne has two SATA controllers, but doesn't select
SOC_AMD_COMMON_BLOCK_SATA, so it's not added to the SATA devices in the
Cezanne chipset devicetree.

Change-Id: If7f0a9638151cf981d891464a2c3a0ec5fc9c780
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-14 20:19:46 +00:00
Arthur Heymans b3dcb96dc5 soc/amd/*: Hook up IOMMU ops in devicetree
This removed the need to maintain a PCI driver.

Change-Id: I43def81d615749008fcc9de8734fa2aca752aa9d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14 20:19:30 +00:00
Arthur Heymans c6f029cbcc soc/amd/*: Hook up LPC ops in devicetree
This removes the need for a PCI driver.

Change-Id: I6674d13f434cfa27fa6514623ba305af6681f70d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14 20:19:03 +00:00
Arthur Heymans fd2bb9b6bc soc/amd/*: Hook up SMBus ops to devicetree
This removes the need for a PCI driver.

Change-Id: Iab75f8c28a247f1370f4425e19cc215678bfa3e5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14 20:18:45 +00:00
Felix Held 65d73cc457 soc/amd: factor out common eMMC code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If5447f9272183f83bc422520ada93d3cfd96551e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14 20:18:29 +00:00
Matt DeVillier 5e2f1b1e64 ec/google/chromeec: Demote LPC EC error printk from ERR to SPEW
Several EC host commands check for support of a given feature or msg
version, and a non-zero response does not necessarily indicate an actual
error. Since the caller is (should be) handling the non-zero response to
the host command, demote the EC printk from ERR to SPEW to clean up the
console log and prevent non-errors from causing false failures in
firmware tests.

BUG=b:238961053

Change-Id: Ib7afc0b7e5b571acb56252f7adb518a6b2716b62
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68259
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 16:10:23 +00:00
Hsuan Ting Chen fec16a3574 util/elogtool: Add support for parsing CrOS diagnostics log
Remove the "_DEPRECATED_" tag from ChromeOS diagnostics event and add a
subtype: "ELOG_CROS_DIAGNOSTICS_LOGS" under it.

The data of "ELOG_CROS_DIAGNOSTICS_LOGS" (0x02) contains:
* An uint8_t of subtype code
* Any number of "ChromeOS diagnostics logs" events

Each "ChromeOS diagnostics log" represents the result of one ChromeOS
diagnostics test run. It is stored within an uint8_t raw[3]:
 * [23:19] = ELOG_CROS_DIAG_TYPE_*
 * [18:16] = ELOG_CROS_DIAG_RESULT_*
 * [15:0]  = Running time in seconds

Also add support for parsing this event. The parser will first calculate
the number of runs it contains, and try to parse the result one by one.

BUG=b:226551117
TEST=Build and boot google/tomato to OS,
localhost ~ # elogtool list
0 | 2022-09-26 04:25:32 | Log area cleared | 186
1 | 2022-09-26 04:25:50 | System boot | 0
2 | 2022-09-26 04:25:50 | Firmware vboot info | boot_mode=Manual recovery
  | recovery_reason=0x2/0 (Recovery button pressed)
  | fw_tried=A | fw_try_count=0 | fw_prev_tried=A
  | fw_prev_result=Unknown
3 | 2022-09-26 04:25:50 | EC Event | Keyboard Recovery
4 | 2022-09-26 04:26:01 | Memory Cache Update | Normal | Success
5 | 2022-09-26 04:26:06 | System boot | 0
6 | 2022-09-26 04:26:07 | Firmware vboot info | boot_mode=Diagnostic
  | fw_tried=A | fw_try_count=0 | fw_prev_tried=A
  | fw_prev_result=Unknown
7 | 2022-09-26 04:26:07 | Diagnostics Mode | Diagnostics Logs
  | type=Memory check (quick), result=Aborted, time=0m0s
  | type=Memory check (full), result=Aborted, time=0m0s
  | type=Storage self-test (extended), result=Aborted, time=0m1s

Change-Id: I02428cd21be2ed797eb7aab45f1ef1d782a9c047
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-14 16:06:39 +00:00
Subrata Banik 4e85ec705e soc/intel/alderlake: Create helper header file for UFS
This patch creates helper header file (ufs.h) for UFS to keep
required registers details and ACPI device id for UFS.

BUG=none
TEST=Able to build and boot Google/Kano.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If08c54eb706876a4255542a708aa5fcd8bf43c55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68299
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-14 16:04:15 +00:00
Subrata Banik 9fb58575d6 soc/intel/alderlake: Add UFS PCR ID
Add UFS PID (`PID_UFSX2`) value 0x50.

BUG=none
TEST=Able to build and boot Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I229469475cd116bf911b6530c3c819d00c808aa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68298
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14 16:03:28 +00:00