With the latest hardware revision, the polarity of GPP_B5 has been
changed. For a full-populated DRAM configuration, the input signal is
now connected to 3.3 V and for a half-populated configuration it is
connected to ground.
BUG=none
TEST=Use different populated mainboards and check coreboot log
GPP_B5 = 0:
[INFO ] meminit_channels: DRAM half-populated
[DEBUG] 1 DIMMs found
GPP_B5 = 1:
[DEBUG] 2 DIMMs found
Change-Id: Iaa3a63fa52c802d8f5d8c6cc11dd6edfac117e88
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76434
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify reset_delay_ms from 300ms to 6ms for ELAN EKTH7D18.
BUG=b:285999032
BRANCH=firmware-nissa-15217.B
TEST=boot uldren to ChromeOS and touchscreen is workable.
Change-Id: Iffcddbe7735b7a837887dec68e1270c2af5f4556
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76417
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Disable scalability tracking for autonomous frequency control in
order to improve power and performance.
BUG=b:280021171
TEST=Boot to OS on brya0
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: If71ee5374c67611b32691bbec4effdf828b3e566
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74723
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Hook the newly exposed EnableHwpScalabilityTracking UPD up so that
boards can configure is via devicetree.
BUG=b:280021171
TEST=Verified by enabling/disabling the UPD on google/brya
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I4c8845c445d46caa30a0245386ab9cd690d2623f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74722
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Hook the newly exposed DisableSagvReorder UPD up so that
boards can configure is via devicetree.
BUG=b:268546941
TEST=Verified by enabling/disabling the UPD on google/brya
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I89235d9384b67f03e68425aadd3458e1c77ff555
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Disable re-ordering SaGv point on warm reset so that most
performant SaGv point is picked after memory training and
boot time is reduced.
BUG=b:268546941
TEST=Observe boot time improvement with these two UPDs set
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I44a1c054d52bb8585a320bb8a52a8f137e639804
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74721
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable upd to reduce size of the memory test.
BUG=b:268546941
TEST=Observe boot time improvement with these two UPDs set
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I95c7d8503596c2712d7abe123ed1f911ac4abacf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Hook the newly exposed LowerBasicMemTestSize UPD up so that
boards can configure is via devicetree.
BUG=b:268546941
TEST=Verified by enabling/disabling the UPD on google/brya
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib813e9f3b7419a3cb54b4e176dcc5cc74a783dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74718
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
The headers added are generated as per FSP v4221.00
BUG=b:290038558
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I23f6e1e4baa39883475cd93fa6aabcec4e7152cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76147
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
test: Warm reboot from Windows 11 w/ Samsung 980 Pro on Banshee
Verify memory type detected properly and following boot works
Change-Id: Iad0a2024bd0ef39f6ab57ff7a6e6aa651d7882a6
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Avoid enabling SIO UART to prevent conflicts with BMC console; utilize VUART0 instead.
TEST=Build for sbp1 & make sure coreboot logs do not spill into BMC
console. Also made sure coreboot logs are accessible via VUART.
Change-Id: I2d4bbd74bb7d37b74378650dd569bca7fa13c29b
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76396
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Set coreboot ready gpio. This gpio is used to indicate to BMC of BIOS
completion.
Change-Id: Iaed8bec12e593cf1687d973765b0117bdc115cb8
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76404
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only A step ADL-S CPUs were added to CPU table for MP init. Add
the remaining ADL-S CPUs to the table.
TEST=Boot MSI PRO Z690-A with C step i5-12600K and observe coreboot
no longer uses generic CPU ops.
Change-Id: I3692a3f089ca23af860bd1c8e3c29fee9d9234c9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76204
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
In newer ADL/RPL PCH EDS 619362 revision 2.1 the ESPI ID 0x7A8A
belongs to the W790 chipset. Earlier revisions had the chipset with
ID 0x7A8A named W685, which was probably just a temporary name.
Change the naming throughout the tree to W790, which is the real
existing chipset.
Change-Id: I87603298d655e9bf898b34acdd5b403f5affaee3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
CPUID is the same for Alder Lake and Raptor Lake S and HX variants.
To reduce the confusion and concerns how to name the macros, remove
the suffixes from macros and platform reporting strings. Thankfully
the stepping names are unique across mobile (P suffixed) and desktop
(S and HX suffixed) SKUs. Distinguishing the S from HX is possible via
host bridge PCI ID.
Change-Id: Ib08fb0923481541dd6f358cf60da44d90bd75ae2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Add PCI IDs, default VR values and power limits for Raptor Lake S
CPUs. Based on docs 639116 and 640555.
TEST=Tested on a MSI PRO Z690-A (ms7d25) with i9-13900K with Ubuntu
22.10 and LinuxBoot (Linux + u-root). Also tested on MSI PRO Z790-P
with i5-13600K (UEFI Payload) usign RPL-S IoT FSP and Ubuntu 22.04.
Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155
Signed-off-by: Max Fritz <antischmock@googlemail.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69798
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
The static function read_space_firmware() is used only once, so merge it
into antirollback_read_space_firmware(). Also change a debug log to
error.
BUG=none
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: I8abcb8b90e82c3e1b01a2144070a5fde6fe7157f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
The CB:76219 removed mtk_i2c_bus_init() from tps65132s_setup(), so
we should initialize I2C bus for TPS65132 in mainboard now.
BUG=None
TEST=./util/abuild/abuild -t google/geralt -a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Iacf78221d2416f41467c709402b7e02e03dc5fc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Some of the microcode update files listed in the Makefile are redundant:
* 06-97-02 is exactly the same as 06-97-05
* 06-9a-03 is completely contained in 06-9a-04 (at offset 0x1c400)
So drop these files. This saves us about 200KiB CBFS space in each case.
Change-Id: Idfcab1de26ea4712295c1d22790bab3a73c17f93
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA
- Don't have resources overlap
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ia8562660cf69d188b0cab4869aa3190f014dbfdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
There is no PCH FIVR participant on MTL and we should remove it
in Rex.
TEST=compile ok and make sure there no TPCH device in acpi
BUG=b:290322310
Change-Id: Icf4be86da3f3cb9b1f0a3f2586b029a533c3e6a9
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76402
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5c6dcbc8ed79b79ee097c7a14fe14ed87af33c2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I502eeb39c05bd4d00b01976c96884636baf3030c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch drops the unnecessary alignment of 64 bytes that was
introduced when implementing the split Intel microcode packing logic
into CBFS.
- The 16-byte alignment that is already used for Intel microcode is
sufficient.
- Removes unnecessary alignment check of 64 bytes against an AMD
platform specific config.
TEST=Able to build and boot google/rex without any functional
impact.
Change-Id: Icc44e9511e321592de7ab8d1346103d0a9951c9b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76397
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
All requests to acpica.org are redirected to an intel.com site now,
which breaks our buildgcc script as it's unable to download the source
tarball. Use GitHub again as it's a more reliable source.
*rant*
Change-Id: Ie4570539d6c8abe59295e5a29b323b091e939f90
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76399
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The commit 4d8da8ed ("Docs: Update sphinx targets with the build directory")
introduces an additional variable intending to allow an user to specify
a different build directory. Since the variable is not writable from the
outside and also the Docker container used to build doc.coreboot.org
calls the Makefile with `BUILDDIR` instead of `SPHINXDIR`, building the
documentation within the container doesn't work anymore.
Thus, change the variable name to `BUILDDIR` and make it writable.
Steps to reproduce:
cd util/docker
make doc.coreboot.org
make docker-build-docs
Change-Id: Ibc44134cf1996592597252aeb9dcf7ffb3378ee3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
During the ACPI dump of the System Resource Affinity Table (SRAT), it
was noticed that the reserved field within the Memory Affinity structure
contained a non-zero value. This commit addresses the issue by
performing a memset to zero on the reserved field, ensuring the
avoidance of any potential problems arising from garbage values.
TEST= Build for ibm/sbp1 & make sure SRAT Memory Affinity entries
reserved fields read zeroes
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: I4ba697a6bd59054e74c84b98f3d9b517d333a5d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75417
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked
for CNVi to function properly with the connected bluetooth devices and
wake up from low power state.
BUG=None
TEST=None
Change-Id: I977493fd95a99381279f5a3f5e679e4893369b8a
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked
for CNVi.
Meteor Lake rex platform does not wake up from low power state by
bluetooth keyboard and mouse properly. It is identified that IO Standby
State needs to be configured as masked to function properly for CNVi.
BUG=None
TEST=Make rex platform suspend to s0ix state and press a key from
bluetooth keyboard. Check the platform wakes up properly from s0ix.
Change-Id: Ia98abde584699fa01acba47a9df4ef6332ac16fd
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76338
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The actual NVM size of camera module is 64KB; however, only 8KB is in
use to store data. This reduces the size of both NVM0 and NVM1 to 8KB
to minimize the time taken to read NVM and launch Camera preview.
BUG=NONE
TEST=Launch Chrome camera application and check the time taken to
read eeprom from camera service log and show camera preview. It takes
2 to 3 seconds to show camera preview while it takes 4 to 5 seconds
without the changes.
Before the changes:
06:21:04.204944Z OpenDevice(): camera_id = 1
06:21:07.297584Z Read camera eeprom from eeprom
06:21:08.763491Z Read camera eeprom from nvmem
After the changes:
21:37:23.923676Z OpenDevice(): camera_id = 1
21:37:24.386020Z Read camera eeprom from eeprom
21:37:24.574515Z Read camera eeprom from nvmem
Change-Id: I0e2272b3307fea60ea7406fc6899ae2cb0134fa3
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76189
Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Update eMMC DLL tuning values for improved initialization reliability
BUG=b:289763421
TEST=cold reboot stress test over 5000 cycles on Foresee and Kingston
eMMC
Change-Id: I63077b8717feecf3d50507abb188b7fadb5d6c79
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76221
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch skips reading the MEM_CH_SEL GPIO aka GPP_E13 to determine
the memory channel configuration. The signal behavior is not proper,
hence limiting the DIMM capacity to half (only MC0 is enabled).
This patch always reports the full memory capacity as in dual channel
(both MC0 and MC1 enabled).
This change is necessary to ensure that the system reports the correct
memory capacity, even if the MEM_CH_SEL GPIO is not working properly.
BUG=b:290174538
TEST=Able to detect 32GB memory capacity while booting google/ovis.
Without this patch:
localhost ~ # cat /proc/meminfo
MemTotal: 16183080 kB
With this patch:
localhost ~ # cat /proc/meminfo
MemTotal: 32673664 kB
Change-Id: I6c3fa941abb044b79b13785f7b65d09957f0487d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76359
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Since multiple GFX entry causes an ACPI error when trying to write _DOD
method multiple times, combine the GFX entry into one so that _DOD
method is written just once.
BUG=b:289854155
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I22ad70d50f1aecf8da70e8dd04a36a0a7c1c7609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76329
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This CL corrects the trigger for HID over SPI from Level to Edge.
BUG:None
TEST:Tested with I2C and SPI
Change-Id: I78937af22df22d80a702477b6790a7aa40d782a4
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76116
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The AW37503 is designed to supply positive/negative supply for driving
the MIPI panel. It doesn't integrate non-volatile memory(EEPROM), so we
need to program the registers at boot. We program the target
positive/negative output voltage via I2C and enable the power rails by
pulling up ENP and ENN pins.
On Starmie, we need +/-6V power supply for the MIPI panel. We program
the AW37503 registers in coreboot so that kernel can control AW37503
via fixed regulators without additional settings(what we did for
TPS65132). Since we distinguish AW37503 and TPS65132 by reading the
vendor ID, we need to initialize I2C bus as early as possible.
Therefore, we move mtk_i2c_bus_init() to mainboard_init().
BUG=b:289482828
TEST=emerge-staryu coreboot chromeos-bootimage
TEST=Test the sequence the voltage
Change-Id: I9ccd4db19c93a032226f006eab0427f78f7b6dc8
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76219
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mario Scheithauer