Commit Graph

49406 Commits

Author SHA1 Message Date
Sean Rhodes ed0c7f53eb util/coreboot-configurator: Update Debian dependancies
Change the control file to allow either libyaml-cpp0.6 or
libyaml-cpp0.7.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I754d3e2018ab78fcb657d313c8662313738b190a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-09-22 15:12:59 +00:00
Liju-Clr Chen a8172c329f soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registers
This patch fixes AP hanging issue caused by the handshaking between
MCUPM and CPUfreq driver.

CPUfreq hardware failed to read MCUPM registers due to DEVAPC
permission. Therefore, update the DEVAPC settings to fix this issue.

BUG=none
TEST=CPUfreq in kernel test pass.

Change-Id: I6b30b01fc0be052182599709cbcc9139e6d09742
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67724
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22 08:04:48 +00:00
Johnny Li 93e8f80434 mb/google/brya/var/crota: set tcc_offset value to 1 ℃
Set tcc_offset value to 1℃  in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.

BUG=b:246913963
TEST=USE="project_crota project_brya" emerge-brya coreboot

Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: Ie2f60bed34fbd6fa3624be60138511a22b199a8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-21 15:33:24 +00:00
zhaojohn 88a496a9c8 soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence
This patch provides a workaround which skips requesting IOM for D3 cold
entry sequence.

BUG=b:244082753
TEST=Verified MUX configuration after hot plugging Type-C devices on
Rex and MTL RVP boards.

Change-Id: I17bcde75360c4b2b40885d355702e3e5f45d770a
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-21 15:33:13 +00:00
Jakub Czapiga a0e36d8cba tests: Add support for tests build failures detection
This patch introduces new target: junit.xml-unit-tests, which builds and
runs unit-tests. It also creates build log containing build logs. This
feature allows for one to see build failures in Jenkins dashboard.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I94184379dcc2ac10f1a47f4a9d205cacbeb640fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67372
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-21 14:06:42 +00:00
Tim Wawrzynczak b525ea726b Revert "soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown"
This reverts commit 7ef5376123.

Reason for revert: It was merged before its dependencies so now master is broken.

Change-Id: Ia270efaed4f5c9d0c7b9761ae22dec55f57f74cf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67285
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-20 22:00:53 +00:00
Martin L Roth 19491c526d Revert "Kconfig: Allow x86 to compress pre-ram stages if not run XIP"
This reverts commit 6317aff5b3.

Reason for revert: fix broken tot master

Change-Id: Ie8075cf6c80448bfc957a1e1183f0283d2011b1b
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67287
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-20 21:44:35 +00:00
Angel Pons f37146de32 Revert "mb/prodrive/hermes: Add part numbers to SMBIOS"
This reverts commit d669562663.

Reason for revert: Was submitted out-of-order and with an unresolved
TODO in the commit message.

Change-Id: Id5a8770226afbfcdf63d451157e4586b6cdd5189
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67284
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-20 10:41:36 +00:00
Sean Rhodes e36205daf8 mb/starlabs/starbook/kbl: Correct USB port for Bluetooth
Previously, the Bluetooth interface worked when port 9 was enabled.

Now, it works with port 5 enabled, which matches the schematic.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If783e60c8120adcd6522676cb3343ed46bf39d78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-09-20 08:08:26 +00:00
Ivan Chen a657b1f7ce mb/google/dedede: Resume from suspend on critical battery
This patch makes dedede EC wake up AP from s0ix when the state of
charge drops to low_battery_shutdown_percent.

Demonstrated as follows:

1. Boot OS.
2. Run powerd_dbus_suspend.
3. On EC, run battfake 4.
4. System resumes.

BUG=b:244253629
TEST=Verified on dedede

Change-Id: I39234d2b9e739383b5f96be49077f8c9831fa0fa
Signed-off-by: Ivan Chen <yulunchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-20 08:07:42 +00:00
Jeremy Compostella 92d3899790 soc/intel/alderlake: Explicitly disable Energy Efficiency Turbo
FSP silicon 3347 changed the default value of the EnergyEfficientTurbo
Updateable Product Data (UPD), enabling the Energy Efficient Turbo
feature by default. This feature prevents the cores from entering
Turbo frequency under heavy load.

As a result of this FSP change, coreboot explicitly disables this
feature to stay consistent with commit `caa5f59279e Revert
"soc/intel/alderlake: Enable energy efficiency turbo mode"'.

BRANCH=firmware-brya-14505.B
BUG=b:246831841
TEST=verify that bit 19 of MSR 0x1fc is set. 'iotools rdmsr 0 0x1fc'

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I7498f87eb4be666b34cfccd0449a2b67a92eb9db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-09-20 08:06:50 +00:00
Zhixing Ma c9933b2c27 mb/intel/adlrvp: enable ECT for LP5 memory
On ADLRVP with LP5  memory, MRC team recommends enabling ECT(Early
Command Training) to avoid hang during boot process.

BRANCH=firmware-brya-14505.B
TEST=Booted to OS on ADLRVP with LP5 memory.

Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I2472707825bbbdd8e5c12a714e0d40ea0b458838
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-09-20 08:05:41 +00:00
Sumeet Pawnikar 69b00c6f1b mb/google/brya/variants/skolas: Set power limit values
Skolas board is based on Raptor Lake SoC, not Alder Lake. The code
change sets CPU power limit values as performance configuration based
on various Raptor Lake SoC SKUs as per the document #686872.

BUG=b:242869605
BRANCH=None
TEST=Built and tested on skolas board

Change-Id: Ieb3ca4ff77039412ef56da49e1b438f5e0b9db02
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-09-20 08:03:55 +00:00
Vinod Polimera 25f6db4d2d qualcomm/sc7280: initialize tu struct with zeros
Coverity is throwing a bunch of "maybe uninitialized" errors for tu
struct. Initialize the tu struct with zero.

BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Monitor name: LQ140M1JW49

Change-Id: Ie249ad4f53abc91376445420712364a28618a15a
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2022-09-20 08:02:19 +00:00
Raihow Shi 15d03094cb mb/google/brask/variants/moli: enable ddc on DDI_PORT_2
Enable ddc on DDI_PORT_2 for support DP++.

BUG=b:240382609
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I475e3c0278cfa92ab40ad84f6da580b4cded9933
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-20 08:01:12 +00:00
Gaggery Tsai 517c5a8c54 soc/intel/alderlake: Add power state thresholds
This patch adds power state 1/2/3 threshold setting interfaces
and pass the settings to FSP.

BUG=b:229803757
BRANCH=None
TEST=Add psi1threshold and psi2threshold to overridetree.cb and
     enable FSP log to ensure the settings are incorrect.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I0330ede4394ebc2d3d32e4b78297c3cb328660d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-20 08:00:18 +00:00
Karthikeyan Ramasubramanian 7125318ac4 mb/google/dedede/var/boten: Turn off camera during S0ix
Add a variant specific S0ix hook to fill the SSDT table to disable and
enable camera during suspend and resume respectively.

BUG=b:206911455
TEST=Build Boten BIOS image. Ensure that camera is disabled during
suspend and enabled during resume.

Change-Id: I3229b22b8d8651bf2d9df25b10ce6749efde7cf6
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
2022-09-20 07:58:10 +00:00
Ivy Jian 61e5816b26 mb/google/rex: Add WWAN ACPI support
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM
features from RTD3.

BUG=b:244077118
TEST=check cbmem -c
\_SB.PCI0.RP06: Enable RTD3 for PCI: 00:1c.5 (Intel PCIe Runtime D3)
\_SB.PCI0.RP06: Enable WWAN for PCI: 00:1c.5 (Fibocom FM-350-GL)

check PXSX Device is generated in ssdt.

Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I6114c589769d2eca882cf1a5255cf4c5937121a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-20 07:56:22 +00:00
Ian Feng d4eb998fc1 mb/google/nissa/var/xivu: Add supported new memory part
Add new ram_id:3 (0011) for memory part K3LKCKC0BM-MGCP.

DRAM Part Name                 ID to assign
K3LKCKC0BM-MGCP                3 (0011)

BUG=b:247039096
TEST=Use part_id_gen to generate related settings and
emerge-nissa coreboot

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I78d2e501b9d8d801a3d149002f638125bf4275f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-09-20 07:54:55 +00:00
Angel Pons 082d822861 cpu/intel/haswell: Update Broadwell ULT µcode updates
The µcode updates for Broadwell come from coreboot's blobs submodule
and have not been updated in at least 7 years. Use the µcode updates
available in the intel-microcode submodule. This change forgoes some
µcode updates for old Broadwell ULT/ULX steppings with CPUID 0x306d2
and 0x306d3, as well as an old µcode update for Haswell ULT/ULX CPUs
with CPUID 0x40651 in favor of a newer intel-microcode revision that
was already being used: when the µcode updates are concatenated into
one file, the newer µcode update revision would be placed before the
older revision, so the latter would never be used.

Change-Id: I67f8a58552bd211095c183e6f7a219d60e3be162
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-20 07:53:57 +00:00
Angel Pons 84d0fe5113 cpu/intel/haswell: Hook up Crystal Well µcode updates
Commit 27126f135d (cpu/intel/haswell: add
Crystal Well CPU IDs) introduced new Haswell CPUIDs but did not include
any µcode updates for them. It is unknown how this could have worked as
the initial µcode inside the CPU can be quite unstable. Intel CPUs with
support for FIT (Firmware Interface Table) can have their µcode updated
before the x86 reset vector is executed.

The µcode updates for Crystal Well CPUID 0x40661 can be found inside the
intel-microcode submodule. There are no publicly available µcode updates
for Crystal Well CPUID 0x40660 as it is a pre-production stepping, which
is not meant to be used anymore. Hook up the available µcode updates for
Crystal Well CPUs.

Change-Id: If5264f333e681171a2ca4a68be155ffd40a1043b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-20 07:52:59 +00:00
Angel Pons 1caa279325 cpu/intel/haswell: Do not include useless µcode updates
There are two types of Haswell/Broadwell platforms: Trad(itional) with
separate CPU and PCH packages, and ULT/ULX where the CPU and PCH share
one package. Mainboards can specify which platform type they are using
the `INTEL_LYNXPOINT_LP` Kconfig option. There are so many differences
between Trad and ULT/ULX that it's not worth doing runtime detection.

The CPUIDs are different for Trad and ULT/ULX platforms, and so are the
µcode updates. So, including Trad µcode updates in a coreboot image for
an ULT/ULX mainboard makes no sense, and vice versa.

Adapt the Makefile so that only relevant µcode updates are added. Also,
add a few comments to indicate which updates correspond to which CPUs.

TEST=Run binwalk on coreboot.rom to verify included µcode updates for:
     - Asrock B85M Pro4 (Haswell Trad)
     - HP Folio 9480M (Haswell ULT/ULX)
     - Purism Librem BDW (Broadwell ULT/ULX)

Change-Id: I6dc9e94ce9fede15cbcbe6be577c48c197a9212a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-20 07:51:20 +00:00
Tim Wawrzynczak 0d3606b2df mb/intel/mtlrvp: Add board_info.txt
Builds are failing on upstream master branch because there is no
board_info.txt for the Intel Meteor Lake RVP mainboard; this patch
adds a basic one so the tree will build.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I3356ad65132dc4aaebd5e7d959a2bdb9ab1316b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67711
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-09-19 20:29:40 +00:00
AlanKY Lee 23b68fe78d mb/google/brya/var/skolas: Add MIPI WFC support
Modify config settings based on new module KBAE350 spec

BUG=b:245640845
BRANCH=None
TEST=Build and boot on skolas

Signed-off-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com>
Change-Id: I8a9bee9bb79bda4e3f1d259716844b42a7fce397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jimmy Su <jimmy.su@intel.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-09-19 18:59:27 +00:00
Arthur Heymans e247435c6b soc/intel/apollolake: LZ4 Compress FSP-M
FSP-M is not run XIP so it can be compressed. This more than halves
the binary size. 364544 bytes -> 168616 bytes.

On the up/squared this also results in a 83ms speedup.

TESTED: up/squared boots.

Change-Id: Ic76b51f0f3007b59ccb9f76b6a57bb9265dab833
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-09-19 14:57:30 +00:00
Arthur Heymans 6317aff5b3 Kconfig: Allow x86 to compress pre-ram stages if not run XIP
On the intel/glkrvp
compressed:
- romstage: 29659
- verstage: 31303
non compressed:
- romstage: 46244
- verstage: 47012

On qemu (with some additional patch to not run XIP)
compressed:
- romstage: 11203
non compressed:
- romstage: 13924

Even with a small romstage the size improvements are substantial,
which should result in a speedup when loading the stage. On the
up/squared loading romstage is sped up by 9ms.

TESTED: successfully boot the up/squared & google/vilboz.

Change-Id: Iac24d243c4bd4cb8c1db14a8e9fc43f508c2cd5d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-09-19 14:57:12 +00:00
Jamie Ryu b6cce33b18 mb/intel/mtlrvp: Add flashmap descriptor
This adds 32MB flashmap descriptor as below:

Descriptor Region: 0x0 - 0x3fff (~16KB)
Intel EC Region: 0x4000 - 0x83fff (~512KB)
ME Region: 0x84000 - 0x8fffff (~8.5MB)
BIOS Region: 0x900000 - 0x01ffffff (~23MB)

BUG=b:224325352
TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Ifb572efe56eb7400b8328ba797892738f5927158
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66098
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 14:56:11 +00:00
Sean Rhodes 9f44a8cc39 soc/intel/apollolake: Add bits of GEN_PMCON2 register
The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie7d40395d754b2abdf9079d6ee5e8ab8c536d449
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67661
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 14:55:29 +00:00
Sean Rhodes 7ef5376123 soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown
Configure FSP S UPDs to allow coreboot to handle the lockdown.

The main change here is setting `Write Protection Support` to 0,
as the default is Enabled, which shouldn't allow writes (even though
it seems to).

The UPDs are identical on APL and GLK, but all ones configured
in this patch have been there since their initial releases.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I35185b498315511f3236758caebfe2f9c28fd04a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65039
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 14:55:23 +00:00
Angel Pons d669562663 mb/prodrive/hermes: Add part numbers to SMBIOS
Adjust the EEPROM layout to account for two new fields: board part
number and product part number. In addition, put them in a Type 11
SMBIOS table (OEM Strings).

TODO: This currently stores the "raw" part numbers, should we add a
prefix to the SMBIOS strings?

Change-Id: I85fb9dc75f231004ccce2a55ebd9d7a4867fcb93
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67276
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 14:53:01 +00:00
Tim Van Patten 1075fef445 amd/mendocino/root_complex: Throttle SOC during low/no battery
Use dynamic power and thermal configuration (DPTC) via ACPI ALIB calls
to throttle the SOC when there is no battery or critically low battery,
to enable the SOC to boot without overwhelming the AC charger and
browning out.

DPTC is not enabled for low/no battery mode with this CL. It will be
enabled for Skyrim in a following CL.

BRANCH=none
BUG=b:217911928
TEST=Boot skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ifeddb99e97af93b40a5aad960d760e4c101cf086
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67189
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 10:00:51 +00:00
Tim Van Patten d8210d6ee1 amd/mendocino/acpi/soc: Add DPTC Support
Add support for DPTC by calling SB.DPTC() as part of PNOT().

BRANCH=none
BUG=b:217911928
TEST=Boot skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ifc332bfc4d273031c93b77673224b4f3c2871fb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67694
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:57:12 +00:00
Tim Van Patten 7a6451bd3e skyrim/overridetree: Add "Throttle" DPTC values
Add the Low/No Battery Mode DPTC values for Skyrim.

These values were generated by AMD.

BRANCH=none
BUG=b:217911928
TEST=Build skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I5f277761cb7379b4344492f95010d8d5ddd689fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67693
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:56:34 +00:00
Tim Van Patten 1cf0acdc1c soc/amd/mendocino: Add low/no battery VRM limit registers
Add DPTC Low/No battery VRM limit registers to throttle the SOC.

BRANCH=none
BUG=b:217911928
TEST=Build skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I9c4ed227b54efbab9f03d6acf64b1160ad73f460
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67692
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:56:06 +00:00
Tim Van Patten 11ca995500 amd/mendocino/root_complex: Set DPTC VRM limit values
Set the DPTC VRM limit values for normal mode.

BRANCH=none
BUG=b:217911928
TEST=Boot skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I2041a713323f039dcfdacdfa43e74cf450c3c0d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67691
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:55:20 +00:00
Tim Van Patten cf9e0a08f5 mb/google/skyrim: Add "Normal" DPTC values
Add the Normal Mode DPTC values for Skyrim.

These values were generated by AMD.

BRANCH=none
BUG=b:217911928
TEST=Build skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I1e1f55b941f3e70aad33d55a90fb012eac3ba12d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67690
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:54:40 +00:00
Tim Van Patten b06873f77c soc/amd/mendocino: Add VRM limit DPTC registers
Add VRM DPTC limit registers. These are required when throttling the SOC
for low/no battery mode to prevent the SOC from overwhelming the
charger.

b/245942343 is tracking passing these additional fields to the FSP and
having the FSP configure them.

BRANCH=none
BUG=b:217911928
TEST=Build skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ie62129d967192f9a9cf654b1854d7dbe4324802a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67378
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:54:00 +00:00
Tim Van Patten a90aebbf2a soc/amd/acpi: Add low/no battery mode to DPTC
Update acpigen_write_alib_dptc() to support "low/no battery mode",
which throttles the SOC when there is no battery connected or the
battery charge is critically low.

This is in preparation for enabling this functionality for Mendocino.

BUG=b:217911928
TEST=Build zork
TEST=Boot nipperkin
TEST=Boot skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Icea10a3876a29744ad8485be1557e184bcbfa397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66804
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:53:17 +00:00
Jan Dabros 2d9e96a5ab soc/amd/mendocino/acpi: Add support for shared TPM_I2C controller
There are platforms equipped with AMD SoC where I2C3 controller
connected to TPM device is shared between X86 and PSP. In order to
handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends
acquire and release requests to be accepted by PSP.

Introduce new CONFIG for Mendocino SoCs similar to what we have for
Cezanne.

BUG=b:241878652
BRANCH=none

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I015a24715271d2b26c0bd3c9425e20fb2987a954
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-19 09:52:25 +00:00
Subrata Banik e8097f7a28 mb/google/rex: Add ELAN6918 touchscreen
ELAN6918 Power Sequencing seems not perfectly matching
with the previous platforms and setting GPP_C06 to high prior
to the power sequencing is actually makes it work.

Ideally Power Sequencing should be as below for ELAN6918 (in ACPI)
`POWER enabled -> RESET deasserted -> Report EN enabled`

But below sequence is only working currently:
`Report EN enabled (ramstage) -> POWER enabled (ACPI) -> RESET
 deasserted (ACPI)`

BUG=b:247029304
TEST=Verified ELAN touch panel is working as expected after booting
Google/rex device to ChromeOS.

Change-Id: Ideaeb0faa882b8e603534bbface51ea76923d436
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-19 09:50:58 +00:00
Nick Vaccaro dbe4fe2c88 mb/google/brya/var/brya4es: deprecate brya4es
The brya4es variant is no longer needed, removing code for brya4es.

BUG=b:246611270
TEST=None

Change-Id: I9b222f89fe766c63158518713be19d7959451721
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-19 09:49:06 +00:00
Werner Zeh 57ed348b20 mb/siemens/mc_apl1: Do not wait for legacy devices on mc_apl7
Since there are no legacy devices on the variant mc_apl7 do not wait
for them on mc_apl7.

Change-Id: Ia4e6c0fb495a347be51bd6604a1d9b73098fb7b6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67684
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:48:27 +00:00
Elyes Haouas c8870b1334 crossgcc: Upgrade llvm from version 14.0.6 to 15.0.0
Test build for QEMU x86 i440fx/piix4.

Change-Id: I3144a83fcbd92eec51d70e9be33ff2fcb2821731
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67416
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-18 17:14:10 +00:00
Elyes Haouas 035e9f9f0c crossgcc: Upgrade cmake from 3.23.2 to 3.24.2
Change-Id: I81a8371190513ca34d3c5efb0e3770ac3d873b03
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-18 17:14:04 +00:00
Yidi Lin 0811a6492d cbmem: use aligned_memcpy for reading lb_cbmem_entry information
The lbtable contains the memory entries that have fields unnaturally
aligned in memory. Therefore, we need to perform an aligned_memcpy() to
fix the issues with platforms that don't allow unaligned accesses.

BUG=b:246887035
TEST=cbmem -l; cbmem -r ${CBMEM ID}

Change-Id: Id94e3d65118083a081fc060a6938836f6176ab54
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-18 03:24:16 +00:00
Patrick Georgi f0d5f67e46 riscv: Enable the newfangled way of selecting instruction sets
gcc12+ will require riscv architecture selection to come not only with
featurei suffixd charactersa, it also comes with feature_ful suffix_ed
words_mith. Much creative, very appreciate.

To accommodate for this madness, enable the already existing (but off by
default) support for that in our gcc11 build, support using by detecting
the compiler's behavior in xcompile and pass that knowledge along to our
build system.

Then cross our fingers and hope for the best!

Change-Id: I5dfeed766626e78d4f8378d9d857b7a4d61510fd
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-17 05:56:34 +00:00
Miriam Polzer 2c38933a0e security/vboot: Add rollback NVRAM space for TPM 2
Create an NVRAM space in TPM 2.0 that survives owner clear and can be
read and written without authorization. This space allows to seal data
with the TPM that can only be unsealed before the space was cleared.
It will be used during ChromeOS enterprise rollback to securely
carry data across a TPM clear.

Public documentation on the rollback feature:
https://source.chromium.org/chromium/chromiumos/platform2/+/main:oobe_config/README.md

BUG=b/233746744

Signed-off-by: Miriam Polzer <mpolzer@google.com>
Change-Id: I59ca0783b41a6f9ecd5b72f07de6fb403baf2820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-09-17 01:42:11 +00:00
Husni Faiz f634aed758 console: attach smbus console driver
This patch attaches the smbus console functions to the high
level console interface.

Change-Id: I3a9bf64e59d529253bfdcdfa565bb2bb92975728
Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67341
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-16 17:03:49 +00:00
Husni Faiz f571ce5c67 bd82x6x/early_pch: enable smbus in bootblock stage
SMBus is typically enabled in the ROMSTAGE. To get the
BOOTBLOCK console message, the SMBus should be enabled
in the BOOTBLOCK stage.

Change-Id: I97d0afb013ede428383acaa0aa97ab04fe80e2a4
Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67340
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-16 17:02:39 +00:00
Husni Faiz 67300f88cd drivers/smbus: add smbus console driver
This patch adds a new smbus console driver and Kconfig
options to enable the driver.

Change-Id: Ife77fb2c3e1cc77678a4972701317d50624ceb95
Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67339
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-16 17:01:17 +00:00